CN100465910C - Method for error protecting and error correcting of flash memory data in products - Google Patents
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- CN100465910C CN100465910C CNB2006100272622A CN200610027262A CN100465910C CN 100465910 C CN100465910 C CN 100465910C CN B2006100272622 A CNB2006100272622 A CN B2006100272622A CN 200610027262 A CN200610027262 A CN 200610027262A CN 100465910 C CN100465910 C CN 100465910C
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Abstract
The invention discloses a defending and correcting method of flash memory data in the product, which comprises the following steps: (1) writing initialization program and record data into the condition set program of flash memory for TTPCOM project; setting step a0: starting to write data to link S12 and a1; (2) inserting S8-2 and S8-1, S9, S10 and S11 between initialization program S8 and S2 and between S8 and S12; judging whether 'last recorded address' in the S8-1 lies in the preset scale; executing S8-2 if not; erasing active segment data; returning to S2; executing S9 if yes; detecting the prepared segment data; executing S10 to judge whether the prepared segment data is whole '1'; executing S11 to erase the prepared data segment data if not; executing S12; otherwise, executing S12 directly; (3) inserting step d between step c and step e to detect whether the written data in the area is whole '1' in the flash memory; inserting step g between step f and step h to detect whether the correction before and after writing data equals. The invention reduces the error rate of flash memory data from 40% to 1%.
Description
Technical field
The present invention relates to the method that a kind of data that prevent to preserve in the product storage element device flash memory are made mistakes by ectocine, more particularly, is about improving the antijamming capability of flash memory in the product, to the mistake proofing of its storage data, the method for error correction.
Background technology
In the operational process of technical grade product, the data of being preserved in product storage element device (Memory) flash memory (FLASH) are usually owing to the influence of external environment (just common " race the flies ") phenomenon of makeing mistakes.These external environments comprise: factor such as electromagnetic radiation, temperature variation, voltge surge and frequent energising, outage causes some " position " among the FLASH (bit) to become " 0 " by " 1 ", thereby causes that product can not normally move.The serious product that also can cause can not be started shooting, and forms in " waste product ", has increased repair rate, influences the reputation of product.
Be example with the memory component (FLASH, flash memory) that is applied in the GSM communication module (GSM Wireless Module) now, the solution of these series of products is as follows:
A. hardware plan adopts the chipset of ADI (Analog Deviec Incorporstian ADI), wherein digital device adopts AD6525+ARM7TDMI: analog device adopts AD6533, and memory device partly adopts Inte MCP (Intel3208);
B. software scenario adopts the platform based on the KADAK embedded OS that Britain TTPCOM company provides.
In solution, be following 2 points to the operational overview of FLASH to product:
1, system is the FLASH logical mappings four different zones: program code area (CODEAPEA) 11, file system area 12 (FILESYSTEM), user data area (NVRAMDATA) 13, reserved area (RESERVATIONAPEA) 14.All there is certain space in each zone, is 64kb such as file system area 12, and user data area 13 is 512kb etc., and the start address of FLASH is 0x01000000, as Figure 1-1
2, carry out in the logical mappings structure of Fig. 1-1, user data area (NVRAMDATA) the 13rd needs frequently to carry out the zone of reading and writing and erase operation in the communication module course of work.For the number of times of the reading and writing that prolong FLASH and the principle of acting on " space of user data area can not be consumed to the greatest extent ", Britain TTPCOM company logically has been divided into four different sections (SEGMENG) again with the flash memory spare FLASH in NVRAM zone, each section comprises the sector (BLOK) of identical size, and detailed structure is shown in Fig. 1-2.
Wherein, activity data section (ACTIVE SEGMENT) 131 can be exchanged with the data of preliminary data section (AVAILABLESEGMENT) 132.Wherein, ACTIVE SEGMENT is the data segment that program is being used, and ACTIVE SEGMENT is the section that is used for data backup: after the data of ACTIVESEGMENT have been filled up whole section space, program can copy active data to AVAILABLE SEGMENT, and its process as Figure 1-3.
Colour bar representative among Fig. 1-3 be the defined data record of Britain TTPCOM company, its data structure is shown in Fig. 1-4.
All data recording all are to write in the user area 13 according to the state machine shown in Fig. 1-5 (State Machine).
Above-mentioned FLASH logical organization and operating process under normal circumstances can not go wrong.But, from the application result of the employed product mobile phone of patent applicant of the present invention, the phenomenon of " FLASH run fly " relatively more serious (ratio be reprocess product about 40%).The error data of preserving among the FLASH roughly can reduce Fig. 1-6 with shown in Fig. 1-7.
Why such situation can appear? through research back discovery repeatedly, these data of makeing mistakes (position) all are to have become " 0 " by " 1 ", and in abominable industrial control condition, the electric property of FLASH components and parts has no idea to be guaranteed, and such situation occurs as Intel support engineer's said " also being understandable " after sale.
Below, further analyze the scheme of Britain TTPCOM company in the FLASH initialization procedure again, shown in Fig. 1-8.
This initialization flow process is not checked preliminary data section 131, so, do you can cause which type of result? because the data (position) among the FLASH (flash memory) are in " writing " operation, PROGRAMME can only be write as " 0 " by " 1 ", but can not be write as " 1 " by " 0 ", therefore, if should become " 0 " by " 1 " in the zone, when operating, " writing " just have no idea to be write as again " 1 ".
Summary of the invention:
In sum, how to overcome the puzzlement of using flash memory (FLASH) often to make mistakes in the existing product because of the influence that is subjected to external environment in the operational process as the storage element device, it is technical matters to be solved by this invention, for this reason, the object of the present invention is to provide a kind of mistake proofing, error correction method to flash data in the product.
Realize purpose technical conceive of the present invention be according to the data bit in the flash memory when " writing " operates, can only be write as " 0 " by " 1 " and can not be formulated technical scheme by the characteristic that " 0 " is write as " 1 ", and in view of the above, by what Britain TTPCOM company designed flash memory is carried out initialize routine to existing, and the improvement that writes the employed state machine program of data recording structure of flash memory.
Overview is got up, and technical scheme of the present invention is:
1, according to a kind of flash memory initial method to the flash data mistake proofing in the product of the present invention, its step comprises: S
1Hardware restarts; S
2The initialization flash memory; S
3Whether the zone bit of first data segment of judging the user data area of flash memory is active, if zone bit is active, carries out S
4, otherwise carry out S
5S
4Second data segment of the user data area of flash memory is changed to standby, carries out S
8S
5Whether the zone bit of second data segment of judging the user data area of flash memory is active, if zone bit is active, carries out S
6, otherwise carry out S
7S
6This first data segment is changed to standby, carries out S
8S
7This first data segment is arranged to active, this second data segment is arranged to standby, and wipes the data of activity data section; S
8All data of traversal activity data section, and S
12The flash memory initialization finishes; Characteristics are, at step S
8And S
12Between insert following steps: S
9Check the data of preliminary data section; S
10Whether the data of judging the preliminary data section are complete " 1 ", if complete " 1 " directly carries out S
12, otherwise carry out S
11S
11Wipe the data of preliminary data section, carry out S afterwards
12
2, according to a kind of method that data recording is write the state machine of flash memory of the present invention to the flash data mistake proofing in the product, comprise link successively, and head and the tail are closed, form the step of closed loop running: a. init state; B. write recording head information; C. write record status bit; E. write record data; F. write the end of record (EOR) mark; H. the original inefficacy of mark, link step a; Be characterized in, be linked at the steps d between step c and the e in addition. entirely whether the interval that will write in the inspection flash memory " 1 ", and is linked at the step g between step f and the h. the verification that the write data of inspection flash memory is forward and backward and whether equal.
3, according to same total inventive concept, flash memory is carried out initialization scheme and the state machine operating scheme that flash memory writes data recording is merged into an overall plan with original TTPCOM, and it is improved, form a kind of method that flash data in the product is carried out mistake proofing, error correction of the present invention, its step comprises the initialized step of the flash memory of TTPCOM scheme: S
1Hardware restarts; S
2The initialization flash memory; S
3Whether the zone bit of first data segment of judging the user data area of flash memory is active, if zone bit is active, carries out S
4, otherwise carry out S
5S
4First data segment of the user data area of flash memory is changed to standby, carries out S
8S
5Whether the zone bit of second data of judging the user data area of flash memory is active, if zone bit is active, carries out S
6, otherwise carry out S
7S
6This first data segment is set to standby, carries out S
8S
7This first data segment is arranged to active, these second data is arranged to standby, and wipes the data of activity data section; S
8All data of traversal activity data section, and S
12The flash memory initialization finishes; With the TTPCOM scheme flash memory is write the step of the state machine operation of data, this scheme has link successively, and the step of the closed link of head and the tail: a. init state; B. write recording head information; E. write record data; F. write the end of record (EOR) mark; H. the original record of mark lost efficacy, link step a; Characteristics are first. at step S
12And be provided with step a between the step a
0Beginning write data record; Second. at step S
8And S
12Between insert following steps: S
8-1Whether the member variable of judgment data record " last one address of writing down " is in preset range, if not preset range, and just execution in step S
8-2Wipe the activity data section, the S of rebound execution in step again
2The initialization flash memory, if be in preset range, execution in step S then
9Check the preliminary data section, again execution in step S
10S
10Judge whether the preliminary data section is " 1 " entirely, if not being " 1 " just execution in step S entirely
11Wipe the data of preliminary data section, afterwards, execution in step S
12,, then directly carry out S if be " 1 " entirely
12The flash memory initialization finishes; Third. write record status bit and step e. writes between the record data in step c, inserting step d. checks in the flash memory whether the interval censored data that will write is " 1 "; And write the original record of end of record (EOR) mark and the step h. mark step g of pegging graft between losing efficacy at step f.. check verification that write data in the flash memory is forward and backward and whether equal.
Advantage of the present invention is a practical proof, has obtained good effect, and error rate has become present about 1% by original about 40%.
Description of drawings
Fig. 1-the 1st, the logical mappings structural representation of flash memory (FLASH) in the existing GSM communication module;
Fig. 1-2 is the plot structure synoptic diagram of the user data in the flash memory logical mappings structure in the existing GSM communication module;
Fig. 1-the 3rd, active several sections and preliminary data section exchange operation chart in the user data area in the existing GSM communication module in the flash memory logical mappings structure;
Fig. 1-the 4th, the structural representation of flash data record in the existing GSM communication module;
Fig. 1-the 5th, data write the state machine diagram of flash memory in the existing GSM communication module;
Fig. 1-the 6th, " race flies " schematic diagram data takes place in data in the existing GSM communication module;
Fig. 1-the 7th, another synoptic diagram of " race flies " data takes place in data in the existing GSM communication module;
Fig. 1-the 8th, existing software platform is to the initialize routine process flow diagram of flash memory in the GSM communication module;
Fig. 2-the 1st, the present invention is to the initialize routine process flow diagram of flash memory in the existing GSM communication module;
Fig. 2-the 2nd, the present invention write the state machine diagram of flash memory to flash data in the existing GSM communication module; And
Fig. 2-3 and Fig. 2-4 is to use the inventive method to solve flash data " race flies " the overall plan process flow diagram of existing GSM communication module.
Embodiment
Provide a better embodiment of the present invention according to Fig. 2-1-Fig. 2-3 below, and described in detail,, rather than be used for limiting scope of the present invention so that those skilled in the art can be easier to understand the feature and the function characteristics of the inventive method.
See also Fig. 2-1, its improvement project that to be the present invention propose existing Britain TTPCOM company to the initialize routine of flash memory in the product (FLASH).Flash memory initialize routine 200 shown in Fig. 2-1, its improvements than the existing flash memory initialize routine 100 shown in Fig. 1-8 are to set up the step of carrying out successively 2001 (checking the data of preliminary data section 131) between all data of step 1007 traversal activity data section and step 1008 (flash memory initialization end), are (data of judging preliminary data 131 " 1 " to step 2002 entirely? if) be " 1 " entirely, execution in step 1008; Otherwise execution in step 2003 (wiping the data of preliminary data section 131).As described in the background art; Use the flash memory initialize routine 100 that provides as the described former Britain of Fig. 1-8 TTPCOM company, because this firstization program is provided with preliminary data section 131 is checked, if data that should the zone become " 0 " by " 1 ", when " writing " operates, just have no idea to be write as again " 1 ", for mistake proofing, whether the data that just must check preliminary data section 131 when initialization are " 1 " entirely, if not being " 1 " entirely, just must carry out " wiping " operation to it, are complete complete " 1 " with the data that guarantee this section.
See also Fig. 2-2, it is that the present invention carries out the state machine improvement project synoptic diagram that data write to the flash memory in the existing product, the state machine diagram difference that existing software platform shown in itself and Fig. 1-5 writes flash data is to set up step 2501 (check between the interval that will write in the flash memory whether complete " 1 ") between step 1503 (writing record status bit) and step 1504 (writing record data), and sets up step 2502 (in the inspection flash memory before the write data between step 1505 (writing the end of record (EOR) mark) and step 1506 (the original record of mark lost efficacy), after verification and whether equate).
Because the structure of the data recording in the product all is to write in the user area 13 according to the described state machine of Fig. 2-2, therefore, improvement project according to Fig. 2-1 and Fig. 2-2, can prevent that the data that write flash memory from makeing mistakes, promptly the data that the preliminary data section is checked in the back before data copy the preliminary data section to from the activity data section whether entirely for " 1 ", can prevent that just copy procedure from causing the data that deposit in to make mistakes.
But attention: will use an important structure variable in the flash memory ergodic data initialization procedure: the address of a last record (shown in Fig. 1-4).If this variable is made mistakes, then produce " race flies " phenomenon, as Fig. 1-6, shown in Fig. 1-7, can cause the product can not normal boot-strap, treating method be: exceeded pre-degree scope in case detect the value of this tolerance, come again the initialization procedure of flash memory after the data formatting (wiping) with active section.
See also Fig. 2-3, it is that enforcement is of the present invention to the flash data mistake proofing in the product, the method flow diagram of error correction, as shown in the figure, it comprises the state machine program 150 that flash memory initialize routine 100 shown in Fig. 1-8 and the data recording shown in Fig. 1-5 write flash memory, characteristics are: the step 1007 of a. in initial program 100, all data and steps 1008 of traversal activity data section, the flash memory initialization is set up execution in step 2004 successively between finishing, whether the member variable " address of a last record " of judging record is in preset range, if not preset range, execution in step 2005, the data of wiping active section, rebound execution in step 1001, rebound initialization internal memory, if preset range, then execution in step 2001, check the data of dead section, does execution in step 2002 judge whether the data of dead section data segment are " 1 " entirely? if not complete " 1 ", execution in step 2003, wipe the data of preliminary data section, execution in step 1008; Complete if " 1 ", then direct execution in step 1008, the flash memory initialization finishes; B. the step 1503 in state machine program 150 writes record status bit, with step 1504, writes and sets up step 2501 between the record data, and entirely whether the interval that will write in the inspection flash memory " 1 "; And in step 1505, write the end of record (EOR) mark, and between the original record of step 1506 mark lost efficacy, set up step 2502, check in the flash memory before the write data, after verification and whether equal.
Claims (3)
1, a kind of flash memory initial method to the flash data mistake proofing in the product, it comprises step successively:
S
1. hardware restarts;
S
2. the initialization flash memory;
S
3. whether the zone bit of first data segment of judging the user data area of flash memory is active, if zone bit is active, carries out S
4, otherwise carry out S
5
S
4. second data segment of the user data area of flash memory is changed to standby, carries out S
8
S
5. whether the zone bit of second data segment of judging the user data area of flash memory is active, if zone bit is active, carries out S
6, otherwise carry out S
7
S
6. this first data segment is changed to standby, carries out S
8
S
7. this first data segment is arranged to active, this second data segment is arranged to standby, and wipes the data of activity data section;
S
8. all data of traversal activity data section, and
S
12. the flash memory initialization finishes; It is characterized in that, at step S
8And S
12Between also have following steps:
S
9. check the data of preliminary data section;
S
10. whether the data of judging the preliminary data section are complete " 1 ", if complete " 1 " directly carries out S
12, otherwise carry out S
11
S
11. wipe the data of preliminary data section, carry out S afterwards
12
2, a kind of method that data recording is write the state machine of flash memory to the flash data mistake proofing in the product comprises link successively, and the step of head and the tail closure:
A. init state;
B. write recording head information;
C. write record status bit;
E. write record data;
F. write the end of record (EOR) mark;
H. the original record of mark lost efficacy, link step a; It is characterized in that, be linked at the steps d between step c and the e in addition. check the interval that will write in the flash memory whether complete " 1 ", and be linked at the step g between step f and the h. check verification that write data in the flash memory is forward and backward and whether equal.
3, a kind of mistake proofing to the flash data in the product, error correction method comprise the initialized step of flash memory of TTPCOM scheme and flash memory are write the step of the state machine operation of data that the initialized step of the flash memory of TTPCOM scheme is: S
1. hardware restarts; S
2. the initialization flash memory; S
3. whether the zone bit of first data segment of judging the user data area of flash memory is active, if zone bit is active, carries out S
4, otherwise carry out S
5S
4. second data segment of the user data area of flash memory is changed to standby, carries out S
8S
5. whether the zone bit of second data segment of judging the user data area of flash memory is active, if zone bit is active, carries out S
6, otherwise carry out S
7S
6. this first data segment is changed to standby, carries out S
8S
7. this first data segment is arranged to active, this second data segment is arranged to standby, and wipes the data of activity data section; S
8. all data of traversal activity data section, and S
12. the flash memory initialization finishes;
The step that flash memory is write the state machine operation of data of TTPCOM scheme is: a. init state; B. write recording head information; C. write record status bit; E. write record data; F. write the end of record (EOR) mark; H. the original record of mark lost efficacy, link step a; It is characterized in that:
First. at step S
12And be provided with step a between the step a
0. beginning write data record;
Second. at step S
8With S
12Between insert following steps: S
8-1. whether the record member variable of judgment data " address of a last record " is in preset range, if not being in preset range, just carries out S
8-2. wipe the activity data section, again rebound S
2. the initialization flash memory, if be in preset range, then carry out S
9. check the preliminary data section, carry out S again
10S
10. judge whether the preliminary data section is complete " 1 ", if not, S just carried out
11. wipe the preliminary data segment data, afterwards, carry out S again
12,, then directly carry out S if be " 1 " entirely
12. the flash memory initialization finishes;
Third. write record status bit and step e. in step c and write that inserting step d. checks whether the data in the interval that will write in the flash memory are " 1 " entirely between the record data; And step f. write the original record of end of record (EOR) mark and step h. mark lost efficacy between inserting step g. check and write the forward and backward verification of data and whether equal in the flash memory.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100272622A CN100465910C (en) | 2006-06-02 | 2006-06-02 | Method for error protecting and error correcting of flash memory data in products |
Applications Claiming Priority (1)
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|---|---|---|---|
| CNB2006100272622A CN100465910C (en) | 2006-06-02 | 2006-06-02 | Method for error protecting and error correcting of flash memory data in products |
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| CN100465910C true CN100465910C (en) | 2009-03-04 |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101872318B (en) * | 2009-04-22 | 2012-10-24 | 群联电子股份有限公司 | Data access method for flash memory and storage system and controller thereof |
| CN101710297B (en) * | 2009-12-17 | 2015-05-06 | 北京中星微电子有限公司 | Method for running application and controller |
| TWI440039B (en) * | 2010-09-07 | 2014-06-01 | Ind Tech Res Inst | Flash memory controller and the method thereof |
| CN104657192A (en) * | 2013-11-20 | 2015-05-27 | 上海华虹集成电路有限责任公司 | Method for simulating flash on simulator |
| CN110459259A (en) * | 2019-07-31 | 2019-11-15 | 至誉科技（武汉）有限公司 | Store test method, system and the storage medium of equipment write error error correcting capability |
| CN110444247A (en) * | 2019-07-31 | 2019-11-12 | 至誉科技（武汉）有限公司 | Store the test device of equipment write error error correcting capability |
| CN117407928B (en) * | 2023-12-13 | 2024-03-22 | 合肥康芯威存储技术有限公司 | Storage device, data protection method for storage device, computer apparatus, and medium |
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