CN100446241C - Semiconductor device capable of holding large size chip and producing method and relative carrier thereof - Google Patents

Semiconductor device capable of holding large size chip and producing method and relative carrier thereof Download PDF

Info

Publication number
CN100446241C
CN100446241C CNB2005100807346A CN200510080734A CN100446241C CN 100446241 C CN100446241 C CN 100446241C CN B2005100807346 A CNB2005100807346 A CN B2005100807346A CN 200510080734 A CN200510080734 A CN 200510080734A CN 100446241 C CN100446241 C CN 100446241C
Authority
CN
China
Prior art keywords
substrate
colloid
hypotenuse
chip
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2005100807346A
Other languages
Chinese (zh)
Other versions
CN1889260A (en
Inventor
蔡云隆
蔡育杰
陈建志
黄建屏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to CNB2005100807346A priority Critical patent/CN100446241C/en
Publication of CN1889260A publication Critical patent/CN1889260A/en
Application granted granted Critical
Publication of CN100446241C publication Critical patent/CN100446241C/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

The present invention refers to semiconductor device capable of holding large size chip, making method and carrier for said semiconductor device. Said device includes closing unit with guide angle and package piece. Said method contains forming one hypotenuse opening on substrate precalculated position, adhering said chip and passive device and connected to said substrate, then forming said chip and passive device covered and stop angle having colloid, colloid stop angle having distance with hypotenuse opening, cutting said colloid in current mode to form package piece with guide angle, finally embedding package piece in closing unit.

Description

Semiconductor device and method for making thereof that can ccontaining large size chip
Technical field
The invention relates to a kind of semiconductor device and method for making thereof, particularly encapsulate a plurality of chips as the semiconductor device and the method for making thereof of storage card and the part that carries that is used for this semiconductor device about a kind of.
Background technology
Existing multi-chip module storage card (MMC) is as the 6th, 040, No. 622 United States Patent (USP) discloses, please refer to Figure 1A, this multi-chip module storage card 1 is embedded in the lid 11 by a packaging part 10 and constitutes, and the electric connection pad of substrate 100 bottom surfaces of this packaging part 10 (Conductive Pads or Gold Fingers) 101 exposes in the atmosphere, simultaneously, this multi-chip module storage card 1 has lead angle 13 (Chamfer), is used for the identification of service orientation.
Refer again to Figure 1B, this packaging part 10 that is embedded in the substrate 11 comprises: substrate 100; A plurality of passive devices (Passive Components) 102 connect and place precalculated position on the substrate 100; Flash chip (Flash Memory Chip) 103 and control chip (Controller Chip) 104; Many gold threads 105 and 106 electrically connect this flash chip 103 and control chip 104; And colloid 107, be formed on this substrate 100, coat this passive device 102, flash chip 103, control chip 104 and gold thread 105,106.
When avoiding molding operation (Molding) to carry out, the resin compound (Resin Compound) that the forms colloid 107 usefulness electric connection pad 101 of glue (Flash) to the bottom surface 100a of substrate 100 that can overflow, universal mode is that order is formed at the colloid 107 on this substrate 100 at present, only cover the interior part 110 (Inner Portion) of the end face 100b of substrate 100, the end face 100b that makes this substrate 100 exposes outside colloid 107 around the outer part 120 (Outer Portion) of part in this.Thereby when carrying out molding operation, this outer part 120 can be avoided resin compound to overflow glue on the electric connection pad 101 of substrate bottom surface, shown in figure IC by mould 12 clamping (Clamp) effectively.Though this glue that overflows of when molding operation carries out, the mode of substrate 100 clampings effectively being avoided, but, in order to supply mould 12 clamping effectively, the outer part of this substrate 100 at least must wide about 1mm, make this outer part must take a part of area of standard size substrate 100 end face 100b, cause to reduce for the area of chip and passive device storing on the substrate 100.
In addition, shown in Fig. 1 D, on the substrate 100 that this multi-chip module storage card 1 uses, represent edge line after colloid 107 forms with imaginary line d, the part that the end face 100b of substrate 100 is positioned at this imaginary line d is above-mentioned part 110, is positioned at the outer part of this imaginary line d and is said external and divides 120.The zone of containing with the oblique fracture line is gum-injecting port (Gate), and the mould that is made of resin compound is flowed through, and this injects the zone that imaginary line d corral goes out and forms colloid.Because chip 103,104 and passive device 102 (being represented by dotted lines) are to the resistance shelves of mould stream, be easy to generate gas hole (Void) in the formed colloid, for avoiding the generation in gas hole, present way is that the setting area with chip and passive device dwindles, the zone that between two parallel imaginary line e-e of setting area and mould flow path direction (among the figure shown in the arrow), limits, make mould stream could effectively avoid the formation in gas hole by the zone of imaginary line e and die cavity side.This imaginary line e moves 3mm in the side of substrate, so this mode of reducing chip and passive device setting area, the installation position and the size of chip and passive device have further been limited, under the trend that memory card capacity increases day by day, it is big that the size of flash chip becomes thereupon, the flash chip of big capacity such as 1GB can can't be contained on the aforesaid substrate because of oversize, makes this existing multi-chip module storage card can't satisfy the demand of memory capacity.
Therefore, the 2004/0259291A1 U.S. patent application case has disclosed a kind of do not have the problems referred to above and multi-chip module storage card that can ccontaining large scale flash chip, shown in Fig. 2 A.This multi-chip module storage card why can address the above problem be because, the size of coating chip and passive device (not marking) colloid 20 covers and exceeds the outer coupling part of substrate 21 (being represented by dotted lines), make the coupling part of mould clamping outside substrate 21, so the enforcement of molding operation need not take the end face of substrate 21, make this end face put for large size chip and passive device, and contain area because of colloid 20 and surpass substrate, do not form so do not have the gas hole in the colloid 20.
But the cutting single job (Singulation) and can't adopt traditional cutting (saw Smgulation) equipment of the multi-chip module storage card that this kind substrate 21 is covered by colloid 20 fully, because traditional cutting apparatus can only carry out straight cutting, can't cut out lead angle required on the multi-chip module memory card specifications.Therefore, this multi-chip module storage card only can adopt the shape that water cutter or laser cutting technique cut out to be needed, shown in Fig. 2 B arrow.But the cost height of water cutter or laser cutting and the consumption of cutting process are bigger, are difficult to satisfy the reduce cost requirement of (Cost down) of market.
Summary of the invention
For overcoming above-mentioned existing shortcoming, main purpose of the present invention is to provide restriction that a kind of usable floor area of substrate is not subjected to encapsulation procedure, can be used for fully that chip and passive device place can ccontaining large size chip semiconductor device and method for making thereof.
Another object of the present invention is to provide a kind of can with traditional cutting equipment cut can ccontaining large size chip semiconductor device and method for making thereof.
A further object of the present invention be to provide a kind of packaging cost low can ccontaining large size chip semiconductor device and method for making thereof.
The part that carries that includes at least one this substrate that another purpose of the present invention is to provide the area on a kind of substrate to utilize fully.
For reaching above-mentioned and other purpose, semiconductor device that can ccontaining large size chip provided by the present invention comprises: the lid with lead angle; And connect packaging part on it for this cover cap, wherein, this packaging part comprises: have the substrate to hypotenuse that should the lead angle position; Connect at least one passive device and at least one chip put on this substrate, and this chip is to be electrically connected to this substrate by a plurality of conducting elements; And the colloid that coats this at least one passive device, at least one chip and conducting element, this colloid is formed with the rescinded angle corresponding to this substrate diagonal, make and form the portion of exposing that exposes outside this colloid between the rescinded angle of this substrate diagonal and colloid, except this exposed portion, the surface of this substrate was all covered by colloid.
The method of making above-mentioned semiconductor device comprises the following steps: to prepare the part that carries with at least one perforate, and comprise the substrate of at least one predetermined moulding this year on the part, and a hypotenuse that forms in this substrate and this at least one perforate forms the cut-grafting relation; Sticking at least one passive device and at least one chip put on the zone of substrate of predetermined moulding of this year of part; Electrically connect this chip and this year part; Carry out molding operation, form the colloid that coats this at least one passive device and at least one chip in this year on the part, except that the position corresponding to this year of part perforate hypotenuse, the side that forms colloid must be not less than the side that carries predetermined shaping substrate on the part at least; Colloid after the shaping has a rescinded angle corresponding to the hypotenuse place of perforate on this year part, makes between the hypotenuse of the rescinded angle of this colloid and perforate to be formed with a predetermined distance; The side of being scheduled to the substrate of moulding along this year on the part carries out straight cuts, formation is bearing part and the size packaging part identical with substrate area with the substrate, wherein, the part of the hypotenuse institute cut-grafting of this substrate and perforate promptly forms the hypotenuse of substrate, and the part that is not covered by colloid between the rescinded angle of the hypotenuse of this substrate and colloid becomes the portion of exposing of this substrate; And the cover cap that will have lead angle is connected on this packaging part, thereby forms this semiconductor device, and after this lid and packaging part winding finished, the hypotenuse of this packaging part substrate joined the lead angle of this lid to.
The part that carries that is used for semiconductor device of the present invention comprises: this year, part was the circuit board of rectangular shape, offered at least one perforate on this circuit board, and comprised that at least one has the substrate of hypotenuse, and made the hypotenuse of this substrate coincide with the hypotenuse of this perforate.
In the present invention, except the hypotenuse of substrate exposes outside the part of colloid between the rescinded angle of colloid, the area coverage of this colloid and substrate measure-alike, at this moment, the part edge proper and substrate and colloid that carries confession mould clamping on the part trims and joins, and makes the cutting knife of cutting in the single job only need cut off this carrier, can not cut to colloid, except reducing the wearing and tearing of cutting knife, also can save the use amount of this colloid, reduce packaging cost.But the without hindrance space of avoiding mould stream stopped by chip and passive device ladle-to-ladle phenomenon takes place then must take the space on the substrate, promptly inwardly must respectively reserve the space of 3mm from limit, substrate two opposite sides, and chip and passive device can not be set.At this moment, though can diminish for the area that utilizes on the substrate, when the size of storage chip or similar chip must not take on the substrate than large tracts of land, this structure and method for making also can be suitable under the traditional cutting equipment of use.
Because the moulding of packaging part only must straight cutting in the semiconductor device of the present invention, must not make water cutter or the laser formation lead angle of cutting sth. askew, so use traditional cutting equipment to get final product.Have again, this colloid covers the area that carries on the part area greater than substrate, substrate only has its hypotenuse not covered by colloid to the part between the rescinded angle of colloid, make and carry part exposes outside colloid except this substrate for the position of mould clamping part, all be positioned at outside the substrate, so can not take the area that substrate is used to be provided with chip and passive device, the large size chip as the 1GB flash chip also can be seated on the substrate, meet the demand of high storage capacity.Simultaneously, as mentioned above, this colloid covers the area that carries on the part and surpasses substrate, so avoid mould stream (Mold Flow) to be subjected to chip and passive device to stop that the without hindrance space that ladle-to-ladle phenomenon takes place is positioned at outside this substrate in the molding operation, just the laying of passive device and chip can not influence the flow path of mould stream on the substrate, and the area on the substrate that the present invention uses can be made full use of.
In sum, the invention provides semiconductor device and method for making thereof that a kind of substrate usable floor area is not subjected to encapsulation procedure to limit, be used to place chip and passive device fully, it can use traditional cutting equipment to cut, therefore can reduce packaging cost, the area on the substrate can be utilized fully.
Description of drawings
Figure 1A is the stereogram of existing multi-chip module storage card;
Figure 1B is the cutaway view that Figure 1A cuts open along the B-B line;
Fig. 1 C is the cutaway view of packaging part when carrying out molding operation in the existing multi-chip module storage card shown in Figure 1A;
Fig. 1 D is that packaging part uses the upward view that carries part in the multi-chip module storage card shown in Figure 1A;
Fig. 2 A is that packaging part uses the upward view that is formed with colloid on year part in another existing multi-chip module storage card;
Fig. 2 B is the schematic diagram that the packaging part shown in Fig. 2 A is cut single job;
Fig. 3 A is the stereogram of the semiconductor device of the embodiment of the invention 1;
Fig. 3 B is the cutaway view that Fig. 3 A cuts open along the B-B line;
Fig. 3 C is the stereogram of packaging part shown in Fig. 3 B;
Fig. 4 A to Fig. 4 Gb is the method for making schematic flow sheet of the embodiment of the invention 1 semiconductor device;
Fig. 5 A is the cutaway view of the semiconductor device of the embodiment of the invention 2;
Fig. 5 B is the upward view of the semiconductor device of the embodiment of the invention 2; And
Fig. 6 A to Fig. 6 G is the method for making schematic flow sheet of the semiconductor device of the embodiment of the invention 2.
Embodiment
" hypotenuse of substrate " described in the present invention, " rescinded angle of colloid " and/or " lead angle of semiconductor device ", be not only specificly to be defined as not tool and the straight line position of radian or breakover point, the personnel that have common knowledge in this technology also understand, in order to satisfy different specification demand and function, it can be to have radian, the shape of breakover point genetic system, but in this article, the personage who reads this paper for the succinct and order on narrating can be fast and understanding correctly, will be still with " hypotenuse of substrate " in the accompanying drawing of cooperation so reach hereinafter, " rescinded angle of colloid " and/or " lead angle of semiconductor device " narration.
Embodiment 1
Fig. 3 A be the embodiment of the invention 1 can ccontaining large size chip the stereogram of semiconductor device 3.Fig. 3 B then is the view sub-anatomy of this Fig. 3 A along the B-B line.
This can ccontaining large size chip semiconductor device 3 mainly be to constitute by the lid 31 that packaging part 30 and lid are connected on this packaging part 30.This packaging part 30 is a prior art with combining of lid 31, no longer illustrates at this.
This packaging part 30 comprises: substrate 300; Passive device 301 connects and puts on the upper surface 300a of this substrate 300; Control chip 302 and storage chip 303; Gold thread 304 and 305 electrically connects this control chip 302 and storage chip 303 to substrate; And colloid 306, coat this passive device 301, control chip 302, storage chip 303 and gold thread 304,305, be formed on this substrate 300.
Be formed with a plurality of electric connection pad 300c that expose outside substrate 300 on the lower surface 300b of this substrate 300 with respect to upper surface 300a, for this passive device 301, control chip 302 and storage chip 303 with as external device (not marking) the formation electrical connection of printed circuit board (PCB), this storage chip 303 can be a flash chip.Simultaneously, shown in Fig. 3 C, this substrate 300 has a hypotenuse 300d, corresponding with the rescinded angle 306a that forms on this colloid 306, make the upper surface 300a of this substrate 300 expose outside colloid 306 in the part of the rescinded angle 306a of its hypotenuse 300d and colloid 306, formation exposes the 300e of portion, except the 300e of the portion of exposing of this substrate 300, make this colloid 306 fully the upper surface 300a of substrate 300 be covered, and except rescinded angle 306a, each side 306b of this colloid 306 and each side 300f of this substrate 300 trim and form coplanar relation.
The method for making that forms this semiconductor package part 3 is shown in Fig. 4 A to Fig. 4 Gb.
Shown in Fig. 4 A, at first, prepare a year part 32 with a plurality of perforates 320, these perforate 320 rectangular leg-of-mutton shapes, can or return any existing modes such as (Router) of cutting with punching press (Punch) forms, simultaneously, the hypotenuse 300d of the hypotenuse 320a of this perforate 320 and the substrate 300 (zone among the figure shown in the imaginary line) that carries on the part 32 the predetermined moulding of joining partially overlap (shown in Fig. 3 C) with this perforate 320 respectively.It is noted that at this, the shape of this perforate 320 is not limit right-angled triangle as shown in the figure, also can be obtuse angle, acute angle or equilateral triangle, semicircle or similar shape, as long as the hypotenuse 320a of perforate 320 overlaps the hypotenuse 300d of this substrate 300, and the hypotenuse 320a of perforate 320 can be longer than the hypotenuse 300d of substrate 300, or with moulding after isometric the getting final product of hypotenuse 300d of substrate 300, in order to follow-up cut single processing procedure and finish after, the substrate 300 of moulding is uniquely must not cut at its hypotenuse 300d place, and back conjunction with figs. again further specifies.In addition, when the hypotenuse 300d of this substrate 300 need not be for straight line, this perforate 320 is the straight limit of palpiform not relatively also, but must coincide with the part of these perforate 320 peritremes because of the hypotenuse 300d of this substrate 300, so the peritreme that this perforate 320 overlaps with the hypotenuse 300d of this substrate 300 part must be corresponding to the shape of the hypotenuse 300d of substrate 300, just the hypotenuse 300d of this substrate 300 is an arc, when having the arc of breakover point or having breakover point linear, these perforate 320 pairing peritremes parts also are the arcs that equates, have the arc of breakover point or have the linear of breakover point.
In addition, year part 32 shown in Fig. 4 A is circuit boards of a strip of sheet, the substrate 300 of being scheduled to moulding on year part 32 is linearly to be spaced, this is exemplary structure, this year, part 32 was according to the needs of processing procedure and specification, also can be the rectangular circuit board that 300 one-tenth array way of substrate (Array type) are laid, or large-sized circuit board only supply the single substrate moulding.But carrying the quantity of the substrate 300 of institute's energy moulding on the part 32 and arrangement mode, to be not limited to present embodiment described.
Refer again to Fig. 4 B, glue on the precalculated position in the zone of this year of part 32 predetermined formation substrates 300 and put four passive devices 301, a control chip 302 and a storage chip 303, this last slice operation (Die Bond) is a prior art, no longer illustrates at this.The quantity of this passive device 301 and chip not with present embodiment described with limit that accompanying drawing is depicted as, can decide according to the specification demand, just can only glue the storage chip of putting a large-sized storage chip or two reduced sizes etc.
Then,, carry out bonding wire operation (Wire Bonding), electrically connect this control chip 302 and storage chip 303 respectively to this substrate 300 by gold thread 304 and 305 with reference to Fig. 4 C.This bonding wire operation does not repeat them here for existing technology.In addition, if necessary, this chip also can be electrically connected to this substrate with flip chip (Flip Chip), and this is the selection on the design and implementation, does not influence the performance of technical characterictic of the present invention.
Then, shown in Fig. 4 D, the sticking part 32 that carries that is equipped with passive device 301, control chip 302 and storage chip 303 is inserted in the mould 33, carry out molding operation, be formed for coating the colloid 306 of this passive device 301, control chip 302, storage chip 303 and gold thread 304 and 305 in this year on the part 32.As seen from the figure, the position of carrying part 32 confession moulds 33 clampings is outside the zone (being represented by dotted lines the place) of predetermined shaping substrate 300, so form the resin compound of colloid 306 can not overflow glue to substrate 300 with respect on the electric connection pad 300c on the lower surface 300b of this colloid 306, the position of confession mould 33 clampings can not take the zone on the substrate 300 yet, make the area on the substrate 300 can fully be used to be provided with passive device and chip, therefore compare with above-mentioned prior art, have bigger electronic component the space is set, thereby large-sized storage chip also can be arranged on the substrate 300.
Refer again to Fig. 4 E, promptly carry out stripping operation after colloid 306 forms, mould 33 is broken away from year part 32 that is formed with this colloid 306 on it.As seen from the figure, formed colloid 306 is greater than the area of this substrate 300 (representing with imaginary line), haply substrate 300 is covered fully, this colloid 306 also has a rescinded angle 306a, the position that forms is the hypotenuse 320a corresponding to this opening 320, and between the hypotenuse 320a of the rescinded angle 306a of this colloid 306 and opening 320, be formed with a predetermined distance, the position that the upper surface 300a of this substrate 300 is positioned between the hypotenuse 320a of the rescinded angle 306a of this colloid 306 and opening 320 exposes outside this colloid 306, and forms one and expose the 300e of portion.This exposes the 300e of portion is substrate 300 unique zones that do not covered by colloid 306, when molding operation, it is that substrate 300 is unique by the position of mould 33 clampings, so after colloid 306 forms, this colloid 306 has rescinded angle 306a, makes the portion 300e of exposing expose outside this colloid 306.Though this exposes the 300e of portion can be by the mould clamping in molding operation, (300e of portion can be exposed away from this usually in the position on 0, so even this exposes the 300e of portion by the mould clamping, do not influence the space that is provided with of chip fully but chip is arranged on substrate 3.
Moreover, shown in Fig. 4 E, two side 306b, 306b of this colloid 306 extend the side 300f of two correspondences of this substrate 300, make between the side 300f of the side 306b of this colloid 306 and substrate 300 and have a default space, because the existence in this space, when mould stream (not marking) enters the space of formation colloid 306 on this year of the part 32 via the gum-injecting port (Mold Gate) 321 on year part 32, can not be subjected to the phenomenon that generation is ladle-to-ladle that stops of passive device 301, control chip 302 and storage chip 303, make the colloid 306 of formation not have the pore generation.Simultaneously, because the space that forms between the side 306b of this colloid 306 and the side 300f of substrate 300 is positioned at outside the zone of this substrate 300, the i.e. existence in this space can not occupy the zone on the substrate 300, so can not influence fully passive device and area of chip are not set on the substrate 300, make large-sized storage chip energy disposed thereon, meet the demand of high storage capacity product.
Then, shown in Fig. 4 Fa, cut single job (Singulation), the part excision is removed in substrate 300 outer waiting.This cutting operation because only must X-axis and Y-axis on straight cuts, shown in Fig. 4 Fb, there is not oblique cutting, use traditional cutting equipment to finish and cut, therefore do not need to make water cutter or laser cutting, so can finish with cheap cost and existing equipment.Moreover, with reference to Fig. 4 Fb, be arranged in the left side of figure and the line of cut of bottom side and can meet at perforate 320, make the hypotenuse 320a of perforate 320 be positioned at the outer part of side 300f of substrate 300, can separate with its part that is positioned at the side 300f of substrate 300, the part that makes the hypotenuse 320a of perforate 320 be positioned at the side 300f of substrate 300 becomes the hypotenuse 300d of substrate 300, just the hypotenuse 300d of this substrate 300 does not need oblique cutting, can when finishing, straight cuts form, the packaging part 30 that the present invention is formed after cutting single job and finishing can provide the holonmic space on the substrate 300 that chip and passive device are set, and need not expensive water cuts or laser cutting can form.
At last, lid 31 lids that will have lead angle 310 are connected on this packaging part 30, and shown in Fig. 4 Ga, the position that this lead angle 310 forms is corresponding to the hypotenuse 300d of these packaging part 30 substrates 300, after just lid 31 lids were connected on this packaging part 30, the hypotenuse 300d of this substrate 300 joined this lead angle 310 to.Finish winding, promptly form the semiconductor device 3 of the embodiment of the invention 1, this semiconductor device 3 is shown in Fig. 4 Gb, packaging part 30 only has the lower surface 300b of substrate 300 can expose outside lid 31, make the electric connection pad 300c on the lower surface 300b of substrate 300 also expose outside, borrow it make this semiconductor device 3 with as external device (ExternalDevice) the formation electrical connection of printed circuit board (PCB).
Embodiment 2
Fig. 5 A is the cutaway view of the semiconductor device 5 of the embodiment of the invention 2.The semiconductor device 5 of this embodiment 2 is roughly identical with the structure that the foregoing description 1 discloses, identical part promptly repeats no more at this, difference is, the side 506b of the colloid 506 of this semiconductor device 5 is not the side 500f copline with substrate 500, it is to tilt from outside to inside, makes the cross section of colloid 506 be the shape of wedge shape.Just shown in Fig. 5 B, the area that this colloid 506 covers on the substrate 500 roughly coincides with substrate 500, have only the 500e of the portion of exposing on the substrate 500 between the rescinded angle 506a of the hypotenuse 500d of this substrate 500 and colloid 506 not covered by colloid 506, so, the zone that forms colloid 506 does not all exceed substrate 500, when packaging part 50 is shaped through cutting single job in the expression semiconductor device 5, the cutting knife of cutting equipment (not marking) can not be cut and colloid 506, the carrying out time of therefore cutting single job can be slower than the consume speed of short and cutting knife, can reduce the loss of consumptive material.
The method for making of this semiconductor device 5 is shown in Fig. 6 A to Fig. 6 G.
At first, as shown in Figure 6A, prepare one have a plurality of isolated perforates 520 carry part 52, these perforate 520 rectangular leg-of-mutton shapes, the hypotenuse 500d of its hypotenuse 520a and the substrate 500 that carries predetermined moulding on the part 52 (among the figure to overflow shown in the line) partially overlaps.All the other describe in detail and change all with identical described in the embodiment 1, promptly no longer repeat at this.
Then, shown in Fig. 6 B, bonding passive device 501, control chip 502 and flash chip 503 respectively in the zone of the substrate 500 of predetermined moulding in two parallel relative C-C imaginary lines on carrying part 52.Owing to can promptly can be restricted so can supply to glue the size of putting chip less than the substrate 300 described in the embodiment 1 for passive device and the sticking area of putting of chip on the substrate 500.This imaginary line C is positioned on the position of the inside 3mm of substrate 500 side 500f, and the space between imaginary line C and substrate 500 side 500f can be flow through smoothly for the stream of the mould in the aftermentioned molding operation, avoids the formation in gas hole.
Then, shown in Fig. 6 C, carry out the bonding wire operation, electrically connect this control chip 502 and flash chip 503 respectively to this substrate 500 by many gold threads 504,505.
Then, shown in Fig. 6 D, carry out molding operation, this sticking part 52 that carries that is equipped with passive device 501, control chip 502 and flash chip 503 is placed in the mould 53, carrying the colloid 506 that is formed for coating this passive device 501, control chip 502, flash chip 503 and gold thread 504,505 on the part 52.At this moment, as seen from the figure, substrate 500 roughly is positioned at outside the substrate 500 and the side 500f adjacency of proper and substrate 500 for the zone of these mould 53 clampings, like this, carry part 52 and supply the position of mould 53 clampings can not occupy the area that can supply passive device and chip to be provided with on the substrate 500, so with the above-mentioned the 6th, 040, No. 622 United States Patent (USP) is compared, and the area for passive device and chip setting on this substrate 500 is still bigger.
After colloid 506 forms, promptly carry out the demoulding, mould 53 is broken away from year part 52 that is formed with colloid 506 on it, after the demoulding, shown in Fig. 6 E, this colloid 506 is to cover whole base plate 500 haply, only there is the part between the hypotenuse 520a of this colloid 506 formed rescinded angle 506a and perforate 520 not covered on the substrate 500 by colloid 506, this part that exposes outside colloid 506 forms the 500e of the portion of exposing of substrate 500, described in above-mentioned embodiment 1, this exposes the 500e of portion is that substrate 500 is unique by the position of mould clamping.
Then, shown in Fig. 6 Fa and Fig. 6 Fb, cut single job, part is removed in substrate 500 outer waiting separated, form packaging part 50 with substrate 500.As seen from the figure, this cuts single job only must carry out straight cuts on X-axis and Y-axis, so can cut by traditional cutting equipment, simultaneously, line of cut coincides with the side 500f of substrate 500, can not cut and colloid 506, make the consume of cutting equipment cutting knife slower, and cutting single job, to carry out the time shorter.
At last, lid 51 lids that will have lead angle (not marking) are connected on this packaging part 50, finish the manufacturing of the semiconductor device 5 of embodiment 2, shown in Fig. 6 G.Though the area that can supply passive device and chip setting on the substrate 500 of this semiconductor device 5 is less than the semiconductor device among the embodiment 13, but under the situation that chip size is allowed, be used to be provided with the area of passive device and chip setting on the semiconductor device 5, the area that provides greater than prior art still, and must not make expensive cutting equipments such as water cutter or laser, it also has the less and lower-cost advantage of consumptive material.

Claims (25)

1. a semiconductor device is characterized in that, this device comprises:
Lid with lead angle; And
This cover cap of confession connects the packaging part on it, and it comprises:
Has substrate to hypotenuse that should the lead angle position;
Connect at least one passive component and at least one chip put on this substrate, and this chip is to borrow a plurality of conductive components to be electrically connected to this substrate; And
Be used to coat the colloid of this at least one passive component, at least one chip and conductive component, this colloid is formed with the rescinded angle corresponding to the hypotenuse of this substrate, make between the rescinded angle of the hypotenuse of this substrate and colloid and form the portion of exposing that exposes outside this colloid, make this substrate except that this exposes portion, its surface that is formed with this colloid is all covered by colloid.
2. semiconductor device as claimed in claim 1 is characterized in that, after this cover cap was connected on the substrate, the hypotenuse of this substrate was engaged in the lead angle of this lid.
3. semiconductor device as claimed in claim 1 is characterized in that, the side of this colloid flushes coplanar relation that forms with the side of substrate.
4. semiconductor device as claimed in claim 1 is characterized in that, the side of this colloid be from the side of substrate by outside tilt inwardly and make the cross section of colloid be the shape of wedge shape.
5. semiconductor device as claimed in claim 1 is characterized in that, the hypotenuse of this substrate is a kind of in straight line, the linear edges with at least one breakover point, arc limit and the arc limit with at least one breakover point.
6. semiconductor device as claimed in claim 1 is characterized in that, the hypotenuse of this substrate and the side of substrate are to form with distinct program.
7. semiconductor device as claimed in claim 1 is characterized in that, the hypotenuse of this substrate must be to the shape of lead angle that should lid.
8. semiconductor device as claimed in claim 1 is characterized in that this conductive component is a bonding wire.
9. semiconductor device as claimed in claim 1 is characterized in that, this substrate exposes outside on the surface of this semiconductor device and is formed with a plurality of electric connection pads, makes this semiconductor device and external device form electrical connection.
10. semiconductor device as claimed in claim 1 is characterized in that, a kind of in the combination that this at least one chip is large-sized memory chip, control chip and memory chip and the combination of two memory chips.
11. the method for making of a semiconductor device is characterized in that, this method for making comprises the following steps:
Preparation has the part that carries of at least one perforate, comprises the substrate of at least one predetermined moulding this year on the part, and this substrate cut-grafting formed hypotenuse to this at least one perforate;
Sticking at least one passive component and at least one chip put on the zone of substrate of predetermined moulding of this year of part;
Electrically connect this chip and this year part;
Carry out molding operation to form the colloid that coats this at least one passive component and at least one chip on the part in this year, the side of formed colloid must be not less than the side that carries the substrate of predetermined moulding on the part at least except that the position of perforate hypotenuse corresponding to this year of part; Colloid after the shaping has a rescinded angle corresponding to the hypotenuse place of the perforate on this year part, makes between the hypotenuse of the rescinded angle of this colloid and perforate to be formed with a predetermined distance;
The side of being scheduled to the substrate of moulding along this year on the part carries out straight cuts, to form with the substrate is bearing part and the size packaging part identical with substrate area, wherein, the part of the hypotenuse institute cut-grafting of this substrate and perforate promptly forms the hypotenuse of substrate, and the portion of exposing that is not become this substrate by the part that colloid covered between the rescinded angle of the hypotenuse of this substrate and colloid; And
The cover cap that will have lead angle is connected on this packaging part, thereby forms this semiconductor device, and after this lid and packaging part winding finished, the hypotenuse of the substrate of this packaging part was engaged to the lead angle of this lid.
12. method for making as claimed in claim 11 is characterized in that, this perforate is to reach back a kind of formation in the butt formula with impact style.
13. method for making as claimed in claim 11, it is characterized in that, the shape of this perforate is a kind of in right-angled triangle, obtuse triangle, acute triangle and the equilateral triangle, and be with one hypotenuse and substrate cut-grafting, the hypotenuse that makes this perforate is after the step of straight cuts is finished, and the not cut part of the hypotenuse of this perforate forms the hypotenuse of this substrate.
14. method for making as claimed in claim 11, it is characterized in that, this perforate is a kind of in semicircle and the analogous shape, and be with the one straight line become this perforate hypotenuse and with the substrate cut-grafting, the hypotenuse that makes this perforate is after the step of straight cuts is finished, and the not cut part of the hypotenuse of this perforate forms the hypotenuse of this substrate.
15. method for making as claimed in claim 11 is characterized in that, the hypotenuse of this perforate is a straight line, this packaging part is formed after, the hypotenuse of this substrate also is a straight line.
16. method for making as claimed in claim 11 is characterized in that, the hypotenuse of this perforate is the non-rectilinear limit, this packaging part is formed after, the hypotenuse of this substrate also is the non-rectilinear limit.
17. method for making as claimed in claim 11 is characterized in that, the hypotenuse of this perforate must be not less than the hypotenuse behind this molding substrate, makes the hypotenuse of this substrate be the unique part without straight cuts of substrate in the step of this straight cuts.
18. method for making as claimed in claim 11, it is characterized in that, after this colloid is shaped, the side of this colloid is positioned at outside the side of this substrate, make colloid be covered in the zone of carrying on the part, except that the part of rescinded angle between the hypotenuse of perforate of this colloid, greater than substrate, so in the step of straight cuts, it is cut that colloid exceeds the part of substrate.
19. method for making as claimed in claim 18 is characterized in that, formed packaging part in the step of straight cuts, except that the hypotenuse of substrate, the side of this substrate all with the side copline that is formed at the colloid on the substrate.
20. method for making as claimed in claim 11, it is characterized in that, after this colloid forms, this colloid is except that its rescinded angle, its side all coincides with the side of this substrate, this colloid is covered the Zone Full that exposes outside the portion of substrate, so in the step of straight cuts, can not be cut to this colloid, and only can be with the part excision of this year of part outside substrate.
21. method for making as claimed in claim 20, it is characterized in that, in the step of straight cuts in the formed packaging part, be formed on colloid on this substrate except that its rescinded angle, its side all be from the side of substrate by outside tilt inwardly, and make the cross section that is formed on the colloid on this substrate be the shape of wedge shape.
22. method for making as claimed in claim 11 is characterized in that, this chip is to realize by bonding wire with the electric connection of carrying the substrate in the part.
23. method for making as claimed in claim 11 is characterized in that, this chip is at least a in control chip and the memory chip.
24. method for making as claimed in claim 11 is characterized in that, the step of this straight cuts is finished by general cutting equipment.
25. method for making as claimed in claim 11 is characterized in that, this substrate exposes outside on the surface of this semiconductor device and is formed with a plurality of electric connection pads, for electrically connecting with external device that this semiconductor device is borrowed.
CNB2005100807346A 2005-06-30 2005-06-30 Semiconductor device capable of holding large size chip and producing method and relative carrier thereof Expired - Fee Related CN100446241C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB2005100807346A CN100446241C (en) 2005-06-30 2005-06-30 Semiconductor device capable of holding large size chip and producing method and relative carrier thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2005100807346A CN100446241C (en) 2005-06-30 2005-06-30 Semiconductor device capable of holding large size chip and producing method and relative carrier thereof

Publications (2)

Publication Number Publication Date
CN1889260A CN1889260A (en) 2007-01-03
CN100446241C true CN100446241C (en) 2008-12-24

Family

ID=37578523

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005100807346A Expired - Fee Related CN100446241C (en) 2005-06-30 2005-06-30 Semiconductor device capable of holding large size chip and producing method and relative carrier thereof

Country Status (1)

Country Link
CN (1) CN100446241C (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110324263B (en) 2018-03-30 2021-06-29 华为技术有限公司 Method, equipment and system for transmitting multicast message
CN209297344U (en) * 2018-12-06 2019-08-23 深圳市江波龙电子股份有限公司 A kind of storage card

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020131251A1 (en) * 2001-03-16 2002-09-19 Corisis David J. Semiconductor card and method of fabrication
US20020140068A1 (en) * 2001-03-28 2002-10-03 Ming-Hsun Lee Leadframe-based semiconductor package for multi-media card
JP2003044804A (en) * 2001-07-30 2003-02-14 Sony Corp Memory card and method for manufacturing the same
CN1493059A (en) * 2001-02-28 2004-04-28 ������������ʽ���� Memory card and its manufacturing method
US20040259291A1 (en) * 2003-06-23 2004-12-23 Sandisk Corporation Method for efficiently producing removable peripheral cards

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1493059A (en) * 2001-02-28 2004-04-28 ������������ʽ���� Memory card and its manufacturing method
US20020131251A1 (en) * 2001-03-16 2002-09-19 Corisis David J. Semiconductor card and method of fabrication
US20020140068A1 (en) * 2001-03-28 2002-10-03 Ming-Hsun Lee Leadframe-based semiconductor package for multi-media card
JP2003044804A (en) * 2001-07-30 2003-02-14 Sony Corp Memory card and method for manufacturing the same
US20040259291A1 (en) * 2003-06-23 2004-12-23 Sandisk Corporation Method for efficiently producing removable peripheral cards

Also Published As

Publication number Publication date
CN1889260A (en) 2007-01-03

Similar Documents

Publication Publication Date Title
TWI249772B (en) Semiconductor device for accommodating large chip, fabrication method thereof, and carrier used in the semiconductor device
CN101496161B (en) SIP module with a single sided lid
CN101641799B (en) A small form factor molded memory card and method thereof
US6538311B2 (en) Two-stage transfer molding method to encapsulate MMC module
US6013945A (en) Electronic module for data cards
US20080156518A1 (en) Alignment and cutting of microelectronic substrates
US20070216006A1 (en) Integrated circuit package on package system
CN101341586A (en) Method of manufacturing flash memory cards
US7629679B2 (en) Semiconductor package, memory card including the same, and mold for fabricating the memory card
CN101404270A (en) Semiconductor device, method of manufacturing the same, and semiconductor substrate
US9462705B2 (en) USB device with preassembled lid
EP3214648A1 (en) Sensing chip encapsulation component and electronic device with same
CN103229293A (en) Semiconductor chip package, semiconductor module, and method for manufacturing same
CN100446241C (en) Semiconductor device capable of holding large size chip and producing method and relative carrier thereof
CN109088295A (en) 4PIN connector manufacture craft
CN100442312C (en) Contact chip card, its production method and use thereof
CN105489597B (en) System-in-package module component, system-in-package module and electronic equipment
TW201517241A (en) Package module with offset stack components
US8164200B2 (en) Stack semiconductor package and method for manufacturing the same
CN101150076A (en) Making method for semiconductor encapsulation component and semiconductor part location structure and method
CN104733447A (en) Packaging module with stacked elements
US20030071129A1 (en) Module card and a method for manufacturing the same
CN102709199A (en) Mold array process method for covering side edge of substrate
KR20160017381A (en) Semiconductor Package and methods for manufacturing the same
CN100466212C (en) Semiconductor package and its making method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20081224