CN100440734C - Dynamic accelerating method and device of analogue/digital converter - Google Patents
Dynamic accelerating method and device of analogue/digital converter Download PDFInfo
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- CN100440734C CN100440734C CNB2005100718662A CN200510071866A CN100440734C CN 100440734 C CN100440734 C CN 100440734C CN B2005100718662 A CNB2005100718662 A CN B2005100718662A CN 200510071866 A CN200510071866 A CN 200510071866A CN 100440734 C CN100440734 C CN 100440734C
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Abstract
The present invention relates to a dynamic accelerating method of an analogue digital converter. The method comprises that a sampling clock signal is generated after a phase-locked loop receives a horizontal synchronizing signal to lock a phase; the sampling frequency of the sampling clock signal is detected; whether the maximum conversion ratio of the analogue digital converter is larger than and equal to the sampling frequency or not is judged; the turning rate of the analogue digital converter is enhanced when the maximum conversion ratio is smaller than the sampling frequency, so that the maximum conversion rate is larger than and equal to the sampling frequency. The present invention feeds back and controls the turning rate of the analogue digital converter in a current supplying mode by frequency detection for the frequency of a sample, so that the maximum conversion ratio of the analogue digital converter is larger than and equal to the sampling frequency, and the optimization of energy utilization rate is achieved.
Description
Technical field
The present invention relates to a kind of dynamic accelerating method of analog/digital converter, particularly relate to a kind of by detecting the dynamic accelerating method of sampling frequency with the maximum transfer ratio of control analog/digital converter.
Background technology
Up to now, the signal source of LCD desire display frame is still in the majority with analog signal, therefore LCD needs this analog signal is converted to digital signal by analog/digital converter, to use as scale controller (scaler) with numerically controlled in the liquid crystal display.
Please refer to Fig. 1, Fig. 1 is the schematic diagram that analog/digital converter receives display frame signal source (analog signal) in the LCD.This analog/digital converter 110 can to take a sample as the analog signal 115 of display frame signal source and switching motion after, output digital signal 117.
Sampling frequency when 110 pairs of analog signals 115 of analog/digital converter are taken a sample is decided by clock signal 130.130 of clock signals produce for LCD is inner a horizontal-drive signal 135 behind 120 frequency lockings of phase-locked loop to produce (frequency of horizontal-drive signal 135 is identical with the horizontal frequency that LCD picture sets usually).And analog/digital converter 110 can be changed the analog signal 115 after the sampling, and the maximum transfer ratio of analog/digital converter 110 in transfer process will depend on the performance of analog/digital converter 110 itself.
In general, analog/digital converter 110 is carrying out in the process of analog/digital conversion to analog signal 115 and to it, the maximum transfer ratio of analog/digital converter 110 must be greater than sampling frequency, just can make analog signal 115 under the horizontal sweep that meets LCD picture is set, be converted to digital signal 117.
Yet, the predicament that is run at present is: in some cases, as when the resolution setting of LCD picture when high more, be that horizontal-drive signal 135 frequencies are when high more, analog/digital converter 110 its maximum transfer ratios of LCD might not be more than or equal to sampling frequency, and cause LCD to make a mistake at reception analog signal 115 shown pictures, on the other hand, if analog/digital converter 110 is set at high-conversion rate (optimum performance of analog/digital converter), when if the resolution of LCD picture is made as low resolution, then analog/digital converter will expend the action that unnecessary energy is done conversion.
In view of this, the present invention proposes a kind of dynamic accelerating method and device of analog/digital converter, can dynamically improve the maximum transfer ratio of analog/digital converter, so that the maximum transfer ratio of analog/digital converter in transfer process can mate sampling frequency.And by the present invention, the analog/digital converter of LCD is the analog signal of accurate Analysis input more, and the display frame that LCD is presented is correct.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of dynamic accelerating method and device of analog/digital converter, makes the maximum transfer ratio of analog/digital converter can mate its sampling frequency, reaches the optimization of capacity usage ratio.
To achieve these goals, the invention provides a kind of dynamic accelerating method of analog/digital converter, its characteristics are that this method comprises: receive a horizontal-drive signal by a phase-locked loop and carry out phase-locked back generation one sampling clock signal; Detect a sampling frequency of this sampling clock signal; Whether a maximum transfer ratio of judging this analog/digital converter is more than or equal to this sampling frequency; And when this maximum transfer ratio during, improve the single-revolution rate of this analog/digital converter less than this sampling frequency so that should the maximum transfer ratio more than or equal to this sampling frequency; This determining step utilizes a lookup table mode to judge that whether this maximum inversion frequency is more than or equal to this sampling frequency.
The dynamic accelerating method of above-mentioned analog/digital converter, its characteristics are that this raising revolution rate step is with an electric current that provides current system to improve this analog/digital converter, to improve this revolution rate.
The dynamic accelerating method of above-mentioned analog/digital converter, its characteristics are that the mode in a plurality of parallel-currents source is switched in this raising revolution rate step utilization, offer the size of this analog/digital converter electric current with adjustment, to change this revolution rate.
The present invention also provides a kind of dynamic accelerator of analog/digital converter, its characteristics are, the sampling frequency of this analog/digital converter is by being received a horizontal-drive signal by a phase-locked loop and carrying out a phase-locked back clock signal that is produced and controlled, this dynamic accelerator comprises: a frequency detection circuit, detect the frequency of this clock signal, and detect back output one testing result signal; And a control unit, receive this testing result signal, and according to this testing result signal output one suitable electric current to this analog/digital converter; This control unit comprises: a lookup table circuit receives this testing result signal with action that this testing result signal is tabled look-up, and exports a control signal according to checking result; And one electric current improve circuit, receive this control signal with decision output this suitable electric current to this analog/digital converter.
The dynamic accelerator of above-mentioned analog/digital converter, its characteristics are that this electric current improves circuit and comprises: organize the parallel-current source, each is organized the parallel-current source and has a current output terminal to couple this analog/digital converter more; And a switch, receive this control signal, and according to this control signal to determine whether corresponding its current output terminal of parallel-current source provides electric current to this analog/digital converter.
The dynamic accelerator of above-mentioned analog/digital converter, its characteristics are that its current output terminal institute can the output current size have certain proportion between this group parallel-current source.
The present invention also provides a kind of dynamic accelerator of analog/digital converter, its characteristics are, the sampling frequency of this analog/digital converter is by being received a horizontal-drive signal by a phase-locked loop and carrying out a phase-locked back clock signal that is produced and controlled, this dynamic accelerator comprises: a comparison circuit, receive this clock signal and receive a reference signal, carrying out the frequency comparison between two signals, and in back output one control signal relatively; And one electric current improve circuit, receive this control signal with decision output this suitable electric current to this analog/digital converter; This electric current improves circuit and comprises: organize the parallel-current source, each is organized the parallel-current source and has a current output terminal more, and this current output terminal couples this analog/digital converter; And a switch, receive this control signal to determine whether corresponding its current output terminal of parallel-current source provides electric current to this analog/digital converter.
Effect of the present invention, be by sampling frequency is carried out frequency detecting, with by the revolution rate of current system FEEDBACK CONTROL analog/digital converter is provided, so that the maximum transfer ratio of analog/digital converter can reach the optimization of capacity usage ratio more than or equal to sampling frequency.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Fig. 1 is the schematic diagram that analog/digital converter receives display frame signal source (analog signal) in the LCD;
Fig. 2 is the flow chart of the dynamic accelerating method of its sampling frequency of analog/digital converter of preferred embodiment of the present invention;
Fig. 3 A is the schematic diagram of the dynamic accelerator of its sampling frequency of analog/digital converter of preferred embodiment of the present invention;
Fig. 3 B improves the schematic diagram of circuit for the electric current of preferred embodiment of the present invention;
Fig. 4 is the schematic diagram of dynamic accelerator of its sampling frequency of analog/digital converter of another embodiment of the present invention.
Wherein, Reference numeral:
110: analog/digital converter
115: analog signal
117: digital signal
120: the phase-locked loop
130: clock signal
135: horizontal-drive signal
201～204: step
300,400: accelerator
310: frequency detecting device
315: the testing result signal
320: control unit
330: lookup table circuit
337,417: control signal
340,420: electric current improves circuit
345,425: current signal
350: switch
360,370: parallel-current source group
380: current source
390: output signal
410: comparison circuit
Embodiment
Please refer to Fig. 2, be the flow chart of the dynamic accelerating method of the analog/digital converter of preferred embodiment of the present invention.In step 201, detect sampling frequency (f by the clock signal of analog/digital converter that the phase-locked loop exports to
s), for example change display resolution, sampling frequency (f
s) should change thereupon.
If step 202 judged result for being, then need not be adjusted the maximum transfer ratio of analog/digital converter, the method promptly finishes, and this is a step 203.
If step 202 judged result is for denying, then need the maximum transfer ratio of analog/digital converter is adjusted, preferably improve the electric current of analog/digital converter, to quicken the revolution rate of analog/digital converter, thereby make maximum transfer ratio more than or equal to sampling frequency, this is a step 204.
This improves the electric current of analog/digital converter inside so that current system to be provided, the analog/digital converter sampling frequency is improved, its advantage is when the analog/digital converter electric current additionally is provided, can improve the revolution rate (rate of change of unit interval voltage, slew rate) in the analog/digital converter.Be familiar with revolution rate relevant technologies person as can be known, the revolution rate is relevant with current value and be directly proportional, therefore can improve this revolution rate by electric current additionally is provided, when the revolution rate in the analog/digital converter improves, just the rate of change of the unit interval voltage of allowed analog signal improves in the analog/digital converter unit interval, is equivalent to handle the analog signal of big frequency.Therefore, when electric current additionally is provided to analog/digital converter, can improve the maximum transfer ratio of analog/digital converter in transfer process.
Please refer to Fig. 3 A, dynamic accelerator schematic diagram for the analog/digital converter of preferred embodiment of the present invention, comprise frequency detection circuit 310 and control unit 320, frequency detection circuit 310 is responsible for detecting the frequency of the clock signal of being exported by phase-locked loop 120 130, and output testing result signal 315 is to control unit 320.
In this preferred embodiment of the present invention, control unit 320 comprises lookup table circuit 330 and electric current improves circuit 340, and the testing result signal 315 that frequency detection circuit 310 is exported is received by lookup table circuit 330, lookup table circuit 330 can be to testing result signal 315 action of tabling look-up, with the maximum transfer ratio of judging analog/digital converter 110 whether more than or equal to sampling frequency; Lookup table circuit 330 is judged the gap of maximum transfer ratio and sampling frequency by tabling look-up, improve circuit 340 with output control signal 337 to electric current, improve circuit with Control current and will export the current signal 345 of the different magnitudes of current to analog/digital converter 110, so that maximum transfer ratio can be more than or equal to sampling frequency.
Fig. 3 B shows that the electric current of the preferred embodiment according to the present invention improves the schematic diagram of circuit, comprises switch 350 and organizes parallel-current source 360,370 etc. more, wherein, every group of exportable magnitude of current such as parallel-current source 360,370 and inequality.Preferably, can utilize its each employed current source 380 number differences such as every group of parallel-current source 360,370, so that every group of parallel-current source 360,370 ... the magnitude of current difference that can export, and different revolution rates is arranged.
Therefore, switch 350 receives control signals 337, can switch whether conducting such as every group of parallel-current source 360,370 according to control signal 337, improves the current signal 345 that circuit 340 can provide the different magnitudes of current with Control current.
Please refer to Fig. 4, be the schematic diagram of the dynamic accelerator of its sampling frequency of analog/digital converter of another preferred embodiment of the present invention.In Fig. 4, accelerator 400 comprises comparison circuit 410 and electric current improves circuit 420.This accelerator receives reference signal 415 for the frequency detecting mode of the clock signal 130 that phase-locked loop 120 is exported by comparison circuit 410, by 410 while of comparison circuit receive clock signal 130 and reference signal 415, with carry out between two signals frequency ratio, with the frequency of judging clock signal 130 whether less than the frequency of reference signal 415.If above-mentioned judged result is for being, then to meet the user required in representative, and not meet the user required otherwise then represent.
And comparison circuit 410 can output one control signal 417 improve circuit 420 to electric current after judgement, gives analog/digital converter 110 with the current signal 425 of the different magnitudes of current of control output.
Comprehensively above-mentioned, the present invention proposes a kind of dynamic accelerating method and device of analog/digital converter, by sampling frequency is carried out frequency detecting, with by the revolution rate of current system FEEDBACK CONTROL analog/digital converter is provided, so that the maximum transfer ratio of analog/digital converter can be more than or equal to sampling frequency.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of claim of the present invention.
Claims (7)
1, a kind of dynamic accelerating method of analog/digital converter is characterized in that, this method comprises:
Receive a horizontal-drive signal by a phase-locked loop and carry out phase-locked back generation one sampling clock signal;
Detect a sampling frequency of this sampling clock signal;
Whether a maximum transfer ratio of judging this analog/digital converter is more than or equal to this sampling frequency; And
When this maximum transfer ratio during less than this sampling frequency, improve the single-revolution rate of this analog/digital converter so that should the maximum transfer ratio more than or equal to this sampling frequency;
This determining step utilizes a lookup table mode to judge that whether this maximum inversion frequency is more than or equal to this sampling frequency.
2, the dynamic accelerating method of analog/digital converter according to claim 1 is characterized in that, this raising revolution rate step is with an electric current that provides current system to improve this analog/digital converter, to improve this revolution rate.
3, the dynamic accelerating method of analog/digital converter according to claim 1, it is characterized in that, the mode in a plurality of parallel-currents source is switched in this raising revolution rate step utilization, offers the size of this analog/digital converter electric current with adjustment, to change this revolution rate.
4, a kind of dynamic accelerator of analog/digital converter, it is characterized in that, the sampling frequency of this analog/digital converter is by being received a horizontal-drive signal and carrying out a phase-locked back clock signal that is produced and controlled by a phase-locked loop, this dynamic accelerator comprises:
One frequency detection circuit detects the frequency of this clock signal, and detects back output one testing result signal; And
One control unit receives this testing result signal, and gives this analog/digital converter according to this testing result signal output one suitable electric current; This control unit comprises:
One lookup table circuit receives this testing result signal with action that this testing result signal is tabled look-up, and exports a control signal according to checking result; And
One electric current improves circuit, receives this control signal, gives this analog/digital converter with this suitable electric current of decision output.
5, the dynamic accelerator of analog/digital converter according to claim 4 is characterized in that, this electric current improves circuit and comprises:
Many group parallel-currents source, each is organized the parallel-current source and has a current output terminal to couple this analog/digital converter; And
Whether one switch receives this control signal, and provide electric current to this analog/digital converter according to this control signal with its current output terminal of parallel-current source that determines correspondence.
6, the dynamic accelerator of analog/digital converter according to claim 5 is characterized in that, its current output terminal institute can the output current size have certain proportion between this group parallel-current source.
7, a kind of dynamic accelerator of analog/digital converter, it is characterized in that, the sampling frequency of this analog/digital converter is by being received a horizontal-drive signal and carrying out a phase-locked back clock signal that is produced and controlled by a phase-locked loop, this dynamic accelerator comprises:
One comparison circuit receives this clock signal and receives a reference signal, carrying out the frequency comparison between two signals, and in back output one control signal relatively; And
One electric current improves circuit, receives this control signal and gives this analog/digital converter with this suitable electric current of decision output; This electric current improves circuit and comprises:
Many group parallel-currents source, each is organized the parallel-current source and has a current output terminal, and this current output terminal couples this analog/digital converter; And
Whether one switch receives this control signal, and provide electric current to this analog/digital converter according to this control signal with its current output terminal of parallel-current source that determines correspondence.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100718662A CN100440734C (en) | 2005-05-25 | 2005-05-25 | Dynamic accelerating method and device of analogue/digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100718662A CN100440734C (en) | 2005-05-25 | 2005-05-25 | Dynamic accelerating method and device of analogue/digital converter |
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| CN1870439A CN1870439A (en) | 2006-11-29 |
| CN100440734C true CN100440734C (en) | 2008-12-03 |
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| CNB2005100718662A Expired - Fee Related CN100440734C (en) | 2005-05-25 | 2005-05-25 | Dynamic accelerating method and device of analogue/digital converter |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101488779B (en) * | 2008-01-15 | 2012-12-12 | 瑞昱半导体股份有限公司 | Transceiver having adjustable sampling point and related message tranceiving method |
| CN102281067A (en) * | 2010-06-09 | 2011-12-14 | 承景科技股份有限公司 | Error correction system for analog-digital converter |
| US9667263B1 (en) * | 2016-10-06 | 2017-05-30 | Yuan-Ju Chao | Apparatus and method of self-healing data converters |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5691720A (en) * | 1996-03-08 | 1997-11-25 | Burr- Brown Corporation | Delta sigma analog-to-digital converter having programmable resolution/bias current circuitry and method |
| CN1217836A (en) * | 1996-05-07 | 1999-05-26 | 艾利森电话股份有限公司 | Method and device to convert analog current to digital signal |
| US6414659B1 (en) * | 1999-06-15 | 2002-07-02 | Samsung Electronics Co., Ltd. | LCD gain and offset value adjustment system and method |
-
2005
- 2005-05-25 CN CNB2005100718662A patent/CN100440734C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5691720A (en) * | 1996-03-08 | 1997-11-25 | Burr- Brown Corporation | Delta sigma analog-to-digital converter having programmable resolution/bias current circuitry and method |
| CN1217836A (en) * | 1996-05-07 | 1999-05-26 | 艾利森电话股份有限公司 | Method and device to convert analog current to digital signal |
| US6414659B1 (en) * | 1999-06-15 | 2002-07-02 | Samsung Electronics Co., Ltd. | LCD gain and offset value adjustment system and method |
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| CN1870439A (en) | 2006-11-29 |
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