CN101488779B - Transceiver having adjustable sampling point and related message tranceiving method - Google Patents
Transceiver having adjustable sampling point and related message tranceiving method Download PDFInfo
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- CN101488779B CN101488779B CN 200810002994 CN200810002994A CN101488779B CN 101488779 B CN101488779 B CN 101488779B CN 200810002994 CN200810002994 CN 200810002994 CN 200810002994 A CN200810002994 A CN 200810002994A CN 101488779 B CN101488779 B CN 101488779B
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Abstract
A transceiver comprises a first digital analogue converter, an operation circuit, an analog-to-digital converter, a digital signal processing circuit, a second digital analogue converter, an adjustable delay circuit and a control circuit. The first digital analogue converter is used for receiving a first digital signal so as to generate analog signals; the operation signal is used for receiving the analog signals and feedback signals so as to generate operated analog signals. The analog-to-digital converter is used for generating a second digital signal according to the operated analog signals; the digital signal processing circuit is used for generating treated digital signals. The second digital analogue converter is used for generating feedback signals according to the treated digital signals. The adjustable delay circuit is used for delaying clocked signals according to control signals so as to regulate sampling points of at least either the first digital analogue converter or the second digital analogue converter; the control circuit is used for generating the control signals according to the treated digital signals.
Description
Technical field
The invention relates to transceiver and receiving/transmission method thereof, particularly relevant for the transceiver that can adjust sampling point and receiving/transmission method thereof.
Background technology
Generally speaking, the transceiver of Ethernet (Ethernet) all has receiving terminal and transmission end, and it can pass through passage (channel) and transmit or receive signal.Yet, when signal transmits or receive, can interfere with each other like the signal of reception or the signal of transmission because of various effects, and produce interference signal (like NEXT, ECHO etc.), so transceiver has the influence that a cover mechanism is come the lessen any interference signal usually.
See also No. the 2007/0042721st, the open application case of United States Patent (USP); Wherein disclosed a kind of transceiver, this transceiver comprises transmission end digital analog converter (Tx DAC), hybrid circuit (HybridCircuit), comparison circuit (Compare Circuit), decoder/slicer (Decoder/Slicer), receiving terminal analog-digital converter (Rx ADC), digital processing circuit and post processing circuitry (PostProcessing Circuit).The operation principle of each element of this known transceivers please refer to No. the 2007/0042721st, the open application case of United States Patent (USP).
Yet this known transceivers still has some shortcomings.Wherein, produce analog signal when TX DAC receiving digital signals, the analog passband signal regular meeting here has the interference signal that produces because of channel, and at this, interference signal is made a general reference the interference that above-mentioned NEXT, ECHO etc. cause because of various factors.Therefore, if the receiving terminal analog-digital converter is sampled to conversion place (transition) of interference signal, then can makes the influence of interference signal become big, thereby possibly produce wrong sampling result.Therefore, the analog signal through a cancellation part produces calculating back analog signal usually, can drop within the treatable scope of receiving terminal analog-digital converter institute so that calculate the back analog signal.Yet, because various factors possibly make analog signal incorrect by the amount of cancellation, and then let and calculate the back analogue signal generating and postpone or distortion, to such an extent as to the signal section of institute's cancellation and not as as original expection drop on the correct position.For this reason, need the method for an ability head it off badly.
Summary of the invention
A purpose of the present invention is for providing a kind of transceiver; It has a mechanism with provide inhibit signal to the element in the transceiver with as the sampling or the usefulness of delay; Perhaps provide multi-phase clock signal to the usefulness of the element in the transceiver, use obtaining preferable sampling point or preferable signal as sampling.
One embodiment of the invention disclose a kind of transceiver, comprise: first digital analog converter, in order to receive first digital signal to produce analog signal; Computing circuit is coupled to this first digital analog converter, in order to receive this analog signal and feedback signal to produce operated analog; Analog-digital converter is coupled to this computing circuit, in order to produce second digital signal according to this operated analog; Digital signal processing circuit is coupled to this analog-digital converter, handles the back digital signal in order to handle this second digital signal to produce; Second digital analog converter is coupled to this digital signal processing circuit, produces this feedback signal in order to handle the back digital signal according to this; Adjustable delay circuit; Be coupled to this digital analog converter and this second digital analog converter, in order to come according to control signal delay clock signals to provide the palpus delay clock signals adjust in this first digital analog converter and this second digital analog converter sampling point of one of which at least; And control circuit, be coupled to this digital signal processing circuit and this adjustable delay circuit, in order to produce this control signal according to this processing back digital signal.
One embodiment of the invention disclose a kind of signal transmit-receive method, and the method comprises: use first digital analog converter to receive first digital signal to produce analog signal; According to this analog signal and feedback signal to produce operated analog; The sampling operated analog produces second digital signal; Handle the back digital signal according to second digital signal to produce; Use second digital analog converter to produce this feedback signal according to this processing back digital signal; Handle the back digital signal according to this and produce this control signal; And according to this control signal to adjust the sampling point of the one of which at least in this first digital analog converter and this second digital analog converter.
Another embodiment of the present invention has disclosed a kind of transceiver, comprises: first digital analog converter, in order to receive first digital signal to produce analog signal; Computing circuit is coupled to this first digital analog converter, in order to receive this analog signal and feedback signal to produce operated analog; Analog-digital converter is coupled to this computing circuit, and this operated analog produces second digital signal in order to take a sample; Digital signal processing circuit is coupled to this analog-digital converter, handles the back digital signal in order to handle this second digital signal to produce; Second digital analog converter is coupled to this digital signal processing circuit, produces this feedback signal in order to handle the back digital signal according to this; The multi-phase clock signal generator, in order to clock signal that a plurality of outs of phase are provided to the one of which at least in this analog-digital converter and second digital analog converter; And decision-making circuit, be coupled to this analog-digital converter, in order to a plurality of sampling values of this operated analog gained of taking a sample according to those clock signals, and decide sampling clock signal according to these a plurality of sampling values.
One embodiment of the invention disclose a kind of signal transmit-receive method, and the method comprises: receive first digital signal to produce analog signal; Receive this analog signal and feedback signal to produce operated analog; Use this operated analog of analog-digital converter sampling to produce second digital signal; Handle this second digital signal and handle the back digital signal to produce; Use digital analog converter to handle the back digital signal and produce this feedback signal according to this; The clock signal that a plurality of outs of phase are provided is to this analog-digital converter or this digital analog converter; And come to this processing back digital signal a plurality of sampling values of gained of taking a sample, so that decide target clock signal according to these a plurality of sampling values according to these a plurality of clock signals.
Description of drawings
Fig. 1 has illustrated the functional block diagram according to the transceiver of the first embodiment of the present invention.
Fig. 2 has illustrated the sequential chart of the conversion of signals point of interference signal.
Fig. 3 has illustrated the flow chart of the signal transmit-receive method of Fig. 1.
Fig. 4 has illustrated the functional block diagram of transceiver according to a second embodiment of the present invention.
Fig. 5 has illustrated the flow chart of the signal transmit-receive method of Fig. 4.
[main element label declaration]
100,400 transceivers
101,401 transmission end digital analog converters
102 path 10s, 3,403 hybrid circuits
105,405 subtracters, 107,407 analog front circuits
109,409 receiving terminal analog-digital converters
111,411 digital processing circuits
113,413 extra digit analog converters
115 adjustable delay circuit 117 control circuits
415 multiphase clock generators, 417 decision-making circuits
Embodiment
Fig. 1 has illustrated the functional block diagram according to the transceiver 100 of the first embodiment of the present invention.As shown in Figure 1, transceiver 100 comprises transmission end digital analog converter (TX DAC) 101, hybrid circuit 103, subtracter 105, analog front circuit (Analog Front End) 107, receiving terminal analog-digital converter (Extra DAC) 109, digital signal processing circuit 111, extra digit analog converter 113, control circuit 117 and adjustable delay circuit 115.TX DAC 101 receiving digital signals DS wherein
1And producing analog signal AS, the analog signal AS here can have the interference signal NS that produces because of channel usually.Hybrid circuit 103 is a codan, in order to eliminate the interference signal NS that is comprised among the analog signal AS.Subtracter 105 reception analog signal AS and feedback signal FB are to produce operated analog CAS.Analog front circuit 107 can include programmable gain amplifier (PGA), low pass filter and analog-digital converter etc., can disturb to increase quality of signals in order to reduce.Receiving terminal analog-digital converter 109 is in order to produce the second digital signal DS according to operated analog CAS
2Digital signal processing circuit 111 is in order to handle the second digital signal DS
2Handle back digital signal PDS to produce.Extra digit analog converter 113 is in order to produce feedback signal FB according to handling back digital signal PDS.It is noted that hybrid circuit 103 can also replace by other codan.And subtracter 105 also can optionally replace with other circuit.
This transceiver 100 utilizes adjustable delay circuit 115 (for example, DLL) in order to according to control signal CS
1Come delay clock signals CLK with provide respectively the delay clock signals DCLK of palpus
1, DCLK
2Give the one of which at least in transmission end digital analog converter 101 and the extra digit analog converter 113, with foundation as its sampling.Control circuit 117 is in order to according to handling back digital signal PDS to produce control signal CS
1Give adjustable delay circuit 115; If transceiver 100 has hybrid circuit 103 or analog front circuit 107; And hybrid circuit 103 or analog front circuit 107 have delay cell, and then control circuit 117 also can produce control signal CS according to handling back digital signal PDS
2, CS
3Give hybrid circuit 103 or analog front circuit 107 to control its retardation.Through such mechanism, can make the sampling point of receiving terminal analog-digital converter 109 not drop on the conversion of signals point of interference signal NS, ask for an interview Fig. 2.Fig. 2 has illustrated the sequential chart of the conversion of signals point of interference signal.As shown in Figure 2, X, the Y place is the transfer point of signal; If sampling point is positioned at X, the Y place, then the influence of interference signal NS can become big; So if make sampling point be positioned at X, outside the Y place, A for example shown in Figure 2; The B place, then can make interference signal NS to last processing after digital signal PDS produce less influence.
Perhaps; The signal quality of digital signal PDS such as SNR (Signal-to Noise Ratio), BER (Bit Error Rate) waited the sample position of controlling transmission end digital analog converter 101, extra digit analog converter 113 after control circuit 117 also can be handled according to digital signal processing circuit 111, and perhaps the retardation of hybrid circuit 103, analog front circuit 107 makes that handling back digital signal PDS has preferable signal quality.It is noted that, control circuit 117 can hardware or the mode of software appear, for instance, it can be incorporated in the digital signal processing circuit 111, or produces control signal with the mode of algorithm.Those skilled in the art are when reaching the effect identical with control circuit 117 with other means through description of the invention, and this all should be included within the scope of the present invention.
Fig. 3 has illustrated the flow chart of the signal transmit-receive method of Fig. 1.Those skilled in the art can be understood the method for signal transmitting and receiving of the present invention easily by the content of detailed technology characteristic shown in Figure 1 of the present invention and Fig. 3, so in each step of this Fig. 3 that repeats no more.
Fig. 4 has illustrated the functional block diagram of transceiver according to a second embodiment of the present invention.As shown in Figure 4, transceiver 400 comprises transmission end digital analog converter 401, hybrid circuit 403, subtracter 405, analog front circuit 407, receiving terminal analog-digital converter 409, digital signal processing circuit 411, extra digit analog converter 413, multi-phase clock signal generator 415 and decision-making circuit 417.Same; The mode of operation of transmission end digital analog converter 401, hybrid circuit 403, subtracter 405, analog front circuit 407, receiving terminal analog-digital converter 409, digital signal processing circuit 411 and extra digit analog converter 413 is identical with operation shown in Figure 1, so repeat no more in this.
The multi-phase clock signal generator 415 of transceiver 400 is in order to provide the clock signal clk of a plurality of outs of phase
1-nGive the one of which at least in receiving terminal digital analog converter 409 or the extra digit analog converter 413 respectively.Decision-making circuit 417 is in order to write down extra digit analog converter 413 according to clock signal clk
1-nTake a sample and handle a plurality of sampling value SV that back digital signal PDS is produced
1-n, and according to sampling value SV
1-nDeciding that clock signals is target clock signal.Among one embodiment, decision-making circuit 417 control multi-phase clock signal generators 415 are to produce target clock signal.In addition, decision-making circuit 417 also can be integrated in the digital processing circuit 411, that is digital processing circuit 411 capable of using writes down sampling value SV
1-nAnd according to sampling value SV
1-nDeciding that clock signals is target clock signal.
Know as is known to the person skilled in the art, desire is judged the quality of sampling phase, and the sampling value of object component capable of using (being extra digit analog converter 413 in this example) judges that if good sampling phase, then its sampling value can be maximum in theory.Therefore decision-making circuit 417 is when judging that sampling phase is preferable, and the sampling value of extra digit analog converter 413 capable of using is judged, when maximum as if sampling value, can determine that just sampling phase is best phase place.Certainly, those skilled in the art also can utilize other mechanism to judge best sampling phase, and it also should belong within the scope of the present invention.After the best sampling phase decision; Receiving terminal analog-digital converter in the transceiver just can be obtained correct signal to obtain correct 1; 0 is worth, and makes its accuracy that falls within the process range of receiving terminal analog-digital converter be able to promote at cancellation analog signal AS.
Fig. 5 has illustrated the flow chart of the signal transmit-receive method of Fig. 4.Those skilled in the art can be understood the method for signal transmitting and receiving of the present invention easily by the content of detailed technology characteristic shown in Figure 4 of the present invention and Fig. 5, so in each step of this Fig. 5 that repeats no more.
Through above-mentioned apparatus and method, can make the receiving terminal analog-digital converter in the transceiver be sampled to preferable position, and can be when utilizing subtracter cancellation partial simulation signal, the more correct part of ability cancellation is to obtain signal quality preferably.And except Ethernet, apparatus and method of the present invention also can be used on other communication system.
The above is merely preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (14)
1. transceiver comprises:
First digital analog converter is in order to receive first digital signal to produce analog signal;
Computing circuit is coupled to this first digital analog converter, in order to receive this analog signal and feedback signal to produce operated analog;
Analog-digital converter is in order to produce second digital signal according to this operated analog;
Digital signal processing circuit is handled the back digital signal in order to handle this second digital signal to produce;
Second digital analog converter produces this feedback signal in order to handle the back digital signal according to this;
Adjustable delay circuit is in order to come delay clock signals to adjust the sampling point of the one of which at least in this first digital analog converter, this second digital analog converter and this analog-digital converter according to control signal; And
Control circuit is in order to produce this control signal according to this processing back digital signal.
2. transceiver according to claim 1 also includes:
Analog front circuit is coupled between this analog-digital converter and this computing circuit, and includes at least one delay circuit;
Wherein, this control circuit also is coupled to this analog front circuit with the retardation according to this processing back this analog front circuit of Digital Signals.
3. transceiver according to claim 1, wherein this analog signal comprises the interference signal that signal channel causes, and this transceiver also includes:
Codan is coupled to this first digital analog converter and this arithmetic element to suppress this interference signal and to comprise at least one delay cell;
Wherein, this control circuit also is coupled to this codan with the retardation according to this processing back this codan of Digital Signals.
4. transceiver according to claim 2; Wherein this analog signal includes the interference signal that transmission channel causes, and wherein this control circuit makes the sampling point of this analog-to-digital conversion circuit can fall within the specific assignment sampling point of this interference signal through the retardation of controlling this analog front circuit.
5. transceiver according to claim 4, wherein this specific assignment sampling point is positioned at outside the part of this interference signal generation signals conversion.
6. transceiver comprises:
First digital analog converter is in order to receive first digital signal to produce analog signal;
Computing circuit is coupled to this first digital analog converter, in order to receive this analog signal and feedback signal to produce operated analog;
Analog-digital converter, this operated analog produces second digital signal in order to take a sample;
Digital signal processing circuit is handled the back digital signal in order to handle this second digital signal to produce;
Second digital analog converter produces this feedback signal in order to handle the back digital signal according to this;
The multi-phase clock signal generator, in order to clock signal that a plurality of outs of phase are provided to the one of which at least in this analog-digital converter and second digital analog converter; And
Decision-making circuit in order to a plurality of sampling values of this operated analog gained of taking a sample according to those clock signals, and decides sampling clock signal according to these a plurality of sampling values.
7. transceiver according to claim 6, wherein this computing circuit is a subtracter, in order to deduct this feedback signal from this analog signal to produce this operated analog.
8. a signal transmit-receive method is used in transceiver, and this method comprises:
Use first digital analog converter to receive first digital signal to produce analog signal;
Produce operated analog according to this analog signal and feedback signal;
This operated analog of taking a sample produces second digital signal;
Handle the back digital signal according to this second digital signal to produce;
Use second digital analog converter to produce this feedback signal according to this processing back digital signal;
Handle the back digital signal according to this and produce control signal; And
Sampling point according to the one of which at least in this control signal this first digital analog converter of adjustment and this second digital analog converter.
9. method according to claim 8 also includes:
Handle the retardation of the analog front circuit of this transceiver of back digital signal adjustment according to this.
10. method according to claim 8 also includes:
Handle the retardation of the codan of back this transceiver of Digital Signals according to this.
11. method according to claim 10, wherein according to the sampling point in this second digital signal of this control signal adjustment to fall within the specific assignment sampling point of interference signal.
12. method according to claim 11, wherein this specific assignment sampling point is positioned at outside the part of this interference signal generation signals conversion.
13. a signal transmit-receive method is used in transceiver, this method comprises:
Receive first digital signal to produce analog signal;
Receive this analog signal and feedback signal to produce operated analog;
Use this operated analog of analog-digital converter sampling to produce second digital signal;
Produce processing back digital signal according to this second digital signal;
Use digital analog converter to handle the back digital signal and produce this feedback signal according to this;
The clock signal that a plurality of outs of phase are provided is to this analog-digital converter or this digital analog converter; And
Come this processing back digital signal is taken a sample to obtain a plurality of sampling values, so that decide target clock signal according to these a plurality of sampling values according to these a plurality of clock signals.
14. method according to claim 13 also includes:
Determining in these a plurality of clock signals, is this target clock signal to the maximum person in should a plurality of sampling values.
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| CN 200810002994 CN101488779B (en) | 2008-01-15 | 2008-01-15 | Transceiver having adjustable sampling point and related message tranceiving method |
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| CN 200810002994 CN101488779B (en) | 2008-01-15 | 2008-01-15 | Transceiver having adjustable sampling point and related message tranceiving method |
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| CN101488779B true CN101488779B (en) | 2012-12-12 |
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| CN107819533B (en) * | 2017-11-16 | 2021-01-29 | 中国人民解放军63892部队 | Method and system for creating infinite-time long-wave-shape signal capable of being changed at will |
| CN112803959B (en) * | 2019-11-13 | 2022-05-10 | 瑞昱半导体股份有限公司 | Transceiver circuit and signal processing method applied to same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1361973A (en) * | 1999-07-16 | 2002-07-31 | 印芬龙科技股份有限公司 | Line termination device for a telephone subscriber line |
| CN1870439A (en) * | 2005-05-25 | 2006-11-29 | 晨星半导体股份有限公司 | Dynamic accelerating method and device of analogue/digital converter |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1361973A (en) * | 1999-07-16 | 2002-07-31 | 印芬龙科技股份有限公司 | Line termination device for a telephone subscriber line |
| CN1870439A (en) * | 2005-05-25 | 2006-11-29 | 晨星半导体股份有限公司 | Dynamic accelerating method and device of analogue/digital converter |
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