CN114765456A - Signal transmitting and receiving circuit, method for operating signal transmitting circuit and method for setting delay circuit - Google Patents

Abstract

The invention discloses a signal transceiving circuit, a method of operating the signal transceiving circuit, and a method of setting a delay circuit. The signal transceiver circuit is used for transmitting an output signal and receiving an input signal, and comprises: a delay circuit for delaying the first clock to generate a second clock; a first digital-to-analog converter for converting a first digital signal into the output signal according to the first clock; a second digital-to-analog converter for converting the first digital signal into an echo cancellation signal according to the second clock; an analog front end circuit for receiving the input signal and the echo cancellation signal and generating an analog signal; and an analog-to-digital converter for converting the analog signal to a second digital signal.

Description

Signal transmitting and receiving circuit, method for operating signal transmitting circuit and method for setting delay circuit

Technical Field

The present invention relates to a signal transceiver circuit, and more particularly, to reducing or eliminating hybrid echo (hybrid echo) in a signal transceiver circuit.

Background

In the known signal transceiving circuits, the signal receiving end usually receives unwanted echo (echo); the echo comes from the signal transmitting end and is related to the output signal transmitted by the signal transmitting end. The signal receiving end usually implements an echo cancellation circuit for canceling echo, and the echo cancellation circuit cancels echo according to an echo cancellation signal provided by the signal transmitting end. Generally, in an actual circuit, there is a physical distance (i.e., a first physical distance) between a circuit generating an output signal and a signal receiving end, and there is another physical distance (i.e., a second physical distance) between a circuit generating an echo cancellation signal and the signal receiving end; unfortunately, because the first physical distance is not exactly equal to the second physical distance, there is a phase difference between the echo and the echo cancellation signal, resulting in a hybrid echo at the signal receiving end. Too much echo can cause performance degradation in the transceiver circuit or the system in which it is used, or even some unexpected errors. Therefore, a circuit or method is needed to reduce or eliminate the hybrid echo.

Disclosure of Invention

In view of the deficiencies of the prior art, it is an object of the present invention to provide a signal transceiving circuit, a method of operating a signal transceiving circuit, and a method of providing a delay circuit to improve the deficiencies of the prior art.

The invention discloses a signal transceiver circuit, which is used for transmitting an output signal and receiving an input signal, and comprises: a delay circuit for delaying the first clock to generate a second clock; a first digital-to-analog converter for converting a first digital signal into the output signal according to the first clock; a second digital-to-analog converter coupled to the delay circuit for converting the first digital signal into an echo cancellation signal according to the second clock; an analog front-end circuit for receiving the input signal and the echo cancellation signal and generating an analog signal; and an analog-to-digital converter coupled to the analog front end circuit for converting the analog signal to a second digital signal.

The invention also discloses a method for setting the delay circuit, the delay circuit is applied to a signal transceiver circuit and delays a first clock according to a delay parameter to generate a second clock, the signal transceiver circuit comprises a first digital-to-analog converter, a second digital-to-analog converter and an analog-to-digital converter, the first digital-to-analog converter operates according to the first clock, the second digital-to-analog converter operates according to the second clock, and the analog-to-digital converter generates a digital signal. The method comprises the following steps: (A) setting the delay parameter of the delay circuit; (B) measuring the power of the digital signal at a plurality of phases to be measured to generate a plurality of measured powers; (C) calculating an average power of the plurality of measured powers, the average power corresponding to the delay parameter; (D) repeating steps (a) through (D) to produce a plurality of average powers; and (E) setting the delay circuit with the delay parameter corresponding to the minimum of the average powers.

The invention also discloses a method for operating a signal transmitting circuit, which transmits an output signal and comprises a delay circuit, a first digital-to-analog converter and a second digital-to-analog converter. The method comprises the following steps: providing a first clock to the delay circuit and the first digital-to-analog converter; the first digital-to-analog converter converts a digital signal into the output signal according to the first clock; the delay circuit delays the first clock to generate a second clock; providing the second clock to the second digital-to-analog converter; and the second digital-to-analog converter converts the digital signal into an echo cancellation signal according to the second clock.

The features, implementations and functions of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

Drawings

FIG. 1 is a functional block diagram of an embodiment of a signal transceiver circuit of the present invention;

FIG. 2 is a flow chart of a method of operation of the signaling circuit of the present invention;

FIG. 3 is a flow chart of a method of setting a delay circuit of the present invention; and

fig. 4A-4C are schematic diagrams of waveforms of the echo Vout', the echo cancellation signal Vec, and the hybrid echo.

Detailed Description

The technical terms in the following description refer to the conventional terms in the technical field, and some terms are explained or defined in the specification, and the explanation of the some terms is based on the explanation or the definition in the specification.

The present disclosure includes a signal transceiving circuit, a method of operating a signal transmitting circuit, and a method of setting a delay circuit. Since some of the components included in the transceiver circuit of the present invention may be known components alone, the following description will omit details of the known components without affecting the full disclosure and feasibility of the present invention. In addition, part or all of the flow of the method for setting the delay circuit of the present invention may be in the form of software and/or hardware, and the following description of the method invention will focus on the content of steps rather than hardware without affecting the full disclosure and feasibility of the method invention.

Fig. 1 is a functional block diagram of a signal transceiver circuit according to an embodiment of the present invention. Signal transceiving circuit 100 is coupled to digital processing circuit 200. The digital output signal Dout generated by the digital processing circuit 200 is converted into the output signal Vout by the signal transceiver circuit 100 and transmitted (e.g., transmitted via an antenna). The signal transceiving circuit 100 receives an external input signal Vin (e.g., via an antenna), and then generates a digital input signal Din.

The signal transceiver circuit 100 includes a signal transmitter circuit 110 and a signal receiver circuit 120. The signal transmitting circuit 110 includes a digital-to-analog converter 112, a digital-to-analog converter 114, and a delay circuit 116. The signal receiving circuit 120 includes an analog front-end (analog front-end) circuit 122 and an analog-to-digital converter 124.

The digital-to-analog converter 112 operates according to a clock CLK to convert the digital output signal Dout generated by the digital processing circuit 200 into an output signal Vout. The echo Vout' of the output signal Vout is transmitted to the analog front end circuit 122 of the signal receiving circuit 120 via the echo path 130. The digital-to-analog converter 114 operates according to the clock CLK' to convert the digital output signal Dout into the echo cancellation signal Vec. The analog front-end circuit 122 is used to process (e.g., amplify, downconvert, etc.) the input signal Vin, and another purpose of the analog front-end circuit 122 is to cancel the echo Vout ' with the echo cancellation signal Vec to reduce the interference of the echo Vout ' with the input signal Vin (i.e., the goal is to make the analog signal Sin not include the echo Vout '). The analog-to-digital converter 124 is used to convert the analog signal Sin into a digital input signal Din.

The delay circuit 116 is used to delay the clock CLK to generate the clock CLK'. The digital processing circuit 200 controls the delay parameter of the delay circuit 116 with the control signal SC. For example, the delay circuit 116 includes a capacitor array and a plurality of switches (the switches are controlled by the control signal SC), whether the switches are turned on or off determines the number of series/parallel capacitors (i.e., determines the equivalent capacitance of the capacitor array), and the equivalent capacitance of the capacitor array (i.e., the delay parameter of the delay circuit 116) is related to the delay amount of the delay circuit 116.

In some cases, the digital-to-analog converter 114 is located closer to the analog front end circuit 122 than the digital-to-analog converter 112 in actual circuitry, resulting in a phase difference between the echo Vout' and the echo cancellation signal Vec (i.e., causing a hybrid echo at the signal receiving circuit 120). To address this issue, the delay circuit 116 delays the clock CLK so that the clock CLK 'lags the clock CLK (i.e., the phase of the clock CLK' is later than the phase of the clock CLK). Making the phase of the clock CLK 'later than that of the clock CLK is equivalent to making the echo cancellation signal Vec of the digital-analog converter 114 come out later than the output signal Vout of the digital-analog converter 112, so that the phase difference between the echo Vout' and the echo cancellation signal Vec in the signal receiving circuit 120 is small (compared with using the same clock for the digital-analog converter 112 and the digital-analog converter 114), and thus the mixed echo can be effectively reduced.

The details of the delay circuit 116 are known to those skilled in the art and will not be described further. In some embodiments, delay circuit 116 may be implemented with a phase interpolator that phase interpolates (i.e., phase interpolates from) clock CLK to generate clock CLK'. In other words, the phase interpolator achieves the effect of delaying the clock CLK by means of phase interpolation. The control of the phase interpolator by the digital control signal SC is well known to those skilled in the art and will not be described in detail (please refer to http:// iram. cs. berkeley. edu/serialo/cs 254/interpolator. html).

Referring to fig. 2, fig. 2 is a flowchart of an operation method of the signal transmitting circuit according to the present invention, including the following steps.

Step S210: the clock CLK is provided to the delay circuit 116 and the digital-to-analog converter 112 (i.e., the first digital-to-analog converter).

Step S220: the digital-to-analog converter 112 converts the digital output signal Dout into an output signal Vout according to the clock CLK.

Step S230: the delay circuit 116 delays the clock CLK to generate the clock CLK'. For a phase interpolator, interpolating the generated clock CLK 'from the clock CLK is equivalent to delaying the clock CLK to generate the clock CLK'.

Step S240: a clock CLK' is provided to the digital-to-analog converter 114 (i.e., the second digital-to-analog converter).

Step S250: the digital-to-analog converter 114 converts the digital output signal Dout into the echo cancellation signal Vec according to the clock CLK'.

The following discusses how the delay parameter of the delay circuit 116 is determined. Referring to fig. 3, fig. 3 is a flowchart of a method for setting a delay circuit according to the present invention, which includes the following steps.

Step S310: the delay parameter of the delay circuit 116 is set. For example, the digital processing circuit 200 controls the equivalent capacitance of the delay circuit 116 by the control signal SC. For another example, if the delay circuit 116 is implemented as a phase interpolator, the step can be that the digital processing circuit 200 controls the switch inside the phase interpolator via the control signal SC.

Step S320: the digital processing circuit 200 determines the phase to be measured.

Step S330: the digital processing circuit 200 measures the power of the digital input signal Din at the phase to be measured to generate a measured power corresponding to the phase to be measured.

Step S340: the digital processing circuit 200 determines whether there is still a phase to be measured. In some embodiments, digital processing circuit 200 measures the power of digital input signal Din at a plurality of phases to be measured within a symbol duration (symbol duration) of digital input signal Din, where symbol duration is the inverse of the symbol rate (symbol rate) of digital input signal Din. For example, if the digital processing circuit 200 is configured to measure the power of the digital input signal Din at N phases to be measured (N is a positive integer), the digital processing circuit 200 performs steps S320 and S330N times, and obtains N measured powers (corresponding to the N phases to be measured, respectively). When there is no unprocessed phase to be measured (no in step S340), the digital processing circuit 200 executes step S350.

Step S350: the digital processing circuit 200 calculates the average of the N measured powers, the average power generated by this step corresponding to the delay parameter set in step S310. In other words, one delay parameter corresponds to one average power.

Step S360: the digital processing circuit 200 determines whether to continue setting the delay parameter of the delay circuit 116. For example, if the physical distance difference between the DAC 112 and the DAC 114 is approximately equivalent to the range of 0-250 ps (picoseconds), and the delay resolution of the delay circuit 116 is 2.5ps, the digital processing circuit 200 sets the delay circuit 116 with M delay parameters (M is an integer and 1. ltoreq. M.ltoreq.100, corresponding to delay times 2.5ps, 5.0ps, …, 247.5ps, and 250ps, respectively). When all the delay parameters have been used (i.e., the digital processing circuit 200 does not select the next delay parameter, no in step S360), the digital processing circuit 200 performs step S370, otherwise the digital processing circuit 200 performs step S310.

Step S370: the digital processing circuit 200 determines the final delay parameter for the delay circuit 116. More specifically, the digital processing circuit 200 finds the minimum value of the M average powers, and takes the delay parameter corresponding to the minimum average power as the final delay parameter, and then sets the delay circuit 116 with the final delay parameter.

As described above, the process of fig. 3 may determine a preferred delay parameter for the delay circuit 116, so that the power of the digital input signal Din is relatively small (i.e., the hybrid echo contained therein is relatively small). In some embodiments, digital processing circuit 200 implements the flow of FIG. 3 in a Finite State Machine (FSM). In other embodiments, digital processing circuit 200 is a circuit with program execution capabilities that executes program code or program instructions (e.g., stored in memory circuit 210 of digital processing circuit 200) to complete the flow of fig. 3.

Referring to fig. 4A-4C, fig. 4A-4C are schematic diagrams of waveforms of the echo Vout ', the echo cancellation signal Vec, and the hybrid echo (i.e., Vout' -Vec), where fig. 4A-4C correspond to different delay parameters (i.e., fig. 4A-4C have respective average powers). "T" in fig. 4A-4C represents the symbol duration of the digital input signal Din, while the points in time T1, T2,. solstice, tk,. solstice, tN each correspond to a phase to be measured (1 ≦ k ≦ N). As shown in fig. 4B, the amplitude of the hybrid echo corresponding to time point t1 is 0, and the amplitude of the hybrid echo corresponding to time point t2 is not 0. It can be seen that if steps S320 and S330 are performed only once, the sampling rate may be too low (possibly accompanied by aliasing distortion (aliasing)) to cause a false determination (i.e. if the power is measured at time t1, a smaller power is obtained, and the hybrid echo is mistaken to be relatively smaller). The purpose of the method of fig. 3 is to find the delay parameter corresponding to a relatively small hybrid echo. When the resolution of the delay circuit 116 is high enough, the process of fig. 3 can ideally find the final delay parameter that substantially aligns the echo Vout' with the echo cancellation signal Vec (i.e., the phase difference between the two is substantially 0, as shown in fig. 4C).

In summary, the present invention overcomes or cancels the signal delay caused by the signal path difference on the physical circuit by delaying the clock of the digital-to-analog converter, so as to obtain better echo cancellation effect (i.e. lower amplitude or power of the mixed sound). Therefore, the signal transceiving circuit of the invention has better performance.

Since the detailed implementation and the variations of the method and the invention can be understood by those skilled in the art with the aid of the disclosure of the apparatus and the invention of the present invention, the repeated descriptions are omitted here for avoiding the redundancy and without affecting the disclosure requirement and the implementability of the method and the invention. It should be noted that the shapes, sizes and proportions of the components in the foregoing figures are merely illustrative and not intended to limit the invention, which is understood by those skilled in the art. In addition, in some embodiments, the steps mentioned in the flowcharts disclosed in the foregoing may be performed in any order, or may even be performed simultaneously or partially simultaneously.

Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can make variations on the technical features of the present invention according to the explicit or implicit contents of the present invention, and all such variations may fall within the scope of the patent protection sought by the present invention.

[ notation ] to show

100: signal receiving and transmitting circuit

200: digital processing circuit

Dout: digital output signal

Vout: output signal

Vin: input signal

Din: digital input signal

110: signal transmission circuit

120: signal receiving circuit

112. 114: digital-to-analog converter

116: delay circuit

122: analog front-end circuit

124: analog-to-digital converter

CLK, CLK': clock (CN)

Vout': echo

130: echo path

Vec: echo cancellation signal

Sin: analog signal

SC: control signal

210: memory circuit

t1, t2, tk, tN: point in time

T: symbol duration

S210、S220、S230、S240、S250、S310、S320、S330、S340、

S350, S360, S370: step (ii) of

Claims (7)

1. A signal transceiver circuit for transmitting an output signal and receiving an input signal, comprising:

a delay circuit for delaying the first clock to generate a second clock;

a first digital-to-analog converter for converting a first digital signal into the output signal according to the first clock;

a second digital-to-analog converter coupled to the delay circuit for converting the first digital signal into an echo cancellation signal according to the second clock;

the analog front-end circuit is used for receiving the input signal and the echo cancellation signal and generating an analog signal; and

an analog-to-digital converter coupled to the analog front end circuit to convert the analog signal to a second digital signal.

2. The signal transceiving circuit of claim 1, wherein said delay circuit is a phase interpolator.

3. A method of setting a delay circuit, the delay circuit being applied to a signal transceiving circuit and delaying a first clock according to a delay parameter to generate a second clock, the signal transceiving circuit comprising a first digital-to-analog converter, a second digital-to-analog converter and an analog-to-digital converter, the first digital-to-analog converter operating according to the first clock, the second digital-to-analog converter operating according to the second clock, the analog-to-digital converter generating a digital signal, the method comprising:

(A) setting the delay parameter of the delay circuit;

(B) measuring the power of the digital signal at a plurality of phases to be measured to generate a plurality of measured powers;

(C) calculating an average power of the plurality of measured powers, the average power corresponding to the delay parameter;

(D) repeating steps (a) through (D) to produce a plurality of average powers; and

(E) setting the delay circuit with the delay parameter corresponding to the minimum of the plurality of average powers.

4. The method of claim 3, wherein the plurality of phases to be measured are a plurality of phases within a symbol duration of the digital signal.

5. The method of claim 3, wherein the delay circuit is a phase interpolator.

6. A method of operating a signal sending circuit that sends an output signal and includes a delay circuit, a first digital-to-analog converter, and a second digital-to-analog converter, the method comprising:

providing a first clock to the delay circuit and the first digital-to-analog converter;

the first digital-to-analog converter converts a digital signal into the output signal according to the first clock;

the delay circuit delays the first clock to generate a second clock;

providing the second clock to the second digital to analog converter; and

and the second digital-analog converter converts the digital signal into an echo cancellation signal according to the second clock.

7. The method of claim 6, wherein the delay circuit is a phase interpolator.

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