CN112583431B - Receiver and related signal processing method - Google Patents
Receiver and related signal processing method Download PDFInfo
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- CN112583431B CN112583431B CN201910936080.4A CN201910936080A CN112583431B CN 112583431 B CN112583431 B CN 112583431B CN 201910936080 A CN201910936080 A CN 201910936080A CN 112583431 B CN112583431 B CN 112583431B
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- echo cancellation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
Abstract
The invention discloses a receiver and a related signal processing method. The receiver includes an analog-to-digital converter, an echo cancellation circuit and a control circuit. In operation of the receiver, the analog-to-digital converter performs an analog-to-digital conversion operation on an analog input signal according to a frequency signal to generate a digital input signal, the echo cancellation circuit performs an echo cancellation operation on the digital input signal according to a plurality of tap coefficients to generate an output signal, and the control circuit controls a phase of the frequency signal input into the analog-to-digital converter; and when the phase of the frequency signal changes, the control circuit calculates a plurality of updated joint coefficients according to the joint coefficients used by the echo cancellation circuit at the previous time point, so as to be used by the echo cancellation circuit.
Description
Technical Field
The present invention relates to a receiver, and more particularly, to a receiver including an echo cancellation circuit.
Background
In a full-duplex ethernet (full-duplex ethernet) system, since the same transmission line has both transmission signal and reception signal, if there is impedance mismatch between the transmission lines or mismatch between the receiver and the related circuit architecture, some of the signal components in the transmission signal will bounce back to the reception path, and these bounced signal components are generally called echo signals. Since the high frequency component of the transmitted signal is usually hard to penetrate and easy to bounce back, the high frequency component of the echo signal is abundant, so that the effective bandwidth of the echo signal is usually not less than half of the frequency signal used by the receiver. Thus, aliasing occurs when the echo signal is returned to the receiver and the receiver uses the frequency signal to sample the echo signal.
In order to reduce the influence of the echo signal, the receiver adjusts the phase of the frequency signal to perform sampling operation or analog-to-digital conversion operation on the echo signal, so as to obtain the frequency response of the digital echo signal under different phases of the frequency signal, so that the relevant circuit can adjust the frequency response to obtain the optimal phase of the frequency signal. Generally, the phase of the frequency signal is usually adjusted by a low amount each time to avoid affecting the quality of the received signal, for example, the phase may be adjusted by a period of the frequency signal (1/1024), which, however, greatly increases the cost of the phase selector in the analog circuit.
Disclosure of Invention
It is therefore an object of the present invention to provide a receiver, in which the frequency signal can have a larger phase adjustment amount, such as the period of the frequency signal (1/128), without affecting the quality of the received signal, so as to solve the problems described in the prior art.
In one embodiment of the present invention, a receiver is disclosed, which comprises an analog-to-digital converter, an echo cancellation circuit and a control circuit. In operation of the receiver, the analog-to-digital converter performs analog-to-digital conversion on an analog input signal according to a frequency signal to generate a digital input signal, the echo cancellation circuit performs echo cancellation on the digital input signal according to a plurality of joint coefficients to generate an output signal, and the control circuit controls the phase of the frequency signal input into the analog-to-digital converter; and when the phase of the frequency signal changes, the control circuit calculates a plurality of updated joint coefficients according to the joint coefficients used by the echo cancellation circuit at the previous time point, so as to be used by the echo cancellation circuit.
In another embodiment of the present invention, a signal processing method is disclosed, which includes the following steps: performing analog-to-digital conversion on an analog input signal according to a frequency signal to generate a digital input signal; performing echo cancellation operation on the digital input signal according to a plurality of joint coefficients to generate an output signal; controlling a phase of the frequency signal input into the analog-to-digital converter; and when the phase of the frequency signal is changed, calculating a plurality of updated joint coefficients according to the joint coefficients used at least at the previous time point so as to be used for echo cancellation operation.
Drawings
Fig. 1 is a diagram illustrating a chip applied to a full duplex ethernet system according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating phase adjustment of a frequency signal and updating tap coefficients.
FIG. 3 is a schematic diagram of generating updated joint coefficients based on whether the two phase change directions are the same.
FIG. 4 is a diagram illustrating the comparison of the SNR of the present embodiment and the prior art.
Fig. 5 is a flowchart of a signal processing method according to an embodiment of the invention.
Detailed Description
Fig. 1 is a diagram illustrating a chip 100 applied to a full duplex ethernet system according to an embodiment of the present invention. As shown in fig. 1, the chip 100 includes a transmitter 110, a receiver 120, and a processing circuit 130, wherein the receiver 120 includes an analog-to-digital converter 122, a control circuit 124, an echo cancellation circuit 126, and a frequency generation circuit 128.
When the chip 100 is in operation, the processing circuit 130 transmits data to another electronic device located outside the chip 100, and the processing circuit 130 transmits the data to the transmitter 110 to generate a transmission signal and transmits the transmission signal to the other electronic device via an external transmission line. However, if the transmission line has impedance mismatch, a part of the signal component of the transmission signal bounces back into the receiving path to become an echo signal, so the analog input signal Vin received by the receiver 120 also includes the echo signal in addition to the data from the other electronic device, especially the echo signal is usually a high frequency signal, thereby affecting the signal quality. In order to reduce the influence of the echo signal, the control circuit 124 in the receiver 120 generates the control signal Vc1 to the frequency generation circuit 128, so that the frequency generation circuit 128 adjusts the phase of the generated frequency signal CLK, so that the analog-to-digital converter 122 performs sampling and analog-to-digital conversion operations on the analog input signal Vin to generate a digital input signal Din, and the control circuit 124 obtains the frequency responses of the frequency signal CLK at different phases according to the digital input signal Din, so as to be used as the basis for phase adjustment of the frequency signal CLK. Simultaneously, the echo cancellation circuit 126 performs an echo cancellation operation on the digital input signal Din to generate an output signal Dout. On the other hand, in order to reduce the manufacturing cost of the frequency generation circuit 128, the frequency signal CLK has a large phase adjustment amount, for example, 1/128 of the frequency signal period is obtained every time the phase adjustment of the frequency signal CLK is performed. However, due to the larger phase adjustment amount, the digital input Signal Din also has a larger change at the time point of the phase change of the frequency Signal CLK, and the Signal-to-Noise Ratio (SNR) of the output Signal Dout is reduced if the tap coefficient (tap coefficient) in the echo cancellation circuit 126 is not updated as soon as possible. To solve this problem, the present invention provides a method for predicting the tap coefficients required in the echo cancellation circuit 126, which can rapidly update the tap coefficients of the echo cancellation circuit 126 when the phase of the frequency signal CLK changes, so as to avoid affecting the signal quality of the output signal Dout.
It should be noted that, since the mechanism for controlling the phase of the frequency signal CLK for the adc 122 and the circuit architecture of the echo cancellation circuit 126 (for example, including an active filter for performing filtering processing by using a plurality of tap coefficients) are well known in the art, and the key point of the present invention is how to generate updated tap coefficients for the echo cancellation circuit, the detailed circuits of the frequency generation circuit 128 and the echo cancellation circuit 126 are not described herein.
Referring to fig. 2, a diagram of phase adjustment and joint coefficient update is shown, wherein each block shown in the diagram can be a data amount of the digital input signal Din during a period of time or a processing unit of Fast Fourier Transform (FFT). In fig. 2, when the echo cancellation circuit 126 starts to process the first block, the control circuit 124 checks whether the phase of the clock signal CLK needs to be changed, and if the phase of the clock signal CLK needs to be changed, the control circuit 124 records a plurality of tap coefficients currently used by the echo cancellation circuit 126 as a plurality of first tap coefficients EC1, and then generates the control signal Vc1 to the clock generation circuit 128 to adjust the phase of the clock signal CLK. In the embodiment, it is assumed that the phase of the clock signal CLK is adjusted for the first time, and therefore, after the phase of the clock signal CLK is adjusted, the echo cancellation circuit 126 updates the adjusted internal tap coefficients by using its own adaptive algorithm, so as to effectively perform the echo cancellation operation on the digital input signal Din. In addition, in order to avoid the clock signal CLK continuously changing its phase after convergence is stable, the control circuit 124 sets a minimum delay time TR for the clock signal CLK during phase adjustment to reduce unnecessary phase changes.
Next, after the shortest delay time TR, when the echo cancellation circuit 126 starts to process the fifth block, the control circuit 124 checks whether the phase of the clock signal CLK needs to be changed, and if the phase of the clock signal CLK needs to be changed, the control circuit 124 records a plurality of tap coefficients currently used by the echo cancellation circuit 126 as a plurality of second tap coefficients EC2, and then generates the control signal Vc1 to the clock generation circuit 128 to adjust the phase of the clock signal CLK. At this time, the control circuit 124 generates a plurality of updated tap coefficients EC3 for the echo cancellation circuit to use according to the directions of the two phase changes and the recorded first tap coefficients EC1 and/or second tap coefficients EC 2. Specifically, referring to fig. 3, assuming that CLK (PH1), CLK (PH2), and CLK (PH3) shown in the figure represent phases of the frequency signal CLK before the first phase adjustment, after the first phase adjustment, and after the second phase adjustment shown in fig. 2, respectively, in fig. 3(a), since the two phases of the frequency signal CLK are the same direction, the control circuit 124 performs extrapolation calculation on the plurality of first joint coefficients EC1 and the plurality of second joint coefficients EC2 to generate a plurality of updated joint coefficients EC3, i.e., EC3 is 2 × EC2-EC 1. On the other hand, in fig. 3(b), since the direction of the first change of the phase of the frequency signal is different from that of the second change, the control circuit 124 directly uses the plurality of first tap coefficients EC1 as the plurality of updated tap coefficients EC 3.
As described above, since the control circuit 124 predicts a plurality of updated tap coefficients required later according to a plurality of head coefficients used by the previous echo cancellation circuit 126 and can be used by the echo cancellation circuit 126 at an appropriate time point, the problem of poor signal quality caused by the fact that the tap coefficients of the echo cancellation circuit 126 cannot be updated to appropriate values quickly after the phase of the clock signal CLK is switched can be effectively avoided. In addition, "Td" shown in fig. 2 represents the time when the noise caused by the phase change of the frequency signal CLK affects the echo cancellation circuit 126, that is, the echo cancellation circuit 126 can perform the echo cancellation operation by using the updated tap coefficient EC3 calculated by the control circuit 124 when "Td" passes after the phase change of the frequency signal CLK.
It should be noted that after the echo cancellation circuit 126 performs the echo cancellation operation using the updated tap coefficient EC3 calculated by the control circuit 124, the adaptive algorithm itself is still used to further update the tap coefficient inside the adjustment, so as to perform the echo cancellation operation on the digital input signal Din more effectively.
FIG. 4 shows the comparison of the signal-to-noise ratio of the present embodiment and the prior art. As shown in the left side of fig. 4, each phase change of the clock signal CLK in the prior art will cause the signal-to-noise ratio of the output signal Vout to be decreased, while as shown in the right side of fig. 4, the phase change of the clock signal CLK in the present embodiment will not cause too much influence on the signal-to-noise ratio of the output signal Vout except for the first phase change of the clock signal CLK.
Fig. 5 is a flowchart of a signal processing method according to an embodiment of the invention. With reference to the contents described in the above embodiments, the flow of the signal processing method is as follows.
Step 500: the process begins.
Step 502: an analog-to-digital conversion is performed on an analog input signal according to a frequency signal to generate a digital input signal.
Step 504: an echo cancellation circuit is used to perform an echo cancellation operation on the digital input signal according to a plurality of tap coefficients to generate an output signal.
Step 506: and controlling the phase of the frequency signal, wherein when the phase of the frequency signal changes, a plurality of updated joint coefficients are calculated according to the joint coefficients used by the echo cancellation circuit at the previous time point so as to be used for echo cancellation operation.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention should be covered by the present invention.
[ notation ] to show
100 chip
110 transmitter
120 receiver
122 analog-to-digital converter
124 control circuit
126 echo cancellation circuit
128 frequency generating circuit
130 processing circuit
500. 502, 504, 506
CLK frequency signal
Din digital input signal
Dout output signal
Vc1 control signal
Vin simulates an input signal.
Claims (10)
1. A receiver, comprising:
an analog-to-digital converter for performing an analog-to-digital conversion operation on an analog input signal according to a frequency signal to generate a digital input signal;
an echo cancellation circuit, coupled to the adc, for performing an echo cancellation operation on the digital input signal according to a plurality of tap coefficients to generate an output signal; and
a control circuit coupled to the analog-to-digital converter and the echo cancellation circuit for controlling the phase of the frequency signal inputted into the analog-to-digital converter, and when the phase of the frequency signal changes, the control circuit calculates a plurality of updated tap coefficients according to the tap coefficients used by the echo cancellation circuit at a previous time point, so as to be used by the echo cancellation circuit.
2. The receiver of claim 1 wherein the control circuit calculates the updated tap coefficients for use by the echo cancellation circuit based on the tap coefficients used by the echo cancellation circuit at least one of two different points in time.
3. The receiver of claim 2, wherein the two different time points correspond to two phase changes of the frequency signal respectively.
4. The receiver of claim 3 wherein the control circuit calculates the updated tap coefficients for use by the echo cancellation circuit based on the direction of the two phase changes of the frequency signal and the tap coefficients used by the echo cancellation circuit at least one of the two different time points.
5. The receiver of claim 4 wherein the control circuit extrapolates the plurality of tap coefficients used by the echo cancellation circuit at the two different points in time to generate the plurality of updated tap coefficients when the direction of the two phase changes of the frequency signal is the same.
6. The receiver of claim 4, wherein the control circuit directly uses the plurality of tap coefficients used by the echo cancellation circuit at an earlier of the two different time points as the plurality of updated tap coefficients when the directions of the two phase changes of the frequency signal are different.
7. The receiver of claim 4 wherein when the phase of the frequency signal is changed for the first time, the control circuit records the tap coefficients currently used by the echo cancellation circuit as first tap coefficients and then changes the phase of the frequency signal; when the phase of the frequency signal is changed for the second time, the control circuit records the joint coefficients used by the echo cancellation circuit at present as a plurality of second joint coefficients, and calculates the updated joint coefficients according to the first joint coefficients and/or the second joint coefficients so as to be used by the echo cancellation circuit after the phase of the frequency signal is changed for the second time.
8. The receiver of claim 7 wherein the control circuit extrapolates the first and second plurality of tap coefficients to generate the updated plurality of tap coefficients when the phase of the frequency signal changes in the same direction as the second change; and when the phase of the frequency signal changes in the first and second directions, the control circuit directly uses the first joint coefficients as the updated joint coefficients.
9. A signal processing method comprises the following steps:
performing analog-to-digital conversion operation on an analog input signal according to a frequency signal to generate a digital input signal;
using an echo cancellation circuit to perform an echo cancellation operation on the digital input signal according to a plurality of joint coefficients to generate an output signal;
controlling the phase of the frequency signal; and
when the phase of the frequency signal is changed, a plurality of updated joint coefficients are calculated according to the joint coefficients used by the echo cancellation circuit at a previous time point, so as to be used for echo cancellation operation.
10. The signal processing method of claim 9 wherein the step of calculating a plurality of updated tap coefficients for use in an echo cancellation operation based on at least the plurality of tap coefficients used by the echo cancellation circuit at a previous time point when the phase of the frequency signal changes comprises:
calculating a plurality of updated joint coefficients according to the joint coefficients used by the echo cancellation circuit at least at one of two different time points, so as to be used for the echo cancellation operation;
wherein the two different time points correspond to two phase changes of the frequency signal respectively.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101002263A (en) * | 2004-08-03 | 2007-07-18 | 松下电器产业株式会社 | Reproduced signal processing device |
| JP2008042816A (en) * | 2006-08-10 | 2008-02-21 | Oki Electric Ind Co Ltd | Echo canceller |
| CN101814934A (en) * | 2009-02-20 | 2010-08-25 | 瑞昱半导体股份有限公司 | Communication device with echo cancellation function and method thereof |
| CN101924973A (en) * | 2009-06-12 | 2010-12-22 | 索尼公司 | Signal processing apparatus and signal processing method for loudspeaker motional feedback |
| CN109151237A (en) * | 2018-08-23 | 2019-01-04 | 西南交通大学 | The illumination-imitation projection self-adoptive echo cancel method attracted based on zero |
| CN110199351A (en) * | 2017-01-13 | 2019-09-03 | 舒尔获得控股公司 | Echo cancelling system and method after mixing |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7480326B2 (en) * | 2002-07-17 | 2009-01-20 | Broadcom Corporation | Channel diagnostic systems and methods |
| JP4094444B2 (en) * | 2003-01-31 | 2008-06-04 | 株式会社エヌ・ティ・ティ・ドコモ | Wireless communication terminal |
| US8160239B2 (en) * | 2006-11-10 | 2012-04-17 | Sony Corporation | Echo canceller and speech processing apparatus |
| US8513952B2 (en) * | 2007-12-11 | 2013-08-20 | Marvell International Ltd. | Sub-symbol rate cable tester |
-
2019
- 2019-09-29 CN CN201910936080.4A patent/CN112583431B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101002263A (en) * | 2004-08-03 | 2007-07-18 | 松下电器产业株式会社 | Reproduced signal processing device |
| JP2008042816A (en) * | 2006-08-10 | 2008-02-21 | Oki Electric Ind Co Ltd | Echo canceller |
| CN101814934A (en) * | 2009-02-20 | 2010-08-25 | 瑞昱半导体股份有限公司 | Communication device with echo cancellation function and method thereof |
| CN101924973A (en) * | 2009-06-12 | 2010-12-22 | 索尼公司 | Signal processing apparatus and signal processing method for loudspeaker motional feedback |
| CN110199351A (en) * | 2017-01-13 | 2019-09-03 | 舒尔获得控股公司 | Echo cancelling system and method after mixing |
| CN109151237A (en) * | 2018-08-23 | 2019-01-04 | 西南交通大学 | The illumination-imitation projection self-adoptive echo cancel method attracted based on zero |
Non-Patent Citations (2)
| Title |
|---|
| Mechanical Fault Diagnostics of PowerTransformer On-loadTap Changers Based onMarginal Point Distribution Coefficient;qinqinghuang;《IEEE》;20190107;全文 * |
| 滤波多音调制FMT中迭代接收算法;李毅辉;《CNKI优秀硕士学位论文全文库》;20181231;全文 * |
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