CN100438021C - 无外引脚半导体封装构造及其制造方法 - Google Patents

无外引脚半导体封装构造及其制造方法 Download PDF

Info

Publication number
CN100438021C
CN100438021C CNB2004100118635A CN200410011863A CN100438021C CN 100438021 C CN100438021 C CN 100438021C CN B2004100118635 A CNB2004100118635 A CN B2004100118635A CN 200410011863 A CN200410011863 A CN 200410011863A CN 100438021 C CN100438021 C CN 100438021C
Authority
CN
China
Prior art keywords
semiconductor device
chip bearing
pin
semiconductor
packaging structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CNB2004100118635A
Other languages
English (en)
Other versions
CN1753179A (zh
Inventor
寇宽旺
金颂悟
卜桑贝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
Original Assignee
Advanced Semiconductor Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Priority to CNB2004100118635A priority Critical patent/CN100438021C/zh
Publication of CN1753179A publication Critical patent/CN1753179A/zh
Application granted granted Critical
Publication of CN100438021C publication Critical patent/CN100438021C/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4905—Shape
    • H01L2224/49051—Connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01083—Bismuth [Bi]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

本发明涉及一种半导体封装构造，包含一半导体装置通过锡膏稳固贴附于一芯片承座的一上表面上，以及多个引脚配置于该芯片承座周围附近，该芯片承座及该引脚的厚度介于10至20μm之间，各该引脚具有一半蚀刻凹处，而该半蚀刻凹处的位置相对一预定切割线，该半导体装置电性连接于该引脚中之一，一封胶体形成于该半导体装置及该引脚上，其中该芯片承座及该引脚的下表面由该封胶体裸露出，较佳地，该半导体装置通过至少一条大尺寸铝线电性连接于该引脚中之一。本发明另提供一种上述半导体封装构造的制造方法。

Description

无外引脚半导体封装构造及其制造方法
技术领域
本发明涉及一种无外引脚半导体封装构造，特别是一种无外引脚半导体封装构造及其制造方法。
背景技术
于集成电路的封装历史中，导线架封装构造已经长期被使用，其主要原因是具有低制造成本及高可靠度。然而，由于集成电路产品不断地朝快速及小尺寸的目标努力，因此对一些具有高性能需求的封装构造，传统导线架封装构造已逐渐被淘汰。因此，球格阵列矩阵(BallGrid Array；BGA)封装构造及芯片尺寸封装构造(Chip Size Package)已经出现，并变成越来越流行的另一种新的封装选择。前者已经广泛地使用于集成电路的芯片中，其中该芯片具有较高的输入/输出数目，且相较于现有封装构造，诸如中央处理单元(Central Processing Unit；CPU)及绘图芯片，前者具有较佳的电气性能及热性能。后者已经广泛地使用于可携带的产品，其接脚(Footprint)、封装外形及封装重量为主要考量。
然而，导线架封装构造仍保有其市场占有率，因为对低输入/输出数目的集成电路而言，仍具有成本效益。由于具有长内引脚及外引脚，传统导线架封装构造被限制应用于芯片尺寸封装构造及低外形封装构造。因此，半导体封装构造工业发展一种不具有外引脚的无外引脚封装构造，如此使接脚(footprint)及封装外形大幅减少。相较于现有鸥翼(Gull-wing)型式及J引脚(J-leaded)型式，图1及2显示一无外引脚封装构造10，其多个引脚11a配置于该封装构造的底部。该无外引脚封装构造10的芯片承座11b由该封装构造的底部裸露出，由此提供较佳的散热。典型地，四个支撑肋条11c连接于该芯片承座11b。该无外引脚封装构造10包含一芯片12，其包封于一封胶体13中。该芯片12的主动表面设有多个打线接垫(图中未示)，通过多条焊线电性连接于该多个引脚11a。
基于外引脚的移除，该无外引脚封装构造具有低封装外型及低重量的特征。再者，由于它所使用的材料为存在的材料清单(Bill ofMaterial；BOM)中，因此该无外引脚封装构造10亦具有成本效益。所有上述特质使得目前无外引脚封装构造非常适用于通讯产品，诸如移动电话、可携带式产品，诸如个人数字助理(Personal Digital Assistant；PDA)、数字相机及信息装置(Information Appliance；IA)。因为计算机及其它电子设备的性能需求的增加，半导体装置操作更高的电力，且被制造更高半导体装置的密度。因此，半导体装置的热性能更是被重视。然而，目前可获得的无外引脚封装构造无法符合应用于汽车、工业及商业的高电力的散热(dissipation)需求。
发明内容
本发明的目的在于克服现有技术的不足与缺陷，提供一种无外引脚封装构造，能够符合应用于汽车、工业及商业的高电力的散热(dissipation)需求。
为达上述目的，本发明提供一种半导体封装构造，包含一第一半导体装置(诸如一电力半导体装置(power semiconductor device))通过例如锡膏(solder paste)稳固地贴附于一第一芯片承座的一上表面上，以及多个引脚配置于该第一芯片承座周围附近。该第一芯片承座及该引脚的厚度介于10至20μm之间。各该引脚具有一半蚀刻凹处，而该半蚀刻凹处的位置相对一预定切割线。该第一半导体装置电性连接于该引脚中之一。一封胶体形成该第一半导体装置及该引脚上，其中该第一芯片承座及该引脚的下表面由该封胶体裸露出。较佳地，该第一半导体装置通过至少一条大尺寸(heavy gauge)铝线电性连接于该引脚中之一。
该半导体封装构造另包含一第二半导体装置(诸如一控制半导体装置(control semiconductor device))，其可通过例如银胶稳固地贴附于一第二芯片承座上。该第二半导体装置通过多条金线电性连接于该引脚及该第一半导体装置。
本发明的该半导体封装构造可固定于一印刷电路板上。该第一及第二芯片承座直接焊接于该印刷电路板的一匹配热垫(matching thermalland)上，用以提供低热阻抗的路径，其可移除固定于该第一及第二芯片承座的该第一及第二半导体装置所产生的热。具有厚度10-20μ的芯片承座及大尺寸(heavy gauge)铝线提供低阻抗(electrical on-resistance)，可帮助从该封装构造散热。
为达上述目的，本发明还提供一种半导体封装构造的制造方法。该半导体封装构造的制造方法包含下列步骤：(A)提供一导线架具有一厚度介于10至20μm之间，其中该导线架包含多个具有阵列布置的单元，每一单元具有一第一及第二芯片承座、一输出条及多个引脚配置于该第一及第二芯片承座周围附近，且每一单元具有一半蚀刻(half-etched)凹处，其形成位置相对于一预定切割线(dicing line)；(B)通过锡膏将一第一半导体装置贴附于该导线架的每一单元的该第一芯片承座上；(C)将一第一半导体装置电性连接于该引脚；(D)形成一已包封产品(molded product)，其中通过对该导线架包封该第一半导体装置及该第二半导体装置，以形成多个封胶体，每一封胶体包封该第一半导体装置及该第二半导体装置，进而形成该已包封产品(molded product)；以及(E)沿该引脚的该半蚀刻凹处冲切(punching)该已包封产品成为多个独立的半导体封装构造。
附图说明
图1为现有技术的无引脚封装构造的仰视示意图；
图2为图1的该无引脚封装构造的剖面示意图；
图3为根据本发明的一实施例的部分导线架的俯视示意图；
图4为根据本发明的一实施例的无引脚半导体封装构造的俯视示意图，其封胶体被移除；
图5为图4的该无引脚半导体封装构造的剖面示意图，其显示于实施冲切单一化步骤之前。
图中符号说明
10   无外引脚封装构造        11a   引脚
11b  芯片承座                11c   支撑肋条
12   芯片                    13    封胶体
100  导线架                  110   引脚
110a 凹处                    112   电力输出条
120  芯片承座                120a  凹处
122  芯片承座                122a  凹处
130  控制半导体装置          132   电力半导体装置
140  金线                    142   铝线
150  封胶体                  200   半导体封装构造
具体实施方式
为了让本发明的上述和其它目的、特征、和优点能更明显，下文特举本发明的实施例，并配合所附图标，作详细说明如下。
参考图3，其显示根据本发明的一实施例的导线架的俯视图。该导线架100包含由多个筑堤(dambar)所分隔的多个单元。虽然只有一个导线架100的单元显示于图3，但是使用于本发明的导线架可包含任意数目的单元，其适用于被使用的制造设备，诸如封胶包封(mold)设备。该筑堤通常于该导线架100上形成一正交格子状。该导线架100一般由以铜为基材的合金所制、由铜所制、或由包含铜的合金所制。该导线架100具有介于10μm与20μm之间的厚度，并通过蚀刻该导线架100的每一单元而成形，其中该单元具有多个引脚110及一电力输出条(power output Bar)112配置于两芯片承座120、122周围附近。另外，一具有半蚀刻的操作实施于该导线架的制程中。该导线架的半蚀刻区域呈现于图3中，用以协助了解。请注意，每一引脚110半蚀刻其底部面积，以形成一凹处(indentation)110a，其位置相对于一预定切割线(dicing line)(图中未示)。熟悉此技术者可知，此处的“半蚀刻”不以仅表示通过蚀刻精确地移除该导线架一半的厚度为限，尚可表示通过部份蚀刻只移除该导线架的部分厚度。适用于本发明的导线架可获得三种引脚层(lead finish)：先镀有具闪亮金的镍钯层(亦即预镀导线架)、锡层及最后镀有锡铅层。
参考图4，其显示根据本发明的一实施例的半导体封装构造200。该半导体封装构造200主要包含一控制半导体装置(controlsemiconductor device)130，其可通过例如银胶(solder paste)稳固地贴附于该芯片承座120的一上表面上。该半导体封装构造200另包含一电力半导体装置(power semiconductor device)132，其可通过例如锡膏稳固地贴附于该芯片承座122的一上表面上。该锡膏提供良好的电传导性及热传导性。合适的锡膏为一种具传导性的锡合金，其包含锡、铅、铋、铟、银及金。于一较佳实施例中，该锡膏是铅/锡为基础的锡膏，其具有介于80％至97％的锡与通常可平衡的铅。该电力半导体装置132可为一被使用于电力放大器(power amplifier)的控制芯片，且该控制半导体装置130可为一控制芯片，其包含一控制电路需要执行该电力半导体装置132的控制。该控制半导体装置130通过多条金线140电性连接于该引脚110及该电力半导体装置132。该电力半导体装置132通过多条大尺寸(heavy gauge)铝线142(较佳为5-10μm)电性连接于该电力输出条112。
参考图5，一封胶体150形成该引脚110、该电力输出条112、该芯片承座120、122、以及该半导体装置130、132上。该引脚110、该电力输出条112及该芯片承座120、122的下表面由该封胶体150的底部裸露出。它们的厚度较佳为介于10至20μm之间，藉此增加该封胶体150与该芯片承座120、122及该引脚110之间的接口区域，进而延长水气扩散进入该封装构造200的路径及时间。再者，该芯片承座120、122被半蚀刻而形成凹处120a、122a，藉此加强将该芯片承座120、122模锁于该封胶体150中。
该封装构造200可固定于一基板上，诸如一印刷电路板，或其它无外引脚装置。该芯片承座120、122直接焊接于该印刷电路板的一匹配热垫(matching thermal land)上，用以提供低热阻抗的路径，其可移除固定于该芯片承座120、122的该半导体装置130、132所产生的热。于该封装构造200中，传导为主要热传方式，其将该半导体装置130、132所产生的热经由裸露于该封装构造200下表面的该芯片承座120、122移除至该封装构造200之外，藉此更加强该封装构造200的热性能。具有厚度10-20μm的芯片承座及大尺寸(heavy gauge)铝线提供低阻抗(electrical on-resistance)，可帮助从该封装构造200散热。因此，本发明的该无引脚封装构造200克服已存在电力封装构造的限制，并符合应用于汽车、工业及商业的高电力的散热(dissipation)需求。
虽然本发明被详细讨论关于具有两半导体装置的该无引脚封装构造200，但是只具有一半导体装置的无引脚封装构造仍被考虑于本发明的精神及范围内。
本发明另提供一制程方法用以制造前述无引脚封装构造。首先，于该导线架100的每一单元中，一控制半导体装置130通过银胶贴附于该芯片承座120，且一电力半导体装置132通过锡膏贴附于该芯片承座122。较佳地，聚亚醯胺(polyimide)胶带(图中未示)贴附于该导线架100的下表面，用以防止在模造制程中出现封胶溢胶的问题(mold flashproblem)。然后，一般打线接合制程执行将金线连结于该控制半导体装置130与该引脚110及该电力半导体装置132之间(如图4所示)。另外，连接于该电力半导体装置132与该电力输出条112的铝线(如图4所示)通过一超音波铝楔型打线机(ultrasonic aluminum wedge bonder)而执行。
再参考图5，通过对该导线架100包封该控制半导体装置130及该电力半导体装置132，以形成多个封胶体(图5只显示一个封胶体)，每一封胶体包封该多个控制半导体装置130中之一及该多个电力半导体装置132中之一，进而形成一已包封产品(molded product)。
之后，单一化步骤被实施，用以切割上述已包封产品成为多个独立的无引脚半导体封装构造。因为该导线架100具有一厚度介于10μm至20μm之间，所以单一化步骤通过切割该导线架100的半蚀刻区域，诸如该引脚110的该凹处110a而实施，以加强其封装完整性。当使用一单独包封制程而形成该已包封产品时，该单一化步骤通过冲切(punching)的操作而实施。可替代地，当使用一重复包封(overmolding)制程而形成该已包封产品时，该单一化步骤利用由该已包封产品的下表面(亦即裸露出该芯片承座120、122及该引脚110的表面)至其上表面锯开(sawing)而实施。
虽然本发明已以前述实施例揭示，然其并非用以限定本发明，任何熟悉此技术者，在不脱离本发明的精神和范围内，当可作各种的更动与修改。因此本发明的保护范围当视权利要求书所界定者为准。

Claims (18)

1.一种半导体封装构造，其特征在于，包含：
一第一芯片承座及多个引脚配置于该第一芯片承座周围，其中该第一芯片承座及该引脚具有一厚度介于10至20μm之间，各该引脚具有一半蚀刻凹处，而该半蚀刻凹处的位置相对一预定切割线；
一第一半导体装置，通过锡膏贴附于该第一芯片承座的一上表面上，并电性连接于该引脚中之一；以及
一封胶体，形成于该第一半导体装置及该引脚上，其中该第一芯片承座及该引脚的下表面由该封胶体裸露出。
2.如权利要求1所述的半导体封装构造，其中，该第一半导体装置为一电力半导体装置。
3.如权利要求1所述的半导体封装构造，其中，另包含一输出条，其中该第一半导体装置通过至少一条大尺寸铝线电性连接于该输出条。
4.如权利要求1所述的半导体封装构造，其中，另包含：
一第二芯片承座，配置于该引脚之间，并具有一厚度介于10至20μm之间；以及
一第二半导体装置，配置于该第二芯片承座上，并通过多条金线电性连接于该引脚及该第一半导体装置。
5.如权利要求4所述的半导体封装构造，其中，该第二半导体装置为一控制半导体装置。
6.如权利要求4所述的半导体封装构造，其中，该第二半导体装置为一控制半导体装置，并通过银胶稳固贴附于该第二芯片承座上。
7.如权利要求4所述的半导体封装构造，其中，该第一芯片承座及该第二芯片承座被半蚀刻而形成凹处，藉此加强将该第一芯片承座及该第二芯片承座模锁于该封胶体中。
8.一种半导体封装构造，其特征在于，包含：
一第一及第二芯片承座、一输出条及多个引脚配置于该第一及第二芯片承座周围；
一第一半导体装置，通过锡膏贴附于该第一芯片承座上，并通过至少一条大尺寸铝线电性连接于该输出条；
一第二半导体装置，配置于该第二芯片承座上，并电性连接于该引脚及该第一半导体装置；以及
一封胶体，形成于该第一半导体装置、该第二半导体装置、该输出条及该引脚上，其中该输出条及该引脚的下表面由该封胶体裸露出，且该第一芯片承座及该第二芯片承座被半蚀刻而形成凹处，藉此加强将该第一芯片承座及该第二芯片承座模锁于该封胶体中。
9.如权利要求8所述的半导体封装构造，其中，
该第一半导体装置为一电力半导体装置；以及
该第二半导体装置为一控制半导体装置，并通过银胶贴附于该第二芯片承座上。
10.一种半导体封装构造，其特征在于，包含：
一第一及第二芯片承座及多个引脚配置于该第一及第二芯片承座周围，其中该第一及第二芯片承座及该引脚具有一厚度介于10至20μm之间；
一第一半导体装置，通过锡膏贴附于该第一芯片承座上；
一第二半导体装置，配置于该第二芯片承座上，并电性连接于该引脚及该第一半导体装置；以及
一封胶体，形成于该第一半导体装置、该第二半导体装置及该引脚上，其中该引脚的下表面由该封胶体裸露出，且该第一芯片承座及该第二芯片承座被半蚀刻而形成凹处，藉此加强将该第一芯片承座及该第二芯片承座模锁于该封胶体中。
11.如权利要求10所述的半导体封装构造，其中，
该第一半导体装置为一电力半导体装置；以及
该第二半导体装置为一控制半导体装置，并通过银胶贴附于该第二芯片承座上。
12.一种半导体封装构造的制造方法，其特征在于，包含下列步骤：
提供一导线架具有一厚度介于10至20μm之间，其中该导线架包含多个具有阵列布置的单元，每一单元具有一第一及第二芯片承座、一输出条及多个引脚配置于该第一及第二芯片承座周围，且每一单元具有一半蚀刻凹处，其形成位置相对于一预定切割线；
通过锡膏将一第一半导体装置贴附于该导线架的每一单元的该第一芯片承座上；
通过银胶将一第二半导体装置贴附于该导线架的每一单元的该第二芯片承座上；
将一第一半导体装置电性连接于该输出条；
将一第二半导体装置电性连接于该引脚及该第一半导体装置；
形成一已包封产品，其中通过对该导线架包封该第一半导体装置及该第二半导体装置，以形成多个封胶体，每一封胶体包封该第一半导体装置及该第二半导体装置，进而形成该已包封产品；以及
沿该引脚的该半蚀刻凹处切割该已包封产品成为多个独立的半导体封装构造。
13.如权利要求12所述的半导体封装构造的制造方法，其中，该
第一半导体装置通过至少一条大尺寸铝线电性连接于该输出条。
14.如权利要求12所述的半导体封装构造的制造方法，其中，该第二半导体装置通过多条金线电性连接于该引脚及该第一半导体装置。
15.如权利要求12所述的半导体封装构造的制造方法，其中，该第一半导体装置为一电力半导体装置且该第二半导体装置为一控制半导体装置。
16.如权利要求12所述的半导体封装构造的制造方法，其中，沿该引脚的该半蚀刻凹处切割该已包封产品成为多个独立的半导体封装构造的步骤中，包含下列步骤：
锯开该已包封产品成为多个独立的半导体封装构造。
17.如权利要求12所述的半导体封装构造的制造方法，其中，该已包封产品具有相对的一上表面及一下表面，该第一及第二芯片承座及该引脚的一表面由该已包封产品的该下表面裸露出；且沿该引脚的该半蚀刻凹处切割该已包封产品成为多个独立的半导体封装构造的步骤中，包含下列步骤：
由该已包封产品的该下表面至该已包封产品的该上表面锯开该已包封产品成为多个独立的半导体封装构造。
18.如权利要求12所述的半导体封装构造的制造方法，其中，沿该引脚的该半蚀刻凹处切割该已包封产品成为多个独立的半导体封装构造的步骤中，包含下列步骤：
冲切该已包封产品成为多个独立的半导体封装构造。
CNB2004100118635A 2004-09-22 2004-09-22 无外引脚半导体封装构造及其制造方法 Active CN100438021C (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB2004100118635A CN100438021C (zh) 2004-09-22 2004-09-22 无外引脚半导体封装构造及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2004100118635A CN100438021C (zh) 2004-09-22 2004-09-22 无外引脚半导体封装构造及其制造方法

Publications (2)

Publication Number Publication Date
CN1753179A CN1753179A (zh) 2006-03-29
CN100438021C true CN100438021C (zh) 2008-11-26

Family

ID=36679943

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004100118635A Active CN100438021C (zh) 2004-09-22 2004-09-22 无外引脚半导体封装构造及其制造方法

Country Status (1)

Country Link
CN (1) CN100438021C (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2444385Y (zh) * 2000-07-27 2001-08-22 超众科技股份有限公司 散热板导热装置
CN1355566A (zh) * 2000-11-27 2002-06-26 矽品精密工业股份有限公司 加强散热型四方扁平无接脚封装
US6528893B2 (en) * 2000-01-28 2003-03-04 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
CN2572564Y (zh) * 2002-09-29 2003-09-10 威盛电子股份有限公司 晶粒级封装结构
CN1457513A (zh) * 2001-03-06 2003-11-19 Asat控股有限公司 增强型无铅芯片座架

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6528893B2 (en) * 2000-01-28 2003-03-04 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
CN2444385Y (zh) * 2000-07-27 2001-08-22 超众科技股份有限公司 散热板导热装置
CN1355566A (zh) * 2000-11-27 2002-06-26 矽品精密工业股份有限公司 加强散热型四方扁平无接脚封装
CN1457513A (zh) * 2001-03-06 2003-11-19 Asat控股有限公司 增强型无铅芯片座架
CN2572564Y (zh) * 2002-09-29 2003-09-10 威盛电子股份有限公司 晶粒级封装结构

Also Published As

Publication number Publication date
CN1753179A (zh) 2006-03-29

Similar Documents

Publication Publication Date Title
US7053469B2 (en) Leadless semiconductor package and manufacturing method thereof
US9741641B2 (en) Method for manufacturing semiconductor device, and semiconductor device
US7879653B2 (en) Leadless semiconductor package with electroplated layer embedded in encapsulant and the method for manufacturing the same
US6400004B1 (en) Leadless semiconductor package
US8823152B1 (en) Semiconductor device with increased I/O leadframe
US7169651B2 (en) Process and lead frame for making leadless semiconductor packages
US5953589A (en) Ball grid array semiconductor package with solder balls fused on printed circuit board and method for fabricating the same
US7927918B2 (en) Packaged products, including stacked package modules, and methods of forming same
US8487424B2 (en) Routable array metal integrated circuit package fabricated using partial etching process
CN110010489B (zh) 用于制作带有侧壁凹陷的半导体器件的方法及相关器件
US20020197826A1 (en) Singulation method used in leadless packaging process
US7847392B1 (en) Semiconductor device including leadframe with increased I/O
CN101312177A (zh) 用于半导体器件的引线框
US20110165729A1 (en) Method of packaging semiconductor device
US7851902B2 (en) Resin-sealed semiconductor device, manufacturing method thereof, base material for the semiconductor device, and layered and resin-sealed semiconductor device
EP3758060A1 (en) Multi-row qfn semiconductor package
US20220157700A1 (en) Two sided bondable lead frame
KR100621555B1 (ko) 리드 프레임, 이를 이용한 반도체 칩 패키지 및 그의 제조방법
CN108198790B (zh) 具有引脚侧壁爬锡功能的堆叠封装结构及其制造工艺
US6524886B2 (en) Method of making leadless semiconductor package
CN108198804B (zh) 具有引脚侧壁爬锡功能的堆叠封装结构及其制造工艺
US6610924B1 (en) Semiconductor package
US20080185698A1 (en) Semiconductor package structure and carrier structure
CN100438021C (zh) 无外引脚半导体封装构造及其制造方法
JP2003197663A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant