CN100438009C - Mounting arrangement for semiconductor parts and method for manufacturing mounting substrate - Google Patents
Mounting arrangement for semiconductor parts and method for manufacturing mounting substrate Download PDFInfo
- Publication number
- CN100438009C CN100438009C CNB2006101155664A CN200610115566A CN100438009C CN 100438009 C CN100438009 C CN 100438009C CN B2006101155664 A CNB2006101155664 A CN B2006101155664A CN 200610115566 A CN200610115566 A CN 200610115566A CN 100438009 C CN100438009 C CN 100438009C
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- junction surface
- semiconductor device
- photoresist
- base plate
- upper layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81385—Shape, e.g. interlocking features
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
The invention provides the mounting structure of a highly productive semiconductor component where peeling between a bump and a land is prevented, and also to provide a method for manufacturing a mounted substrate to be used therefore. In the mounting structure of the semiconductor component, edge faces (4a, 4b) of a land (4) wherein a bump (8) is positioned are provided with a locking part (5) comprising: a rising surface (5a) almost vertical from an insulating substrate (2); a swelling part (5b) projecting almost at right angles from the upper part of the rising surface (5a); and a recess part (5c) surrounded by the rising surface (5a), the swelling part (5b), and the insulating substrate (2). Since a bump (8) is made to dig into the recess (5c) of the locking part (5), the connection of the bump (8) to the land (4) is made strong, and peeling is prevented between the bump (8) and the land (4).
Description
Technical field
The present invention relates to be applicable to that the installation constitution of the semiconductor device in various e-machines or the electronic circuit cell etc. reaches the manufacture method of wherein used installation base plate.
Background technology
When the figure to the installation constitution of in the past semiconductor device describes, then Figure 25 be semiconductor device in the past installation constitution want portion's amplification profile, Figure 26 relates to the installation constitution of semiconductor device in the past, it is the vertical view of wanting portion of installation base plate of the formation at expression junction surface, in addition, when the formation of the installation constitution of in the past semiconductor device being described based on Figure 25, Figure 26, then installation base plate 51 by insulated substrate 52, be located at Wiring pattern 53 on this insulated substrate 52, the junction surface 54 of being located at the end of this Wiring pattern 53 forms.In addition, Wiring pattern 53 and junction surface 54 form by the etching metal film, and junction surface 54 forms by the 54a of island portion of a plurality of distributions, and the end face of the 54a of this island portion becomes from insulated substrate 52 towards the vertical face in ground, top.
But, the installation constitution of semiconductor device in the past is owing to be that end face at the 54a of island portion at junction surface 54 forms under the state of vertical plane, pad 57 is attached on the junction surface 54, therefore 54 at pad 57 and junction surface adhere to very weak, peel off easily, and because of the expansion or the contraction of bonding agent 58, the adhering to and can be stripped from of 54 at pad 57 and junction surface.
In addition, the manufacture method of installation base plate in the past is owing to be to be located at metal film on the insulated substrate 52 by etching, form Wiring pattern 53 and junction surface 54, therefore the end face of the 54a of island portion at junction surface 54 forms vertical plane, thus, adhering to of 54 at pad 57 and junction surface is very weak, peels off easily, and because of the expansion or the contraction of bonding agent 58, the adhering to and can be stripped from of 54 at pad 57 and junction surface.
The installation constitution of semiconductor device in the past is owing to be that end face at the 54a of island portion at junction surface 54 forms under the state of vertical plane, pad 57 is attached on the junction surface 54, therefore 54 at pad 57 and junction surface adhere to very weak, peel off easily, and because of the expansion or the contraction of bonding agent 58, the adhering to and can be stripped from of 54 at pad 57 and junction surface.
In addition, the manufacture method of installation base plate in the past is owing to be to be located at metal film on the insulated substrate 52 by etching, form Wiring pattern 53 and junction surface 54, therefore the end face of the 54a of island portion at junction surface 54 forms vertical plane, thus, adhering to of 54 at pad 57 and junction surface is very weak, peels off easily, and because of the expansion or the contraction of bonding agent 58, the adhering to and can be stripped from of 54 at pad 57 and junction surface.
Summary of the invention
Given this present invention plants the realistic situation of conventional art and finishes, and its purpose is, provide do not have peeling off between pad and junction surface, the manufacture method of the installation constitution of semiconductor device that productivity is good and wherein used installation base plate.
In order to reach described purpose, as first solution route of the present invention, adopted following formation, promptly, possess: installation base plate with the insulated substrate that is provided with Wiring pattern and junction surface, at the semiconductor device that is installed on by pad on the described junction surface on the described installation base plate, on the end face at the residing described junction surface of described pad, be provided with by: with the raised floor of described insulated substrate approximate vertical, the bellying of giving prominence to respect to described raised floor from the top of this raised floor with roughly meeting at right angles, by this bellying, the fastener that the recess that described raised floor and described insulated substrate surround constitutes is nipped in the described recess of described fastener described pad.
In addition, as second solution route, adopted following formation, that is, described junction surface has draws back a pair of described end face that the compartment of terrain is faced mutually mutually, described pad is nipped be located in the described fastener on this a pair of described end face.
In addition, as the 3rd solution route, adopted following formation, promptly, has the bonding agent that is located between described semiconductor device and the described insulated substrate, described junction surface has a pair of described end face that draws back the compartment of terrain mutually and face mutually, be located between this a pair of end face and the slot part that described junction surface has been eliminated, at least one distolateral opening portion of being located at this slot part, is located in described bonding agent in the described slot part and passes described opening portion and flow out.
In addition, as the 4th solution route, adopted following formation, that is, described pad is formed by golden material.
In addition, as the 5th solution route, adopted following formation, promptly, described bellying as the upper layer at described junction surface is formed by the high metal of corrosion resistance, and the lower layer at described junction surface of being located at the lower side of described bellying is formed by the high metal of conductance.
In addition, as the 6th solution route, adopted following formation, that is, described upper layer is formed by nickel-phosphorus, and described lower layer is formed by copper.
In addition, as the 7th solution route, adopted following manufacture method, that is, possessed the installation constitution of any described semiconductor device in the technical scheme 1 to 4, described installation base plate is utilized: the operation that forms basalis on described insulated substrate; On this basalis, form the operation of the photoresist that can develop; With described photoresist developing, be used on the position that becomes described Wiring pattern and described junction surface forming that photoresist is removed portion and the operation that forms required pattern form; To be attached to the state on the described basalis, remove the operation that forms metallic intermediate layer in the portion at described photoresist; Being attached on the described intermediate layer, the state that stretches out on described photoresist becomes the operation of the metallic upper layer of described bellying; The operation that described photoresist is removed; Except residing position, described intermediate layer, the operation that described basalis is removed is made, form described Wiring pattern and described junction surface, and on the described end face at described junction surface, formed the described fastener that constitutes by described raised floor, described bellying, described recess.
In addition, as the 8th solution route, adopted following manufacture method, that is, possessed the installation constitution of any described semiconductor device in the technical scheme 1 to 4, described installation base plate is utilized: the operation that forms basalis on described insulated substrate; On described basalis, form the operation in metallic intermediate layer; On described intermediate layer, form the operation of metallic upper layer; On described upper layer, form the operation of the photoresist that can develop; With described photoresist developing, and will become the operation that the photoresist at the position beyond described Wiring pattern and the described junction surface is removed; Except the residing position of described photoresist, the operation of utilizing etching to remove described upper layer; The operation that near the described intermediate layer at the position the bottom of position that described upper layer is removed and exposes and the end that is positioned at described upper layer utilizes Wet-type etching to remove; The operation that described photoresist on the described upper layer is removed; Except residing position, described intermediate layer, the operation that described basalis utilizes etching to remove is made, form described Wiring pattern and described junction surface, and on the described end face at described junction surface, formed the described fastener that constitutes by described raised floor, described bellying, described recess.
In addition, as the 9th solution route, adopted following manufacture method, that is, described upper layer is formed by the high metal of corrosion resistance, and described intermediate layer is formed by the high metal of conductance.
In addition, as the tenth solution route, adopted following manufacture method, that is, described upper layer is formed by nickel-phosphorus, and described intermediate layer is formed by copper.
In the installation constitution of semiconductor device of the present invention, because end face at the residing junction surface of pad, be provided with by the fastener that constitutes with the raised floor of insulated substrate approximate vertical, the bellying of giving prominence to respect to raised floor from the top of this raised floor, the recess that surrounded by this bellying, raised floor and insulated substrate with roughly meeting at right angles, pad is nipped in the recess of fastener, therefore combining because of the pad fastener of nipping is become firmly of pad and junction surface can obtain not have the product of peeling off between pad and junction surface.
In addition, because welding disk has and draws back a pair of end face that the compartment of terrain is faced mutually mutually, pad is nipped be located in the fastener on this a pair of end face, so combining between pad and junction surface become more firm, can obtain not have the product of peeling off between pad and junction surface.
In addition, owing to have the bonding agent that is located between semiconductor device and the insulated substrate, therefore can make the installation of semiconductor device on insulated substrate firm, even and bonding agent expands or contraction, do not have peeling off between pad and junction surface yet, in addition, owing to the junction surface has a pair of end face that draws back the compartment of terrain mutually and face mutually, is located at the slot part that has eliminated the junction surface between this a pair of end face, at least one distolateral opening portion of being located at this slot part, can obtain to be located in therefore that bonding agent in the slot part is easy to pass the opening portion and the product that flows out.
In addition, because pad forms by golden material, so the conducting between pad and junction surface becomes more good, and can obtain the nip good product of pad in fastener.
In addition, because the bellying as the upper layer at junction surface is formed by the high metal of corrosion resistance, and the lower layer at junction surface of being located at the lower side of bellying is formed by the high metal of conductance, therefore the good lower layer of conductivity just can utilize the bellying as upper layer to prevent corrosion, can obtain the good product of long-time conductivity.
In addition, because upper layer forms by nickel-phosphorus, and lower layer forms by copper, therefore can obtain lower layer conductivity well and the good product of upper layer corrosion resistance.
In addition, be utilized owing to installation base plate: the operation that on insulated substrate, forms basalis; On this basalis, form the operation of the photoresist that can develop; With photoresist developing, be used on the position that becomes Wiring pattern and junction surface forming that photoresist is removed portion and the operation that forms required pattern form; To be attached to the state on the basalis, in removing portion, photoresist forms the operation in metallic intermediate layer; Being attached on the intermediate layer, the state that stretches out on photoresist becomes the operation of the metallic upper layer of bellying; The operation that photoresist is removed; Except residing position, intermediate layer, the operation that basalis is removed is made, form Wiring pattern and junction surface, therefore productivity is good, and can easily be formed on the junction surface that has the fastener that constitutes by raised floor, bellying, recess on the end face, can obtain not have the product of peeling off between pad and junction surface.
In addition, be utilized owing to installation base plate: the operation that on insulated substrate, forms basalis; On basalis, form the operation in metallic intermediate layer; On the intermediate layer, form the operation of metallic upper layer; On upper layer, form the operation of the photoresist that can develop; With photoresist developing, and will become the operation that the photoresist at the position beyond Wiring pattern and the junction surface is removed; Except the residing position of photoresist, the operation of utilizing etching to remove upper layer; The operation that near the intermediate layer at the position the bottom of position that upper layer is removed and exposes and the end that is positioned at upper layer utilizes Wet-type etching to remove; The operation that photoresist on the upper layer is removed; Except residing position, intermediate layer, the operation that basalis utilizes etching to remove is made, Wiring pattern and junction surface have been formed, therefore productivity is good, and can easily be formed on the junction surface that has the fastener that constitutes by raised floor, bellying, recess on the end face, can obtain not have the product of peeling off between pad and junction surface.
In addition, because upper layer is formed by the high metal of corrosion resistance, and the intermediate layer is formed by the high metal of conductance, so the good lower layer of conductivity just can utilize the bellying as upper layer to prevent corrosion, can obtain the good product of long-time conductivity.
In addition, because upper layer forms by nickel-phosphorus, and the intermediate layer forms by copper, therefore can obtain intermediate layer conductivity well and the good product of upper layer corrosion resistance.
Description of drawings
Fig. 1 be semiconductor device of the present invention installation constitution embodiment 1 want portion's amplification profile.
Fig. 2 relates to the embodiment 1 of the installation constitution of semiconductor device of the present invention, is the vertical view of wanting portion of installation base plate of the formation at expression junction surface.
Fig. 3 relates to the embodiment 2 of the installation constitution of semiconductor device of the present invention, is the vertical view of wanting portion of installation base plate of the formation at expression junction surface.
Fig. 4 is the profile of the 4-4 line of Fig. 3.
Fig. 5 relates to the embodiment 3 of the installation constitution of semiconductor device of the present invention, is the vertical view of wanting portion of installation base plate of the formation at expression junction surface.
Fig. 6 relates to the embodiment 4 of the installation constitution of semiconductor device of the present invention, is the vertical view of wanting portion of installation base plate of the formation at expression junction surface.
Fig. 7 relates to the embodiment 5 of the installation constitution of semiconductor device of the present invention, is the vertical view of wanting portion of installation base plate of the formation at expression junction surface.
Fig. 8 be semiconductor device of the present invention installation constitution embodiment 6 want portion's amplification profile.
Fig. 9 relates to the embodiment 1 of the manufacture method of installation base plate of the present invention, is the key diagram that expression forms the operation of basalis.
Figure 10 relates to the embodiment 1 of the manufacture method of installation base plate of the present invention, is the key diagram that expression forms the operation of photoresist.
Figure 11 relates to the embodiment 1 of the manufacture method of installation base plate of the present invention, is that expression formation photoresist is removed the key diagram of the operation of portion.
Figure 12 relates to the embodiment 1 of the manufacture method of installation base plate of the present invention, is the key diagram that expression forms the operation in intermediate layer.
Figure 13 relates to the embodiment 1 of the manufacture method of installation base plate of the present invention, is the key diagram that expression forms the operation of upper layer.
Figure 14 relates to the embodiment 1 of the manufacture method of installation base plate of the present invention, is the key diagram of expression operation that photoresist is removed.
Figure 15 relates to the embodiment 1 of the manufacture method of installation base plate of the present invention, is the key diagram of expression operation that basalis is removed.
Figure 16 relates to the embodiment 2 of the manufacture method of installation base plate of the present invention, is the key diagram that expression forms the operation of basalis.
Figure 17 relates to the embodiment 2 of the manufacture method of installation base plate of the present invention, is the key diagram that expression forms the operation in intermediate layer.
Figure 18 relates to the embodiment 2 of the manufacture method of installation base plate of the present invention, is the key diagram that expression forms the operation of upper layer.
Figure 19 relates to the embodiment 2 of the manufacture method of installation base plate of the present invention, is the key diagram that expression forms the operation of photoresist.
Figure 20 relates to the embodiment 2 of the manufacture method of installation base plate of the present invention, is that expression is removed the key diagram of operation with first of photoresist+remove.
Figure 21 relates to the embodiment 2 of the manufacture method of installation base plate of the present invention, is the key diagram of expression operation that upper layer is removed.
Figure 22 relates to the embodiment 2 of the manufacture method of installation base plate of the present invention, is the key diagram of expression operation that the intermediate layer is removed.
Figure 23 relates to the embodiment 2 of the manufacture method of installation base plate of the present invention, is that expression second is removed the key diagram of operation with what photoresist was removed.
Figure 24 relates to the embodiment 2 of the manufacture method of installation base plate of the present invention, is the key diagram of expression operation that basalis is removed.
Figure 25 be semiconductor device in the past installation constitution want portion's amplification profile.
Figure 26 relates to the installation constitution of semiconductor device in the past, is the vertical view of wanting portion of installation base plate of the formation at expression junction surface.
Wherein, 1-installation base plate, 2-insulated substrate.
Embodiment
When the reference accompanying drawing describes the working of an invention mode, then Fig. 1 be semiconductor device of the present invention installation constitution embodiment 1 want portion's amplification profile, Fig. 2 relates to the embodiment 1 of the installation constitution of semiconductor device of the present invention, it is the vertical view of wanting portion of installation base plate of the formation at expression junction surface, Fig. 3 relates to the embodiment 2 of the installation constitution of semiconductor device of the present invention, it is the vertical view of wanting portion of installation base plate of the formation at expression junction surface, Fig. 4 is the profile of the 4-4 line of Fig. 3, Fig. 5 relates to the embodiment 3 of the installation constitution of semiconductor device of the present invention, it is the vertical view of wanting portion of installation base plate of the formation at expression junction surface, Fig. 6 relates to the embodiment 4 of the installation constitution of semiconductor device of the present invention, it is the vertical view of wanting portion of installation base plate of the formation at expression junction surface, Fig. 7 relates to the embodiment 5 of the installation constitution of semiconductor device of the present invention, be the vertical view of wanting portion of installation base plate of the formation at expression junction surface, Fig. 8 be semiconductor device of the present invention installation constitution embodiment 6 want portion's amplification profile.
In addition, Fig. 9 relates to the embodiment 1 of the manufacture method of installation base plate of the present invention, it is the key diagram that expression forms the operation of basalis, Figure 10 relates to the embodiment 1 of the manufacture method of installation base plate of the present invention, it is the key diagram that expression forms the operation of photoresist, Figure 11 relates to the embodiment 1 of the manufacture method of installation base plate of the present invention, be that expression formation photoresist is removed the key diagram of the operation of portion, Figure 12 relates to the embodiment 1 of the manufacture method of installation base plate of the present invention, it is the key diagram that expression forms the operation in intermediate layer, Figure 13 relates to the embodiment 1 of the manufacture method of installation base plate of the present invention, it is the key diagram that expression forms the operation of upper layer, Figure 14 relates to the embodiment 1 of the manufacture method of installation base plate of the present invention, it is the key diagram of expression operation that photoresist is removed, Figure 15 relates to the embodiment 1 of the manufacture method of installation base plate of the present invention, is the key diagram of expression operation that basalis is removed.
In addition, Figure 16 relates to the embodiment 2 of the manufacture method of installation base plate of the present invention, it is the key diagram that expression forms the operation of basalis, Figure 17 relates to the embodiment 2 of the manufacture method of installation base plate of the present invention, it is the key diagram that expression forms the operation in intermediate layer, Figure 18 relates to the embodiment 2 of the manufacture method of installation base plate of the present invention, it is the key diagram that expression forms the operation of upper layer, Figure 19 relates to the embodiment 2 of the manufacture method of installation base plate of the present invention, it is the key diagram that expression forms the operation of photoresist, Figure 20 relates to the embodiment 2 of the manufacture method of installation base plate of the present invention, be that expression first is removed the key diagram of operation with what photoresist was removed, Figure 21 relates to the embodiment 2 of the manufacture method of installation base plate of the present invention, it is the key diagram of expression operation that upper layer is removed, Figure 22 relates to the embodiment 2 of the manufacture method of installation base plate of the present invention, it is the key diagram of expression operation that the intermediate layer is removed, Figure 23 relates to the embodiment 2 of the manufacture method of installation base plate of the present invention, be that expression second is removed the key diagram of operation with what photoresist was removed, Figure 24 relates to the embodiment 2 of the manufacture method of installation base plate of the present invention, is the key diagram of expression operation that basalis is removed.
Below, when the formation of the embodiment 1 of the installation constitution of semiconductor device of the present invention being described based on Fig. 1, Fig. 2, then installation base plate 1 by the insulated substrate made from pottery (low-temperature sintering ceramic) etc. 2, be located at Wiring pattern 3 on this insulated substrate 2, the junction surface 4 be located on the end etc. of this Wiring pattern 3 forms.
This junction surface 4 has to be drawn back at least one pair of end face 4a, 4b of facing mutually the compartment of terrain mutually, is located at the fastener 5 on this end face 4a, the 4b, this fastener 5 by: form with raised floor 5a, the bellying 5b that gives prominence to respect to raised floor from the top of this raised floor 5a of the face approximate vertical of insulated substrate 2, the recess 5c that surrounded by this bellying 5b, raised floor 5a and insulated substrate 2 with roughly meeting at right angles.In addition, in junction surface 4, be provided with: be located between a pair of end face 4a, the 4b and be removed junction surface 4 and the opening portion 4d that opened as at least one end of slot part 4c, this slot part 4c of the portion that eliminates at junction surface 4.
The semiconductor device 6 that is made of semiconductor chip etc. is provided with a plurality of electrodes 7 below, on this electrode 7, be attached with the pad 8 that constitutes by Jin Cai etc., and be attached to pad 8 on the electrode 7 by thermo-compressed on junction surface 4, semiconductor device 6 is installed on the installation base plate 1.At this moment, pad 8 is located in the fastener 5 on end face 4a, the 4b at junction surface 4 (pad 8 embeds in the recess 5c) and is engaged with junction surface 4 by nipping.
In addition, constitute the installation constitution of semiconductor device of the present invention as follows, promptly, at semiconductor device 6 with between above the insulated substrate 2, be folded with bonding agent 9, the installation of semiconductor device 6 is firmly changed, and the bonding agent 9 that is located among the slot part 4c can not be stranded in the slot part 4c, outside slot part 4c, flow out and pass opening portion 4d.
In addition, Fig. 3, Fig. 4 represent the embodiment 2 of the installation constitution of semiconductor device of the present invention, when this embodiment 2 is described, then junction surface 4 be provided with by: be made into the U font an end, and draw back mutually on a pair of end face 4a, the 4b that faces mutually the compartment of terrain, with the raised floor 5a of the face approximate vertical of insulated substrate 2; The bellying 5b that gives prominence to respect to raised floor from the top of this raised floor 5a with roughly meeting at right angles; By the fastener 5 of the recess 5c formation of this bellying 5b, raised floor 5a and insulated substrate 2 encirclements.Other formation has the formation identical with described embodiment 1, uses identical numbering for same parts, here its explanation is omitted.
In addition, Fig. 5 represents the embodiment 3 of the installation constitution of semiconductor device of the present invention, when this embodiment 3 is described, then junction surface 4 be provided with by: be made into the H font an end, and draw back mutually on a pair of end face 4a, the 4b that faces mutually the compartment of terrain, with the raised floor 5a of the face approximate vertical of insulated substrate 2; The bellying 5b that gives prominence to respect to raised floor from the top of this raised floor 5a with roughly meeting at right angles; By the fastener 5 of the recess 5c formation of this bellying 5b, raised floor 5a and insulated substrate 2 encirclements.Other formation has the formation identical with described embodiment 1, uses identical numbering for same parts, here its explanation is omitted.
In addition, Fig. 6 represents the embodiment 4 of the installation constitution of semiconductor device of the present invention, when this embodiment 4 is described, then in junction surface 4, be provided with by: be formed with the slot part 4c that is made into the T font, and draw back mutually on a pair of end face 4a, the 4b that faces mutually the compartment of terrain, with the raised floor 5a of the face approximate vertical of insulated substrate 2; The bellying 5b that gives prominence to respect to raised floor from the top of this raised floor 5a with roughly meeting at right angles; By the fastener 5 of the recess 5c formation of this bellying 5b, raised floor 5a and insulated substrate 2 encirclements.Other formation has the formation identical with described embodiment 1, uses identical numbering for same parts, here its explanation is omitted.
In addition, Fig. 7 represents the embodiment 5 of the installation constitution of semiconductor device of the present invention, when this embodiment 5 is described, then junction surface 4 be provided with by: be made into cross in the part, and draw back mutually on a pair of end face 4a, the 4b that faces mutually the compartment of terrain, with the raised floor 5a of the face approximate vertical of insulated substrate 2; The bellying 5b that gives prominence to respect to raised floor from the top of this raised floor 5a with roughly meeting at right angles; By the fastener 5 of the recess 5c formation of this bellying 5b, raised floor 5a and insulated substrate 2 encirclements.Other formation has the formation identical with described embodiment 1, uses identical numbering for same parts, here its explanation is omitted.
In addition, Fig. 8 represents the embodiment 6 of the installation constitution of semiconductor device of the present invention, when this embodiment 6 is described, then junction surface 4 by: be formed at the basalis 10 on the insulated substrate 2; Be formed on this basalis 10, by metal lower layers (intermediate layer 11) such as high copper of conductance or silver; Be formed on this lower layer 11, constitute by metal upper layer 12 such as the high nickel of corrosion resistance or nickel-phosphorus (NiP), on basalis 10 and lower layer 11, be provided with the raised floor 5c of fastener 5, and utilize upper layer 12 to form the bellying 5b of fastener 5, among the recess 5c of pad 8 because of the fastener 5 of nipping, and engaged with junction surface 4.Other formation has the formation identical with described embodiment 1, uses identical numbering for same parts, here its explanation is omitted.In addition, on upper layer 12, also can be formed for preventing the gold layer that corrodes.
Below, when the execution mode 1 of the manufacture method of installation base plate of the present invention being described based on Fig. 9～Figure 15, then at first as shown in Figure 9, carried out after the operation of the basalis 10 that the upper strata 10b that forms on the insulated substrate 2 by the 10a of lower floor of titanium and copper constitutes, as shown in figure 10, carry out on this basalis 10, forming the operation of the photoresist 13 that can develop, after this, as shown in figure 11, carry out following operation, that is, photoresist 13 is developed, on the position that becomes Wiring pattern 3 and junction surface 4, form photoresist and remove the 13a of portion and make required pattern form.
Then, as shown in figure 12, to be attached to the state on the basalis 10, after having carried out in photoresist is removed the 13a of portion utilizing printing or plated film to form operation by metal metallic intermediate layers 11 such as high copper of conductance or silver, as shown in figure 13, to be attached on the intermediate layer 11, the state that a part is stretched out on photoresist 13, use the high nickel of corrosion resistance or nickel-phosphorus metals such as (NiP) to utilize the electroless plating film to become the operation of the metallic upper layer 12 of bellying 5b, then, as shown in figure 14, after having carried out removing the operation of photoresist 13, as shown in figure 15, carry out except 12 residing positions, intermediate layer, after basalis 10 utilized the operation that etching removes, the manufacturing of installation base plate 1 promptly finishes, and utilizes the manufacture method of this kind installation base plate 1, just can form Wiring pattern 3 and junction surface 4, and can be at the junction surface 4 end face 4a, on the 4b, form by raised floor 5a, bellying 5b, the fastener 5 that recess 5c constitutes.
Below, when the embodiment 2 of the manufacture method of installation base plate of the present invention being described based on Figure 16～Figure 24, then at first as shown in figure 16, carried out after the operation of the basalis 10 that the upper strata 10b that forms on the insulated substrate 2 by the 10a of lower floor of titanium and copper constitutes, as shown in figure 17, carry out on this basalis 10, utilizing plated film etc. to form operation by metal metallic intermediate layers 11 such as high copper of conductance or silver, after this, as shown in figure 18, carry out following operation, promptly, on intermediate layer 11, utilize plated film etc. to form by the high nickel of corrosion resistance or the operation of nickel-phosphorus metal metallic upper layer 12 such as (Nip), then, as shown in figure 19, carry out on upper layer 12, forming the operation of the photoresist 13 that can develop.
Then, as shown in figure 20, carried out photoresist 13 is developed, to become Wiring pattern 3 and junction surface 4 beyond the photoresist 13 at position remove first remove operation after, as shown in figure 21, carry out except photoresist 13 residing positions, the operation of utilizing etching to remove upper layer 12, after this, as shown in figure 22, near the intermediate layer 11 at the position the bottom of position of carrying out upper layer 12 is removed and exposing and the end that is positioned at upper layer 12 utilizes the optionally etching operation of removing of Wet-type etching, then, as shown in figure 23, carried out with the photoresist 13 of upper layer 12 remove second remove operation after, as shown in figure 24, carry out except 11 residing positions, intermediate layer, after basalis 10 utilized the operation that etching removes, the manufacturing of installation base plate 1 promptly finishes, utilize the manufacture method of this kind installation base plate 1, just can form Wiring pattern 3 and junction surface 4, and can be at the junction surface 4 end face 4a, on the 4b, form by raised floor 5a, bellying 5b, the fastener 5 that recess 5c constitutes.
Claims (9)
1. the installation constitution of a semiconductor device is characterized in that,
Possess: have the installation base plate of the insulated substrate that is provided with Wiring pattern and junction surface, at the semiconductor device that is installed on by pad on the described junction surface on the described installation base plate,
On the end face at the residing described junction surface of described pad, be provided with by the fastener that constitutes with the raised floor of described insulated substrate approximate vertical, the bellying of giving prominence to respect to described raised floor from the top of this raised floor, the recess that surrounded by this bellying and described raised floor and described insulated substrate with roughly meeting at right angles, described pad is nipped in the described recess of described fastener
Described junction surface has draws back 2 described end faces that the compartment of terrain is faced mutually mutually, described pad is nipped be located in the described fastener on these 2 described end faces.
2. the installation constitution of semiconductor device according to claim 1, it is characterized in that, has the bonding agent that is located between described semiconductor device and the described insulated substrate, described junction surface has a pair of described end face that draws back the compartment of terrain mutually and face mutually, be located between this a pair of end face and the slot part that described junction surface has been eliminated, at least one distolateral opening portion of being located at this slot part, is located in described bonding agent in the described slot part and passes described opening portion and flow out.
3. the installation constitution of semiconductor device according to claim 1 is characterized in that, described pad is formed by golden material.
4. the installation constitution of semiconductor device according to claim 1, it is characterized in that, described bellying as the upper layer at described junction surface is formed by the high metal of corrosion resistance, and the lower layer at described junction surface of being located at the lower side of described bellying is formed by the high metal of conductance.
5. the installation constitution of semiconductor device according to claim 4 is characterized in that, described upper layer is formed by nickel-phosphorus, and described lower layer is formed by copper.
6. the manufacture method of used installation base plate in the installation constitution of a semiconductor device is characterized in that,
The installation constitution that possesses any described semiconductor device in the claim 1 to 3,
Described installation base plate is utilized: the operation that forms basalis on described insulated substrate; On this basalis, form the operation of the photoresist that can develop; With described photoresist developing, be used on the position that becomes described Wiring pattern and described junction surface forming that photoresist is removed portion and the operation that forms required pattern form; To be attached to the state on the described basalis, remove the operation that forms metallic intermediate layer in the portion at described photoresist; Being attached on the described intermediate layer, the state that stretches out on described photoresist becomes the operation of the metallic upper layer of described bellying; The operation that described photoresist is removed; Except residing position, described intermediate layer, the operation that described basalis is removed is made, form described Wiring pattern and described junction surface, and on the described end face at described junction surface, formed the described fastener that constitutes by described raised floor, described bellying, described recess.
7. the manufacture method of used installation base plate in the installation constitution of a semiconductor device is characterized in that,
The installation constitution that possesses any described semiconductor device in the claim 1 to 3,
Described installation base plate is utilized: the operation that forms basalis on described insulated substrate; On described basalis, form the operation in metallic intermediate layer; On described intermediate layer, form the operation of metallic upper layer; On described upper layer, form the operation of the photoresist that can develop; With described photoresist developing, and will become the operation that the photoresist at the position beyond described Wiring pattern and the described junction surface is removed; Except the residing position of described photoresist, the operation of utilizing etching to remove described upper layer; The operation that near the described intermediate layer at the position the bottom of position that described upper layer is removed and exposes and the end that is positioned at described upper layer utilizes Wet-type etching to remove; The operation that described photoresist on the described upper layer is removed; Except residing position, described intermediate layer, the operation that described basalis utilizes etching to remove is made, form described Wiring pattern and described junction surface, and on the described end face at described junction surface, formed the described fastener that constitutes by described raised floor, described bellying, described recess.
8. the manufacture method of used installation base plate in the installation constitution of semiconductor device according to claim 6 is characterized in that, described upper layer is formed by the high metal of corrosion resistance, and described intermediate layer is formed by the high metal of conductance.
9. the manufacture method of used installation base plate in the installation constitution of semiconductor device according to claim 8 it is characterized in that described upper layer is formed by nickel-phosphorus, and described intermediate layer is formed by copper.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005259408 | 2005-09-07 | ||
| JP2005259408A JP2007073748A (en) | 2005-09-07 | 2005-09-07 | Mounting structure for semiconductor component and method for manufacturing mounted substrate to be used therefor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1929121A CN1929121A (en) | 2007-03-14 |
| CN100438009C true CN100438009C (en) | 2008-11-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2006101155664A Expired - Fee Related CN100438009C (en) | 2005-09-07 | 2006-08-18 | Mounting arrangement for semiconductor parts and method for manufacturing mounting substrate |
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| CN (1) | CN100438009C (en) |
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|---|---|---|---|---|
| CN109037172B (en) * | 2017-06-12 | 2021-03-19 | 百容电子股份有限公司 | Packaging device of chip, heat dissipation member thereof and manufacturing method of heat dissipation member |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003109987A (en) * | 2001-10-02 | 2003-04-11 | Toshiba Corp | Flip chip mounting board and semiconductor device |
| JP2003209139A (en) * | 2002-01-15 | 2003-07-25 | Seiko Epson Corp | Semiconductor device and its manufacturing method, substrate, circuit board, and electric instrument |
| US20040060174A1 (en) * | 2002-09-17 | 2004-04-01 | Shinko Electric Industries Co. Ltd. | Method for producing wiring substrate |
| CN1536658A (en) * | 2003-03-31 | 2004-10-13 | ��ʽ���������Ƽ� | Semiconductor device and its mfg. method |
-
2005
- 2005-09-07 JP JP2005259408A patent/JP2007073748A/en not_active Withdrawn
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2006
- 2006-08-18 CN CNB2006101155664A patent/CN100438009C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003109987A (en) * | 2001-10-02 | 2003-04-11 | Toshiba Corp | Flip chip mounting board and semiconductor device |
| JP2003209139A (en) * | 2002-01-15 | 2003-07-25 | Seiko Epson Corp | Semiconductor device and its manufacturing method, substrate, circuit board, and electric instrument |
| US20040060174A1 (en) * | 2002-09-17 | 2004-04-01 | Shinko Electric Industries Co. Ltd. | Method for producing wiring substrate |
| CN1536658A (en) * | 2003-03-31 | 2004-10-13 | ��ʽ���������Ƽ� | Semiconductor device and its mfg. method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2007073748A (en) | 2007-03-22 |
| CN1929121A (en) | 2007-03-14 |
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