CN100435554C - Method and circuit for restoring of weakened phase caused by phase reinforcement in image signal processing - Google Patents
Method and circuit for restoring of weakened phase caused by phase reinforcement in image signal processing Download PDFInfo
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- 238000000034 method Methods 0.000 title abstract description 61
- 238000012545 processing Methods 0.000 title description 6
- 230000002787 reinforcement Effects 0.000 title 1
- 238000005070 sampling Methods 0.000 claims abstract description 182
- 230000001360 synchronised effect Effects 0.000 claims abstract description 19
- 230000010363 phase shift Effects 0.000 claims description 26
- 238000013519 translation Methods 0.000 claims description 24
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 230000000630 rising effect Effects 0.000 claims description 9
- 230000007704 transition Effects 0.000 abstract description 4
- 235000021251 pulses Nutrition 0.000 description 135
- 238000009825 accumulation Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 238000006073 displacement reaction Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 5
- 238000010009 beating Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000012423 maintenance Methods 0.000 description 3
- 235000010627 Phaseolus vulgaris Nutrition 0.000 description 1
- 244000046052 Phaseolus vulgaris Species 0.000 description 1
- 208000032369 Primary transmission Diseases 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000008929 regeneration Effects 0.000 description 1
- 238000011069 regeneration method Methods 0.000 description 1
- VEMKTZHHVJILDY-UHFFFAOYSA-N resmethrin Chemical compound CC1(C)C(C=C(C)C)C1C(=O)OCC1=COC(CC=2C=CC=CC=2)=C1 VEMKTZHHVJILDY-UHFFFAOYSA-N 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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Abstract
The present invention relates to a method and a circuit for generating optimized phase transition sampling pulses of image signals A(t) with synchronous signal SYNC pulses. The method comprises generating a sampling pulse, a first sampling edge is synchronous to the pulse back edge of Sync_int, wherein the period of the sampling pulse is cut into M segments of the SYNC pulse; a sampling pulse period number N is accumulated and is from the pulse back edge of the Sync_int to the A(t) number, and the N exceeds a sampling value of the sampling pulse by a certain value; the sampling pulse and the Sync_int pulse are translated via phase again and again from the back edge of the Sync-int to the accumulated period numbers when the pulse sampling value exceeds by a special value region and becomes N-1, and the system obtains of the worst phase of the sampling pulse; a transition value is added to the sampling pulse phase to generate an optimized phase sampling pulse for sampling the A(t).
Description
Technical field
The invention relates to a kind of method that picture signal is handled that is used for, particularly about a kind of method and circuit of weakened phase restoring, when sampling possesses the synchronous images signal of synchronous signal impulse, in order to produce suitable phase deviation sampling pulse.
Background technology
Traditionally, the cathode ray tube (CRT) monitor has been dominated the field of desktop PC monitor.Yet along with portable computer and the general use of handheld-type intelligent type device, the use of plane formula panel and LCD display is also constantly grown up.Recently, the occupation rate on the type computer market is more and more high on the table for the plane formula panel display.It is in light weight, and the characteristic that volume is little generally is subjected to liking of designer and user.
Basically, the cathode ray tube (CRT) monitor is the effect that reaches demonstration through the method for VGA, and wherein, the viewing area is cut into pixel (pixels) sequence that comprises horizontal line and vertical line.For instance, the viewing area is cut into 480 horizontal lines, and each horizontal line comprises 640 parts or pixel (pixels).When showing an image (image), image beam (image bean) begins to scan a horizontal line by a corner of screen earlier.After scanning this horizontal line and finishing, image beam is perpendicular positioning just, and begins to scan another horizontal line.So repeat constantly, till the image (image) of whole screen upgrades.This kind image display pattern in the multiple mode of per second (second) with the quality of guaranteeing image (image) and correct time of developing.
Because the VGA method for displaying image is very ripe, so itself and numeral, the compatibility of plane formula panel display becomes very important.Promote numeral to show and the use of VGA type of drive and image displaying card that a basic problem need overcome.The signal of the red, green, blue element of each image pixel (pixels) is simulation, and these analog signals must be converted to digital signal to drive the digital pixel on the plane formula panel display.Therefore, picture signal is that digital process is necessary and important by analog-converted.
Please refer to Fig. 1, Fig. 1 is the flow chart that picture signal is handled in the prior art.In circuit 10, this picture signal input A (t) of a class is sampled (sample) and is kept (hold).For instance, this picture signal input A (t) of class may be a colour signal from VGA display card on the PC.Sampling (sample) and maintenance (hold) circuit 10 main purposes are in a set time of being controlled by sampling (sample) pulse clk_s, carry out the sampling (sample) of this picture signal of class A (t).Sampling (sample) numerical value of A (t) can be represented as S
i, wherein Si is the numerical value among the clk_s circulation i.As sampling (sample) numerical value S
iAfter the generation, this numerical value will by a class this/digital converter changes (ADC) and is changed to a digital signal.
Refer again to Fig. 2, Fig. 2 shows that two sequential charts are to be illustrated in the sampling process a potential problem.Fig. 2 has also shown this picture signal of class A (t) and sampling (sample) pulse clk_s.This picture signal of class A (t) 11 has two states, and one is pixel number state 18 and transition status 22.Each pixel number state 18 is represented a single position on the screen.This picture signal of class A (t) is converted to a pixel number state 18 so that general image lines transmit sequentially by a pixel number state 18.On behalf of this picture signal of class A (t) 11, the delivery time 22 be in the time of an error condition.
According to above description, this picture signal of class A (t) 11 is sampled on a time point of being controlled by sampling pulse clk_s12 and clk_s13.In this example, sample point is the rising edge 14 of clk_s.In first couple of this picture signal of class A (t) 11 and clk_s12, the transmission Phase synchronization of the rising edge of sampling pulse and picture signal A (t).Therefore, sample data S2 will be by serious distortion.So from the angle of image document, sampling pulse clk_s will be regarded as being in the wrong phase place.
In second couple of this picture signal of class A (t) 11 and clk_s13, the sampling pulse phase place will move in the correct position.The rising edge of clk_s will betide on the correct pixel information phase place of picture signal A (t).Therefore, sampled images signal S
iShould be correct.From the angle of image document, the phase place arrangement of sampling pulse is for setting up a correct sample data stream S
iReal is an important factor, correct images from regeneration in particularly showing for numeral.The adjustment of this phase place is commonly referred to as phase retrieval (Phase Recovery).
Refer again to Fig. 3, Fig. 3 shows the method for phase retrieval in the prior art.This kind method is called energy accumulation phase retrieval method.This kind method is controlled image sampling S in a succession of different impulse phase arrangement
iEnergy accumulation.The phase place that energy accumulation is the highest will be decided to be correct sample phases.
Refer again to Fig. 4, Fig. 4 is the sequential chart of energy accumulation method.At first please note synchronizing signal SYNC 50 earlier.Synchronizing signal SYNC 50 is a standard signal by the output of VGA drive circuit.The pulse of SYNC results from each bar horizontal line of picture signal A (t) 52 image documents that constituted.The pulse of SYNC is to be used for synchronously and next bar data horizontal line of sign.More particularly, the horizontal pixel of last part 60 another data of explanation of SYNC pulse after waiting for a period of time, will be sent out on time point A (t).In this example, the stand-by period between A (t) the sequential point of the pixel that last part 60 and first of SYNC pulse 50 is transmitted, be commonly referred to as BACKPORCH (back along) time.Before BACKPORCH (back along) time determined that an effective picture signal A (t) sampling can begin, the time that the sampling circuit logic must be waited for.Unfortunately, the image processing circuit logic but can't clearly be known certain BACKPORCH (edge, back) time by the VGA driver.
Shown among the figure that several different sampling pulses comprise clk_s0 54, clk_s1 56, and clk_sk 58.On behalf of different sample phases, each sampling pulse can be used to sampled images signal A (t) 52.Refer again to Fig. 3, in the energy accumulation method, in step 30, is zero (by the clk_s0 representative) when phase place is initiated.Then, this zero phase will be used to the sampled images signal.Refer again to figure four, (t) 52 of A among the figure sampled by clk_s0 in rising edge 64.Refer again to figure three, in step 34, when the VGA system was set m pixel of demonstration, sampling for the first time to the sample data of the m time sampling flowed the energy of Si5 (with (si)
2Proportional) will be stored and accumulate.Then, the phase place of sampling pulse will shift (step 38).If last transfer phase place k does not finish in step 42, then handling procedure will repeat.After treating that all phase place energy are finished by accumulation, the maximum phase translation will be by decision (step 46).
Conventional energy accumulated phase restoring method among Fig. 3 and Fig. 4 exists some problems.The first, when using a large-scale display matrix, it is very big that the SYNC period (time that SYNC is interpulse) will become, so the summation circuit of needs use one complexity could be handled a large amount of sampling number S
1The second, if the change in voltage of picture signal A (t) too little (or even not having), just then this method could be used.For instance, one all is blue image, and its picture signal almost is without any the constant DC that changes, so the kind method just can't be distinguished the state of ceiling capacity.The 3rd, if occur a large amount of basic noises in the system, just then this noise can with sampled signal S
1Together by accumulated process, so the phase place that noise often leads to errors is selected by sampling.
Mention method and circuit that many picture signals are handled in the prior art, United States Patent (USP) 6,108,043 discloses one handles the circuit that possesses the interval SYNC signal of difference.United States Patent (USP) 6,144,413 disclose the method and the device of picture signal sampling, and this method can detect the difference of the filtration SYNC signal of being sampled to determine best sample phases.United States Patent (USP) 6,233 is mentioned the phase-locked loop that is used for the picture signal processing for 020.
Summary of the invention
First purpose of the present invention promptly is that a kind of effective and feasible method and circuit are being provided, and this method and circuit are used to produce a kind of optimum phase translation sampling pulse that is used to possess the picture signal A (t) of synchronizing signal SYNC pulse.
Another object of the present invention is that a kind of method and circuit are being provided, and this method and circuit do not need to use the accumulation function.
Another object of the present invention is that a kind of method and circuit are being provided, and this method and circuit can effectively be handled picture signal, comprise the signal such as the Blue screen of DC grade.
Another object of the present invention is that a kind of method and circuit are being provided, and this method and circuit can effectively present basic noise.
Another object of the present invention is that a kind of method and circuit are being provided, and this method and circuit can suitable processing have the picture signal of SYNC reference signal.
Another object of the present invention is that a kind of method and circuit are being provided, and this method and circuit can be found out correct optimal sampling phase place.
Another object of the present invention is that a kind of method and circuit are being provided, this method and circuit can with the signal removing method compatibility of beating.
For reaching the above object, the invention provides the production method of the optimum phase translation sampling pulse of a kind of picture signal A (t) that is used to possess synchronizing signal SYNC pulse, it comprises:
Step a: produce a sampling pulse, its first sampling edge will be synchronous with the pulse trailing edge of Sync_int, and wherein, the cycle of this sampling pulse is the time that is cut into every section of this SYNC pulse of M section;
Step b: from this Sync_int pulse trailing edge, surpass between the special value in the sampling pulse sample value, accumulate a sampling pulse number of cycles N to this A (t) numerical value;
Step c: in this sampling pulse and this Sync_int pulse by after the phase shift over and over again, up to starting from this Sync_int pulse trailing edge, when this A (t) numerical value is become N-1 in the interval that the sampling pulse sample value surpasses a special value by the number of cycles of sampling pulse stored count, a minimum value occurs surpassing for the first time eventually, then obtain the poorest phase place of this sampling pulse;
Steps d: add a shift value again from the poorest phase place of this sampling pulse, and produce an optimum phase sampling pulse with this A (t) that samples.
Simultaneously, the present invention also comprises the sampling pulse circuit of the optimum phase translation sampling pulse of a kind of picture signal A (t) that is used to possess synchronizing signal SYNC pulse, and this circuit comprises:
One device is in order to producing a sampling pulse, and its first sampling edge will be synchronous with the pulse trailing edge of Sync_int, and wherein, the cycle of this sampling pulse is the time that is cut into every section of this SYNC pulse of M section;
One device surpasses between the special value in the sampling pulse sample value to this A (t) numerical value in order to from this Sync_int pulse trailing edge, accumulates a sampling pulse number of cycles N;
One device is in order at this sampling pulse and this Sync_int pulse quilt over and over again after the phase shift, up to starting from this Sync_int pulse trailing edge, when this A (t) numerical value is become N-1 in the interval that the sampling pulse sample value surpasses a special value by the number of cycles of sampling pulse stored count, a minimum value occurs surpassing for the first time eventually, then obtain the poorest phase place of this sampling pulse;
One device adds a shift value again in order to the poorest phase place from this sampling pulse, and produces an optimum phase sampling pulse with this A (t) that samples.
As for detailed construction of the present invention, application principle, effect and effect, then the explanation of doing with reference to following adjoint can be understood completely:
Description of drawings
Fig. 1 is used for the sampling of picture signal sampling and the configuration diagram of holding circuit logic in the prior art;
Fig. 2 is the schematic diagram of bursts of error phase place and correct impulse phase in the picture signal sampling process in the prior art;
Fig. 3 and Fig. 4 are the schematic diagram that uses energy accumulation phase retrieval method in the prior art;
Fig. 5 is the schematic diagram of the most preferred embodiment of use phase retrieval method of the present invention;
Fig. 6 and Fig. 7 are the schematic diagram of phase retrieval method time sequence status of the present invention;
Fig. 8 is the schematic diagram of the most preferred embodiment of phase retrieval method circuit logic of the present invention.
Description of reference numerals: 10 sampling and maintenance; 11 picture signal A (t); 12 sampling pulses; 13 sampling pulses; 14 rising edges; 18 pixel number states; 22 pixel transitions states; 30,34,38,42,46-step; 50 synchronizing signals; 52 picture signals; 54,56,58 sampling pulses; The last part of 60-SYNC pulse; 64,66,68-rising edge; 100,104,108,112-step; 120,128,136,144-SYNC pulse signal; 124 picture signal A (t); 132,140,148-sampling pulse; 150,154,162,164-SYNC pulse signal trailing edge; 180,184,190-SYNC pulse signal; 188,194 sampling pulses; 196,198 pulse sections; 220 phase-locked loop circuits (PLL); 230 phase interpolation circuits; 240 sampling and maintenance; The 250 signals elimination circuit of beating.
Embodiment
The invention reside in provides a kind of method and device, possesses the optimum phase translation sampling pulse of the picture signal A (t) of synchronizing signal SYNC pulse in order to generation.Clearly, the person skilled in the art can do and modify or change, right does not anyly break away from the equivalence that preferred embodiment spirit of the present invention does and modifies or change, must be included in the present patent application claim.
Please refer to Fig. 5, Fig. 5 is for using the schematic diagram of one of phase retrieval method of the present invention most preferred embodiment.This kind method is called the phase place increase and causes backporch (edge, back) to reduce the weakened phase restoring method of (PIBD), or is called PIBD weakened phase restoring method.The key of this method is looked for the poorest situation phase shift when the sampled images data, afterwards a fixed displacement value is added on this poorest situation phase shift to produce an optimal sampling time point.
The most preferred embodiment of Fig. 5 has illustrated some important features of the present invention, and further specified in the sequential chart of Fig. 6 and Fig. 7.This method comprises, in step 100, produces a sampling pulse, its first the sampling edge will be synchronous with the pulse trailing edge of Sync_int, wherein, the cycle of this sampling pulse is this SYNC pulse that is cut into the M section.Please refer to Fig. 6, SYNC pulse signal 120 decision SYNC frameworks are to form independent lines of image document on picture signal A (t) 124.The most important notion of this signal processing step is to produce a sampling pulse clk_s synchronous with SYNC pulse signal trailing edge 150.In addition, pulse period (T
Clk) must equal to be cut into the SYNC period (T of m section (m is the number of each bar image line horizontal pixel)
Sync).The method that produces sampling pulse clk_s the best is used a phase-locked loop circuit (PLL).
Other one important but dispensable step is, before producing the sampling pulse step (step 100), can insert the signal removal process of beating.Please refer to Fig. 7, SYNC pulse signal 180 presents violent jumping phenomena among the figure, and wherein, pulse edge 196 has moved and can't be consistent synchronously with sampling pulse.S like this can lead to errors
iRead in and make deterioration of efficiency.One signal is beated and is eliminated circuit and can be used to eliminate this signal and beat and produce the pulse signal SYNC0 184 that a no signal is beated.The pulse signal SYNC0 that this no signal is beated will keep the correct edge position 198 of this pulse signal SYNC.Pulse signal SYNC0 will be used to be used as a SYNC pulsed reference signal in remaining signal processing and in the production process of synchronous sampling pulse clk0 188.Notice that the trailing edge from the time point of trailing edge to SYNC0 is the SYNC framework, the sampling pulse clk0 in the SYNC framework comprises m circulation.
Most important characteristic of the present invention is the sampling pulse clk0 188 and the pulse signal sync0 189 that can produce a phase shift.The sampling pulse clk0 194 of phase shift and pulse signal sync0 190 see through one to separate and adjustable phase shift summation shift value and getting in the sampling pulse clk0 of non-phase shift.See through and select correct phase shift summation, method of the present invention can be selected the poorest sample mode and optimal sampling state.
Please refer to Fig. 5, in phase shift 0, this first this A (t) numerical value of sampling edge that the number of times of the sampling pulse circulation N in the trailing edge of SYNC pulse will be calculated up to this sampling pulse surpasses a minimum value (step 104).Refer again to Fig. 6, give special heed to PHASE 0, the trailing edge 154 of sync_int 128 is synchronous with the rising edge of 0 pulse cycle of clk_s 158.Notice that the displacement of phase place 0 is the phase shift summation of a separation and non-zero.In fact, the displacement time of phase place 0 may be 0 second.
Between effectively transmitting the first time of SYNC 120 trailing edges 150 and image input signal A (t) 124, the stand-by period that is produced by the VGA system is called BACKPORCH (edge, back).In the example of PHASE 0, BACKPORCH (edge, back) can be regarded as surpassing a minimum voltage from phase shift sync_int up to the transmission of A (t).The number of times that method of the present invention is calculated the clk_s pulse cycle produces and gives a numerical value of N up to this transmission.In the example of PHASE 0, this transmission betides among the N pulse cycle, and the length of BACKPORCH (edge, back) is the N pulse cycle.
Refer again to Fig. 5, sampling pulse and SYNC pulse are that phase shift surpasses a minimum value (step 108) for the first time up to A (t) numerical value of first sampling edge of sampling pulse in pulse cycle N-1.This step has been set up the poorest phase shift of a sampling pulse clk_s.Refer again to Fig. 6, please be careful PHASE i, phase shift i+ Δ t (wherein, Δ t → 0) moves sampling pulse clk_s on the time point that transmits for the first time as for A (t) in the N-1 pulse cycle.In this example, the length of BACKPORCH (edge, back) is the N-1 pulse cycle.
Please be careful, the phase shift of sync_int and clk_s be betide one extremely short and independently in the time.For instance, betide in 0.4 millisecond.Therefore, because the increase of phase shift can cause the BACKPORCH minimizing of (edge, back) time, so the transmission time point in N pulse cycle and N-1 pulse cycle can be found.In PHASE i example, the crucial length that transmits the BACKPORCH (edge, back) of point is the N-1 pulse cycle, and sync_int 136 and clk_s 140 are shifted phase place by phase i.
PHASE i example is very important in the present invention, and because of it has defined the poorest sampling time point, the poorest time point of A (t) sampling is in transmitting.But because this poorest sampling time point can be defined and by phase-locked loop locking, A (t) reference point of best time point (displacement of the poorest sampling time point) of sampling so it can be used to make decision.
At last, refer again to Fig. 5, sampling betides in the displacement of the poorest sampling time point to produce a preferable phase shift sampling pulse (step 112).Because first delivering position of picture signal has been determined and corresponding to the boundary line of N and N-1 pulse cycle, so, in order to the optimal phase shift (T of the actual sampling of carrying out A (t)
Optimum) can be defined as the poorest phase shift (T
d) add a displacement and be expressed as pulse period (T
Clk) some, its formula is as follows:
T
optimum＝T
d+C+T
clk
Wherein, C can be any numerical value between 0 and 1.In a desirable example, best displacement can be C=1/2.Yet, if when the delivery time of each data was considered into, the numerical value of C can be between 2/3 to 3/4.
Method of the present invention comprises some advantage, and the first, optimal sample phases (T
Optimum) in being defined in the independent phase translation step accurately.The second, need not use energy accumulation method complicated in the common technology.The 3rd, be the primary transmission of A (t) because of the key of its technology but not accumulate whole signal crossfire S
iEnergy, this method is not subject to the image signal characteristic.Therefore, this method is applicable to the situation of full Blue screen, and can be applicable to the image signal of any SYNC of comprising reference signal.
Please refer to Fig. 8, the explanation one suitableization phase shift sampling pulse circuit of the synchronous images signal A (t) that comprises synchronous SYNC pulse that is used to sample among the figure.This circuit can use the PIBD method of aforementioned discussion, and this circuit comprises that a device is in order to produce a sampling pulse 220.First sampling edge of sampling pulse clk0 and the trailing edge of sync0 pulse are synchronous.Wherein, the period of this sampling pulse comprises this SYNC pulse that is cut into the M section.The optimum device that produces sampling pulse comprises a phase-locked loop circuit (PLL) 220.The input of phase-locked loop circuit (PLL) 220 treatment S YNC signals, in addition, a sync0 that no signal is beated and a divider M also are transfused to produce pulse output clk0, wherein, the period of clk0 equals a sync0 period that is cut into the M section, and wherein the trailing edge of first sampling edge of clk0 and sync0 pulse is synchronous.
From the above mentioned, a signal is beated and is eliminated the signal that circuit 250 can be used to eliminate the SYNC pulse signal and beat.This circuit is very unimportant for the present invention, but can provide great improvement on using.Secondly, a phase interpolation circuit 230 can be used to accumulate this sampling pulse number of cycles N and starts from this SYNC pulse trailing edge, eventually to this A (t) numerical value in the sampling pulse sample value above a special value; This phase interpolation circuit 230 also can in order in this sampling pulse and this SYNC pulse by after the phase shift over and over again, up to starting from this SYNC pulse trailing edge, become N-1 in the interval that the sampling pulse sample value surpasses a special value by the number of cycles of sampling pulse stored count to this A (t) numerical value eventually, then system obtains the poorest phase place of this sampling pulse; And one device 240 add a shift value again in order to phase place from this sampling pulse, and produce an optimum phase sampling pulse with this A (t) that samples.This phase interpolation circuit 230 can produce the poorest phase shift pulse clk_s.This poorest phase shift pulse clk_s is connected with an OFFSET so that the sample time of image signal A (t) is moved to a preferable sample time from the poorest phase place.
In sum, the production method and the device of the optimum phase translation sampling pulse of a kind of picture signal A (t) that is used to possess synchronizing signal SYNC pulse of the present invention provide another kind of enforceable selection on picture signal is handled.
But the above only is a preferred embodiment of the present invention, is not to be used for limiting scope of the invention process.Be that the equalization that all the present patent application claims are done changes and modification, be all the contained lid of claim of the present invention.
Claims (17)
1. the production method of the optimum phase translation sampling pulse of a picture signal A (t) who is used to possess synchronizing signal SYNC pulse, it is characterized in that: it comprises:
Step a: produce a sampling pulse, its first sampling edge will be synchronous with the pulse trailing edge of Sync_int, and wherein, the cycle of this sampling pulse is the time that is cut into every section of this SYNC pulse of M section;
Step b: from this Sync_int pulse trailing edge, surpass between the special value in the sampling pulse sample value, accumulate a sampling pulse number of cycles N to this A (t) numerical value;
Step c: in this sampling pulse and this Sync_int pulse by after the phase shift over and over again, up to starting from this Sync_int pulse trailing edge, when this A (t) numerical value is become N-1 in the interval that the sampling pulse sample value surpasses a special value by the number of cycles of sampling pulse stored count, a minimum value occurs surpassing for the first time eventually, then obtain the poorest phase place of this sampling pulse;
Steps d: add a shift value again from the poorest phase place of this sampling pulse, and produce an optimum phase sampling pulse with this A (t) that samples.
2. the production method of the optimum phase translation sampling pulse of the picture signal A (t) that is used to possess synchronizing signal SYNC pulse as claimed in claim 1 is characterized in that: before step a, comprise that also one eliminates the step that signal is beated in the described SYNC pulse.
3. the production method of the optimum phase translation sampling pulse of the picture signal A (t) that is used to possess synchronizing signal SYNC pulse as claimed in claim 1, it is characterized in that: this SYNC pulse comprises a horizontal synchronization pulse, in addition, M then is the number of pixels on the horizontal line that is positioned at the numeral demonstration.
4. the production method of the optimum phase translation sampling pulse of the picture signal A (t) that is used to possess synchronizing signal SYNC pulse as claimed in claim 1, it is characterized in that: this shift value comprises the pulse period of this sampling pulse 1/2.
5. the production method of the optimum phase translation sampling pulse of the picture signal A (t) that is used to possess synchronizing signal SYNC pulse as claimed in claim 1, it is characterized in that: this shift value comprises the pulse period of this sampling pulse 3/4.
6. the production method of the optimum phase translation sampling pulse of the picture signal A (t) that is used to possess synchronizing signal SYNC pulse as claimed in claim 1, it is characterized in that: this synchronous images signal A (t) comprises the picture signal of a VGA form.
7. the production method of the optimum phase translation sampling pulse of the picture signal A (t) that is used to possess synchronizing signal SYNC pulse as claimed in claim 1 is characterized in that: first sampling its rising edge of cause (rising edge) of this sampling pulse constitutes.
8. the production method of the optimum phase translation sampling pulse of the picture signal A (t) that is used to possess synchronizing signal SYNC pulse as claimed in claim 1, it is characterized in that: this shift value comprises the some of this sampling pulse.
9. the sampling pulse circuit of the optimum phase translation sampling pulse of a picture signal A (t) who is used to possess synchronizing signal SYNC pulse, it is characterized in that: this circuit comprises:
One device is in order to producing a sampling pulse, and its first sampling edge will be synchronous with the pulse trailing edge of Sync_int, and wherein, the cycle of this sampling pulse is the time that is cut into every section of this SYNC pulse of M section;
One device surpasses between the special value in the sampling pulse sample value to this A (t) numerical value in order to from this Sync_int pulse trailing edge, accumulates a sampling pulse number of cycles N;
One device is in order at this sampling pulse and this Sync_int pulse quilt over and over again after the phase shift, up to starting from this Sync_int pulse trailing edge, when this A (t) numerical value is become N-1 in the interval that the sampling pulse sample value surpasses a special value by the number of cycles of sampling pulse stored count, a minimum value occurs surpassing for the first time eventually, then obtain the poorest phase place of this sampling pulse;
One device adds a shift value again in order to the poorest phase place from this sampling pulse, and produces an optimum phase sampling pulse with this A (t) that samples.
10. the sampling pulse circuit of the optimum phase translation sampling pulse of a kind of picture signal A (t) that is used to possess synchronizing signal SYNC pulse as claimed in claim 9 is characterized in that: comprise that more a device beats in order to the signal of eliminating in this SYNC pulse.
11. the sampling pulse circuit of the optimum phase translation sampling pulse of a kind of picture signal A (t) that is used to possess synchronizing signal SYNC pulse as claimed in claim 9, it is characterized in that: described device is in order to produce a sampling pulse, its first the sampling edge will be synchronous with the pulse trailing edge of Sync_int, also comprise a phase-locked loop.
12. the sampling pulse circuit of the optimum phase translation sampling pulse of a kind of picture signal A (t) that is used to possess synchronizing signal SYNC pulse as claimed in claim 9, it is characterized in that: the SYNC pulse comprises a horizontal synchronization pulse, in addition, M then is the number of pixels on the horizontal line that is positioned at the numeral demonstration.
13. the sampling pulse circuit of the optimum phase translation sampling pulse of a kind of picture signal A (t) that is used to possess synchronizing signal SYNC pulse as claimed in claim 9, it is characterized in that: this shift value comprises the cycle of this sampling pulse 1/2.
14. the sampling pulse circuit of the optimum phase translation sampling pulse of a kind of picture signal A (t) that is used to possess synchronizing signal SYNC pulse as claimed in claim 9, it is characterized in that: this shift value comprises the cycle of this sampling pulse 3/4.
15. the sampling pulse circuit of the optimum phase translation sampling pulse of a kind of picture signal A (t) that is used to possess synchronizing signal SYNC pulse as claimed in claim 9, it is characterized in that: this shift value comprises the part cycle of this Sample interval, and this numerical value partly can from 0 to 1.
16. the sampling pulse circuit of the optimum phase translation sampling pulse of a kind of picture signal A (t) that is used to possess synchronizing signal SYNC pulse as claimed in claim 9, it is characterized in that: this synchronous images signal A (t) comprises the picture signal of a VGA form.
17. the sampling pulse circuit of the optimum phase translation sampling pulse of a kind of picture signal A (t) that is used to possess synchronizing signal SYNC pulse as claimed in claim 9 is characterized in that: its rising edge of sampling cause of this sampling pulse constitutes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031429823A CN100435554C (en) | 2003-06-13 | 2003-06-13 | Method and circuit for restoring of weakened phase caused by phase reinforcement in image signal processing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031429823A CN100435554C (en) | 2003-06-13 | 2003-06-13 | Method and circuit for restoring of weakened phase caused by phase reinforcement in image signal processing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1567980A CN1567980A (en) | 2005-01-19 |
| CN100435554C true CN100435554C (en) | 2008-11-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031429823A Expired - Fee Related CN100435554C (en) | 2003-06-13 | 2003-06-13 | Method and circuit for restoring of weakened phase caused by phase reinforcement in image signal processing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100435554C (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1207850A (en) * | 1996-01-16 | 1999-02-10 | 麦克罗维西恩公司 | Method and apparatus for improving effects of color burst modifications to video signal |
| JP2000305536A (en) * | 1999-02-19 | 2000-11-02 | Matsushita Electric Ind Co Ltd | Image signal processing device |
| CN1345435A (en) * | 1999-03-26 | 2002-04-17 | 富士通西门子电脑股份有限公司 | Method and device for compensating phase for flat screens |
-
2003
- 2003-06-13 CN CNB031429823A patent/CN100435554C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1207850A (en) * | 1996-01-16 | 1999-02-10 | 麦克罗维西恩公司 | Method and apparatus for improving effects of color burst modifications to video signal |
| JP2000305536A (en) * | 1999-02-19 | 2000-11-02 | Matsushita Electric Ind Co Ltd | Image signal processing device |
| CN1345435A (en) * | 1999-03-26 | 2002-04-17 | 富士通西门子电脑股份有限公司 | Method and device for compensating phase for flat screens |
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| Publication number | Publication date |
|---|---|
| CN1567980A (en) | 2005-01-19 |
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