CN100421255C - Fully depleted soi multiple threshold voltage application - Google Patents
Fully depleted soi multiple threshold voltage application Download PDFInfo
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- CN100421255C CN100421255C CNB2005100679140A CN200510067914A CN100421255C CN 100421255 C CN100421255 C CN 100421255C CN B2005100679140 A CNB2005100679140 A CN B2005100679140A CN 200510067914 A CN200510067914 A CN 200510067914A CN 100421255 C CN100421255 C CN 100421255C
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Abstract
The invention relates to the application of whole deficiency SOI multi-critical voltage. An integrated circuit includes a substrate and a bury-type dielectric layer which is formed in the substrate. The bury-type dielectric layer is provided with a first thickness in a first area, a second bury-type dielectric layer thickness in a second area and a step between the first and the second area. A semiconductor layer is arranged on the bury-type dielectric layer. The bury-type dielectric layer thickness can change with various different applications. And applied transistors can be provided with different expected critical voltages, such as the core application, the low power supply application and I/O application. In addition, different bury-type oxide thicknesses can be used in a same wafer for providing the Vth regulation ability which is actually preserved to an FD SOI back sluice bias element that requires Vth regulation, such as the core application, the low power supply application and I/O application.
Description
Technical field
The present invention relates to a kind of semiconductor element, particularly the system and method for using relevant for a kind of complete depletion type SOI multiple threshold voltage.
Background technology
In order to make emulative electronic installation, for instance, all expect usually can output the semiconductor wafer of several zoness of different of tool (for example core space, low power supply area, I/O district), and these zoness of different have the semiconductor element that can change according to speed and power supply.Can provide the semiconductor element of these features of some or all to comprise silicon-on-insulator (SOI) element.Yet an existing challenge in the SOI technology has remarkable critical voltage (V for forming
Th) the thin Si passage SOI I/O element of control ability.For instance, in SOI I/O uses, because can having a bigger drain than body silicon wafer element, the SOI element cause energy barrier to reduce (DIBL) effect (it is caused by the buoyancy aid characteristic), so need a higher V
ThIn addition, the high voltage that provides in the I/O district usually can increase the problem of relevant leakage current.When the SOI component thickness is dwindled, to carry out usefulness and reduce floater effect in order to improve, solve more and more important that these shortcomings will become.
Several prior art method attempt to control V via the transistorized main body current potential of control SOI
ThFirst method is to see through the base material contact hole transistor bodies is strapped in the accurate position of a fixed voltage.Yet although the floater effect (FBE) in the reduction SOI element, this main body constraint method may suffer from area and speed loss.In addition, can dwindle the SOI silicon thickness by the benefit of main body constraint method acquisition and make size decreases, this is that contact is useless because the body resistance that increases will make main body.
Another kind is used to control V
ThKnown main body method be that channel region mixes.Although improve V
ThYet passage is implanted the vague and general ability that can reduce the SOI element, uses by FBE execution usefulness is descended.
The general using method that another kind is used for the FBE reduction is to make the silicon thickness attenuation, fully the channel region of depletion type (FD) SOI element.FD SOI element can make extra knock-on ionization (I-I) induce carrier to clear out of from passage, uses compacting FBE.The entity of FBE compacting situation can obviously improve the critical voltage control ability in the transistor channels district.
The transistorized body region of bias voltage SOI is element V traditionally
ThA pith of control is facilitated V and the attenuation of silicon body thickness has been become
ThA preferred approach of control.Yet, concerning the SOI technology, still need to provide enough abilities of returning the lock bias voltage, to reach the V of expection
ThNumerical value.
Another kind is used to reach expection V
ThKnown and acceptable method be, via the change gate electrode material composition change the gate electrode operational function.Fig. 1 a and 1b are known element 100 and 102, wherein can change gate electrode 104 materials and form and corresponding gate electrode 104 operational functions, with the critical voltage of control element.CMOS structure 100 shown in Fig. 1 a is proposed by people such as Polishchuk, title in the paper is " Dual Work Function Metal Gate CMOS Transistors byNi-Ti Interdiffusion ", and be exposed in IEEE Electron Device Letters, Vol.23, No.4, April 2002, incorporate into and do reference herein.Fig. 1 a demonstrates gate electrode 104 and comprises that nickel and titanium are positioned in the PMOS district 106, and comprises that titanium is positioned on the nmos area 108.
FD SOI transistor 102 shown in Fig. 1 b is proposed by H.Wakabayashi, title in the paper is " A Novel W/TiNx Metal Gate CMOS Technology UsingNitrogen-Concentration-Controlled TiNx Film ", and be exposed in IEEE IEDM, Dec 1999, incorporate into and do reference herein, its gate electrode 104 materials are formed and are comprised the nitrogen N of tungsten W, titanium Ti, first concentration and the nitrogen Nx of second concentration.Material is formed the gate operational function that changes each gate electrode 104 of meeting change, uses the critical voltage that changes FD SOI transistor 102.
Fig. 1 a and 1b are presented at gate electrode material in the zonule of wafer and form and change.Yet for instance, it is difficult in providing different gate operational function materials to SOI core application and I/O element application on the wafer.In traditional circuit application, be about 0.65eV to the critical voltage of 3.3eV I/O element, and be about 0.2eV the critical voltage of 1.0eV core parts.The target critical voltage can reach via use wellblock or bag district's implantation mode in the main body base material.Yet, concerning complete depletion type SOI element,, adjust so critical voltage can't be implanted via passage or bag district because heavy base material concentration can be transformed into the FD element partially depleted element and reduce and carry out usefulness.Concerning complete depletion type SOI element, a method that reach different critical voltage is the gate operational function for a change.This can prove by following equation:
For instance, be constant if we keep Na (base material concentration), we may need another variable, use Control Critical voltage to one expected value in different application.Because metal gate development has recently become mainstream technology, so gate operational function (Φ m) is to be used for V
ThA good candidate of adjusting.This is that compared to polysilicon, the metal gate not only can improve gate resistance because doing when integrating with high-k dielectric material, and it has characteristic preferably, shown in Fig. 1 C.
Summary of the invention
The objective of the invention is to, overcome existing complete depletion type SOI critical voltage and use the defective that exists, and provide a kind of integrated circuit of new structure, it has complete depletion type SOI multiple threshold voltage element and non-SOI multiple threshold voltage element, solving or to prevent these and other problems and reach technical advantages, thereby be suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.Use according to a kind of complete depletion type SOI multiple threshold voltage that the present invention proposes, to solve or to prevent these and other problems and reach technical advantages, in other embodiments, the present invention proposes a kind of integrated circuit, and it has complete depletion type SOI multiple threshold voltage element and non-SOI multiple threshold voltage element.
According to an explanation embodiment of the present invention, a kind of integrated circuit comprises a base material and the buried dielectric layer that is formed in this base material.Buried dielectric layer have one first thickness in first district, one second buried medium thickness is in second district, and a ladder is between between this first and second district.Semi-conductor layer is positioned on this buried dielectric layer.
According to another explanation embodiment of the present invention, a kind of semiconductor wafer (as known crystal grain) has one first district and one second district.Semiconductor wafer also comprises a base material and the semi-conductor layer that is positioned on the base material.Semiconductor wafer more comprises a buried dielectric layer, is arranged in to small part to be formed under the semiconductor layer of this base material.Buried dielectric layer has one first thickness in this first district and have one second thickness in this second district, both ladders of being separated by.The first transistor with first gate electrode is formed in this first district with the transistor seconds with second gate electrode.The 4th transistor utmost point that the 3rd transistor AND gate with the 3rd gate electrode has the 4th gate electrode is formed in this second district.
According to another explanation embodiment of the present invention, a kind of semiconductor wafer comprises a base material.Base material comprises at least one buried dielectric layer, and buried dielectric layer has the first buried medium thickness in a V
ThThe district and the second buried medium thickness are in the 2nd V
ThThe district, the first buried medium thickness is greater than the second buried medium thickness, wherein a V
ThWith the 2nd V
ThBetween gap be about 0.15-0.45eV.Comprise in the particular example and have about 0.2eV (less than 1.8) V
ThA core space and have about 0.65eV V
ThAn I/O district, wherein the buried medium thickness of core space is greater than the buried medium thickness in I/O district.In other were used, the critical voltage in I/O district can be greater than 1.8eV.
According to another explanation embodiment of the present invention, a kind of semiconductor wafer comprises a base material.Base material comprises at least one buried dielectric layer, buried dielectric layer have the first buried medium thickness in core space and the second buried medium thickness in the I/O district, the first buried medium thickness is greater than the second buried medium thickness.This wafer comprises that also one first complete depleted silicon on insulator p passage gold oxygen half (FD SOI PMOS) transistor is in core space, the one FD SOI PMOS transistor has first gate electrode and is positioned on first brake-pole dielectric layer, and first brake-pole dielectric layer has first operational function.Semiconductor wafer more comprises one the one FD SOI n passage gold oxygen, half (NMOS) transistor in core space, and a FD SOI nmos pass transistor has second gate electrode and is positioned on second brake-pole dielectric layer, and second brake-pole dielectric layer has second operational function.Semiconductor wafer more comprises one the 2nd FD SOI PMOS transistor in I/O (I/O) district, and the 2nd FD SOI PMOS transistor has the 3rd gate electrode and is positioned on the 3rd brake-pole dielectric layer, and the 3rd brake-pole dielectric layer has the 3rd operational function.Semiconductor wafer more comprises one the 2nd FD SOI nmos pass transistor in the I/O district, and the 2nd FD SOI nmos pass transistor has the 4th gate electrode and is positioned on the 4th brake-pole dielectric layer, and the 4th brake-pole dielectric layer has the 4th operational function.The first, second, third and the 4th operational function comes down to differ from one another.
Preferred embodiment of the present invention provides a kind of obvious advantage of critical voltage of relevant controlling semiconductor element, particularly relevant for the complete depletion type SOI element of the different circuit application of tool on a wafer.For instance, the present invention can be used for comprising requirement thin with the element of buried oxide layer on a single die as thin as a wafer.For instance, application comprises that core application, low application of power and I/O use.The Improvement type control mode of the critical voltage of element in different application, can cause reduction of resistance barrier and enhancement type element and circuit to be carried out in the usefulness at the drain of FD SOI element provides better control ability.
By technique scheme, the complete depletion type SOI multiple threshold voltage of the present invention is used has following advantage at least: buried medium thickness can change according to various different application, and the transistor of these application can have different expection critical voltages, and for example core application, low application of power and I/O use.Another advantage is, can use different buried oxidated layer thickness in same wafer, keeps to requiring V so that essence to be provided
ThThe V of the FD SOI back-gate bias element of adjusting
ThAdjustment capability, for example core application, low application of power and I/O use.
In sum, the integrated circuit of special construction of the present invention, it has complete depletion type SOI multiple threshold voltage element and non-SOI multiple threshold voltage element, to solve or to prevent these and other problems and reach technical advantages.It has above-mentioned many advantages and practical value, and in like product, do not see have similar structural design to publish or use and really genus innovation, no matter it all has bigger improvement on product structure or function, have large improvement technically, and produced handy and practical effect, thereby being suitable for practicality more, and having the extensive value of industry, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 a and 1b are known pair of operational function metal to-metal brake gated transistors; And 1c figure is the correlation between critical voltage and the gate operational function.
Fig. 2 a-2c is the profile according to the operating procedure of first manufacture method of the present invention first explanation embodiment.
Fig. 2 d is the profile of buried dielectric material step.
Fig. 2 e is the first explanation embodiment of the present invention.
Fig. 2 f is the second explanation embodiment of the present invention.
Fig. 3 a-3h is the profile according to the operating procedure of second manufacture method of the present invention the 3rd explanation embodiment.
100:CMOS structure 102,214,260,261,262,263:FD SOI transistor
104,250,252,254,256: gate electrode 106:PMOS district
108:NMOS district 200: base material
202: core space 204: the I/O district
206: cover curtain 208: dielectric material
209,210: buried dielectric layer 211: frame of broken lines
212: inclined-plane side 213: wellblock
215: ladder 220: shallow slot isolation structure
222: semiconductor layer 223: wafer
224: brake-pole dielectric layer 225: thickness
226: step 228: polysilicon layer
230: polysilicon surface 232: photoresist
234:n type doped polysilicon area 236:n type admixture mixes
238,240: metal level 270: source electrode
272: drain 274: gate
280,282: contact hole
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, the complete depletion type SOI multiple threshold voltage that foundation the present invention proposes is used its embodiment, structure, feature and effect thereof, describe in detail as after.
The present invention will be illustrated in down with preferred embodiment, and promptly a kind of complete depletion type SOI multiple threshold voltage is used.Yet the present invention also can be used for other semiconductor elements and has on base material needing on the semiconductor application of multiple threshold voltage.
Shown in Fig. 2 a-f, base material 200 comprises the semiconductor substrate material.Substrate material preferably has crystallization direction for＜100〉the p type crystalline silicon material in fact of mixing.Certainly, for instance, base material 200 can be that the n type mixes, and has the crystallization direction as p type doping base material, or other crystallization directions are for example＜111〉and＜110.Base material 200 can comprise any material that is fit to as semiconductor substrate, for example GaAs, indium phosphide, silicon, germanium, carbon, and combination, comprise resilient coating, and the gradual part that resilient coating comprises a semi-conducting material gradual silicon gallium resilient coating for example.For instance, base material 200 also can be a strain type semiconductor, for example strained silicon or ceramic wafer.
The example of I/O element can comprise for example tristate buffer, input buffer and output buffer.The I/O element can comprise the Electrostatic Discharge circuit, and can provide a tolerance to complex voltage.I/O district for example I/O district 204 is formed on the suburb of wafer, itself and the center distance of being separated by.Core space for example core space 202 generally is to be arranged in each zone of wafer, and it is near the center.Yet I/O and core space also can have other configuration modes.Core space 202 generally comprises the transistor with the high-speed and low power requirement that is used for large-scale long-pending body (LSI) circuit (for example ULSI, VLSI), and for example processor, controller and special integrated circuit are used (ASICs).
See also Fig. 2 b, deposition one is covered curtain 206 in the I/O district 204 of base material 200, and exposes the core space 202 of base material 200.Base material 200 is carried out an implantation process, implant the expose portion of dielectric material 208, to form a buried dielectric layer 210 to silicon substrate 200.Implantation process is an oxygen implantation process preferably, for example implants with oxygen and separates (SIMOX).And implantation process certainly is for example to implant separation (SIMNI), implant with nitrogen with oxygen and separate or internal heat oxidation (ITOX) with nitrogen.The SIMOX implantation step comprises that preferably use is greater than (for example every square centimeter 1.8 * 10 of the oxonium ion implantation process of the base material temperatures of 600 degree approximately Celsius
18).
The other materials for example implantation process of nitrogen and hydrogen can be carried out simultaneously or subsequently.For instance, buried dielectric layer 210 can be the hydrogenation oxide layer of a nitriding and oxidizing layer or hybrid silica.It is available to prevent the impurity dopant diffusion to buried oxide layer, to use preventing that element execution usefulness from reducing to implant the nitriding and oxidizing layer.For instance, impurity dopant diffusion phenomenon may take place in the impurity admixture implantation process during well forms manufacturing step, for example n type well (n wells).
See also Fig. 2 c, divest cover curtain 206, and then implant dielectric material 208 preferably oxygen to the core space 202 and I/O district 204 of silicon substrate 200.The second oxygen implantation step makes buried dielectric layer 210 be extended to the I/O district 204 of silicon substrate 200, and makes buried dielectric layer 210 thickenings in the core space 202.The thickness t of buried dielectric layer 210 in the core space 202
CorePreferably about 100 dusts.The thickness t of buried dielectric layer 210 in the I/O district 204
I/OPreferably about 300 dusts.The scope of the thickness of buried dielectric layer can be between about 50 dusts and about 2000 dusts.
After implantation process, the SIMOX process comprises a high temperature (1300 degree for example approximately Celsius) first tempering step that carries out base material.In other explanations embodiment, can repeat repeatedly to cover the step that curtain and buried dielectric layer are implanted, use on wafer the buried dielectric layer of any thickness of formation in any zone.
Buried dielectric layer 210 separates semiconductor layer 222 by wafer substrate 200.Wafer 223 comprises that silicon 222 is positioned on the insulating barrier 210, and wafer 223 is silicon-on-insulator (SOI) wafer traditionally.Semiconductor layer 222 has a thickness 225 of about 200 dusts usually.Yet the scope of thickness 225 can be between about 50 dusts and about 500 dusts.
Have the right side angle though the buried dielectric layer ladder 215 in the frame of broken lines 211 demonstrates in graphic, right, ladder 211 preferably has an inclined-plane side 212, shown in Fig. 2 d.Fig. 2 d is the enlarged drawing of frame of broken lines 211.Side 212 inclined-planes are thickness gradients, and it is to decide according to circuit design.For instance, angled section can be an exclusion area of active region, but vacant element or passive device can be formed on wherein.This is because angled section can comprise entanglement and inconsistent electric capacity, and it may cause unsettled electronics to carry out usefulness at active member.In explanation embodiment, the ladder in buried oxide layer can have different thickness gradients, yet the scope of each thickness gradient (in vertical direction) is preferably between about 50 dusts and about 200 dusts.In some instances, may expect little spacing (less than about 0.3um) between two active regions, one has thin resistance barrier dielectric layer, and another has thick resistance barrier dielectric layer.In these examples, because the active region of a sealing, so ladder preferably is not more than the about 1/10 of spacing, to avoid the critical voltage change.
Follow-up manufacturing step forms the first explanation embodiment shown in Fig. 2 e.Shallow slot isolation structure 220 separates FD SOI transistor 214.What be arranged in buried dielectric layer 210 in the core space 202 will have a lower critical voltage than the transistor 214 that I/O district 204 is positioned at above the thinner part of buried dielectric layer 210 than the transistor above the thickness portion 214.
In the zones of different 202 and 204 of same substrate 200, change the thickness of buried dielectric layer 210, but the critical voltage of essence control FD SOI element 214.Concerning each transistor 214, lower embedding type dielectric layer 210 is as the capacitance dielectric layer between between anode and negative electrode, and anode is represented wellblock or body region 213, and negative electrode is represented the base material 200 below the buried dielectric layer 210.Change the electric capacity that buried dielectric layer 210 thickness can change transistor channels district in the wellblock 213, using according to zone 202 or 204 provides a different critical voltage to FD SOI element 214.
Because the difference in buried dielectric layer 210 thickness, the FD SOI element 214 in the I/O district 204 can have a higher possible V than the essence like in the core space 202
1In general, thin buried dielectric layer will provide a bigger V
ThAdjusting range, and thicker buried dielectric layer will provide a less V
ThAdjusting range.
In other explanations embodiment, the change of buried medium thickness is not limited in the change through the zone.Can on a wafer or a wafer, change buried medium thickness, to reach any zone of expection tool virtually any size.Though buried medium thickness is preferably critical voltage according to FD SOI element and requires and change, but buried medium thickness also can change for example temperature (for example SOI oneself heating effect), electric current and interference according to other application requirements of relevant semiconductor element operation.
Can produce phosphorus or boron doped silicon oxide in the top area of buried dielectric layer 210 in order to form ion implantation step in n type or the semi-conducting material 222 of p type wellblock 213 on buried dielectric layer 210.III-V type impurity diffuses to buried dielectric layer 210 by wellblock, upper strata 213 also may provide doped silicon oxide in the zone of buried dielectric layer 210.
The second explanation embodiment is shown in Fig. 2 f, and it demonstrates to use and surpasses two kinds of buried dielectric layer 209 thickness zone C ORE, LP and I/O on same wafer base material 200.According to the last thickness of buried dielectric layer 209, the FD SOI transistor in the follow-up silicon substrate 222 that is formed on the buried dielectric layer 209 will have different V
ThBest is, the FDSOI transistor that is formed on the thick of buried dielectric layer 209 will have a lower V than the FD SOI transistor that is formed in LP district or the I/O district
ThThe FD SOI transistor that is formed in the LP district will have a higher V than the transistor that is formed in the CORE district
ThThe FD SOI transistor that is formed in the I/O district will have a higher V than the transistor that is formed in LP district and the CORE district
Th
According to second method of the 3rd explanation embodiment, shown in Fig. 3 a-3h, comprise the buried dielectric layer 210 of the first explanation embodiment.In Fig. 3 a, shallow slot isolation structure 220 is in the silicon area 222 that is formed on the buried dielectric layer 210.Certainly, other kinds isolation structure (for example the tableland isolates and the LOCOS isolation structure) also can use.The silicon area 222 that is positioned on the buried dielectric layer 210 is thick for about 200 dusts.
Brake-pole dielectric layer 224 comprises cvd silicon oxide.The thickness of brake-pole dielectric layer 224 is about 100 dusts, and its scope can be between about 20 dusts and about 100 dusts.Brake-pole dielectric layer is formed by the high-k dielectric material with a high-k, and this high-k is greater than about 4.0.High-k dielectric material can be a metal and dielectric material, comprises for example Al of metal oxide
2O
3, Ta
2O
5, ZrO
2With HfO
2Or HfSi.Various different types of processing mode can be used on the high-k dielectric material, for example known NH
3Tempering, O+ tempering, NO tempering and N
2O tempering mode.
With a cover curtain material for example the photoresistance (not shown) cover brake-pole dielectric layer 224 in the I/O district 204, remove the brake-pole dielectric layer 224 that the part in the core space 202 exposes then, shown in Fig. 3 b.The final thickness of the brake-pole dielectric layer 224 in the core space 202 is about 8 dusts, and its scope can be between about 8 dusts and about 20 dusts.Emphasis is, as shown is one fairly large at the step 226 of 204 formation of core space 202 and I/O district.
Brake-pole dielectric layer 224 can make FD SOI element have a higher critical voltage than thickness portion, it will be formed in the I/O district 204 follow-up.Relatively, the FD SOI element that is formed in the core space 202 will have thin brake-pole dielectric layer 224 and the lower critical voltage of a correspondence.
Deposit spathic silicon layer 228 is on brake-pole dielectric layer 224, shown in Fig. 3 c.Though, polysilicon step (not shown) can be formed on the brake-pole dielectric layer step 226 in the polysilicon surface 230, but the polysilicon step is a small relatively surface features, and the polysilicon surface shown in Fig. 3 c 230 then is with the usefulness that explains through the substantial planar process.
Fig. 3 d is for forming the subsequent step of photoresist 232 on polysilicon 228.Use n type admixture to mix 236, to form n type doped polysilicon area 234 in the not shaded portions 234 of polysilicon 228.Admixture is preferably implanted with known method for implantation, and for example immersion electricity slurry ion is implanted (PIII) or immersion metal electricity slurry ion is implanted (MePIII).Admixture is phosphorus preferably, also can be arsenic, boron, Metz card spirit (BF
2), hydrogen, nitrogen, oxygen, argon, or its in conjunction with the person.
Shown in Fig. 3 e, the successive sedimentation the first metal layer 238 and second metal level 240 are on brake-pole dielectric layer 224.The thickness of the first metal layer 238 is about 50 dusts, and the thickness of second metal level 240 is about 200 dusts.Metal level 238 and 240 depositional mode are to use known deposition process, for example evaporation, sputter or various forms of chemical gaseous phase depositing process electricity slurry enhancement type chemical vapour deposition technique for example.The first metal layer 238 preferably includes titanium, and second metal level 240 preferably includes platinum.Yet the one 238 and the 2 240 metal level also can comprise for example nickel, palladium, platinum, iridium, ruthenium, rhodium, molybdenum, hafnium, aluminium, cobalt, tungsten, or its combination.And can comprise metal alloy for example bimetallic alloy, metal silicide, metal silicon nitride, doping type metal alloy and doping type metal-silicide alloy in conjunction with the person.
Carry out follow-up little shadow step, the part of second metal level 240 in the I/O district 204 is covered, remove the expose portion of second metal level 240 in the core space 202 then, shown in Fig. 3 f.Can use Wet-type etching or reactive ion etching to remove second metal level 240 of part.
Carry out second drawing process about 10 minutes with 500 degree approximately Celsius, make metal 238 and 240 diffuse to the not doping 228 and 234 districts of mixing of polysilicon, shown in Fig. 3 g.Second drawing process is in order to produce a silicotitanium gate electrode 250 and a n type doped silicon titanium alloy gate electrode 252 in core space 202.Second drawing process also can produce a titanium, platinum and silicon alloy 254 and a n type Doped with Titanium, platinum and silicon alloy 256 in I/O district 204.In explanation embodiment, a single gate electrode doping step only is described.Yet, as have the knack of known to this skill person, gate electrode can have different doping contents and different impurities.This process can be between the depositional stage of gate polysilicon layer 228, via for example several doping steps and finish via the doped in situ step.Best is that the ratio of the doping content between gate electrode is 10
5Or it is lower.
Fig. 3 h is at the structure chart of other processing procedure with Fig. 3 g after producing FD SOI PMOS transistor 260,261 and FD SOINMOS transistor 262,263.Change material and form, use making gate electrode 250,252,254 and 256 operational function can provide a corresponding critical voltage difference between FD SOI element 260,261,262 and 263.FD SOI transistor 260,261,262 and 263 critical voltage partly are by gate electrode 250,252 among Fig. 3 h, 254 and 256 operational function control.The scope of the operational function of gate electrode 250 is between about 4.7eV and approximately between the 5.0eV.The scope of the operational function of gate electrode 254 is between about 4.4eV and approximately between the 4.7eV.The scope of the operational function of gate electrode 252 is between about 4.2eV and approximately between the 4.5eV.The scope of the operational function of gate electrode 256 is between about 4.5eV and approximately between the 4.8eV.
In conjunction with buried dielectric layer 210 varied in thickness, brake-pole dielectric layer 224 varied in thickness, and gate electrode 250,252, the variation of 254 and 256 operational functions, can be at the FD SOI transistor 260 on same wafer crystal grain 200 or the same wafer, 261,262 and 263 threshold voltage variations provides the control ability of height.
The FD SOI transistor 260,261,262 and 263 that is used for explanation embodiment described herein is to be used to illustrate shortage type base material element.The present invention also can be applicable to part shortage type element, for example part shortage type silicon-on-insulator (PD SOI) transistor.The present invention illustrates that other elements among the embodiment comprise for example golden oxygen half FETs of field-effect transistor (FET) (MOSFETs), metal semiconductor FETs (MEFETs), thin-film transistor (TFTs), strain-type channel transistor and double-gate utmost point MOSFETs.Though the present invention is applicable to any technology node, right the present invention preferably is used for 65nm node and less technology node.
Contact hole 280 for example couples the source electrode 270, drain 272 of transistor 263 and the contact hole 280 in gate 274 districts, can change or uses the new operational function of formation in transistor with other modes.For instance, the metal silicide that is formed in the source area 270 of FD SOI NMOS 263 can provide one the 5th operational function in source area, makes that tungsten material and the doped polycrystalline silicon in source area 270 tops in the contact hole 280 produces diffusion.Another gate operational function is provided by the diffusion that the n type of gate electrode 256 in tungsten material in the contact hole 282 and gate electrode 274 tops is mixed polysilicon and titanium.
Preferred embodiment of the present invention provides a kind of obvious advantage of critical voltage of relevant controlling semiconductor element, particularly relevant for the complete depletion type SOI element of the different circuit application of tool on a wafer.For instance, the present invention can be used for comprising requirement thin with the element of buried oxide layer on a single die as thin as a wafer.For instance, application comprises that core application, low application of power and I/O use.The Improvement type control mode of the critical voltage of element in different application, can cause reduction of resistance barrier and enhancement type element and circuit to be carried out in the usefulness at the drain of FD SOI element provides better control ability.
An advantage of preferred embodiment of the present invention is, buried medium thickness can change according to various different application, and the transistor of these application can have different expection critical voltages, and for example core application, low application of power and I/O use.Another advantage is, can use different buried oxidated layer thickness in same wafer, keeps to requiring V so that essence to be provided
ThThe V of the FD SOI back-gate bias element of adjusting
ThAdjustment capability, for example core application, low application of power and I/O use.
Though preferred embodiment of the present invention and advantage thereof are exposed in detail; it must be appreciated; without departing from the spirit and scope of the present invention, when can doing various changes, change and retouching, so protection scope of the present invention ought be looked accompanying the claim person of defining and is as the criterion.For instance, anyly have the knack of this skill person and can learn easily, depletion type SOI multiple threshold voltage is used fully can various variations, and it is included in the scope of the present invention.
In addition, range of application of the present invention is not limited in the specific embodiments of process, machine, manufacturing, important document composition, device, method and step described in the specification.According to the present invention, anyly have the knack of this skill person and can disclose book, process, machine, manufacturing, important document composition, device, method or step, existing or learn easily in the skill thus backward, can utilize corresponding embodiment described herein, carry out in fact identical function or reach identical result in fact.Therefore, protection scope of the present invention comprises these processes, machine, manufacturing, important document composition, device, method or step.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the structure that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, but every content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (19)
1. an integrated circuit has one first district and one second district, comprising:
One base material;
One buried dielectric layer, be formed in this base material, this the buried dielectric layer that is positioned at this first district has one first thickness, this the buried dielectric layer that is positioned at this second district has one second thickness, wherein this first district is used for one first of requirement one first critical voltage to use, and wherein this second district is used for one second of requirement one second critical voltage to use, and this buried dielectric layer that wherein is positioned at this first district and this second district has the flat upper surfaces that is in same horizontal plane; And
Semi-conductor layer, be positioned on this buried dielectric layer, this semiconductor layer that wherein is arranged in this first district is formed with a first transistor, this the first transistor has one first gate electrode, and this semiconductor layer that is arranged in this second district is formed with a transistor seconds, and wherein this transistor seconds has one second gate electrode.
2. integrated circuit according to claim 1, wherein the part of this base material comprises silicon metal.
3. integrated circuit according to claim 1 wherein is positioned at the germanium that this semiconductor layer on this buried dielectric layer comprises strained silicon or semi-conducting material.
4. integrated circuit according to claim 1, more comprise a ladder between this first and second the district between, wherein this ladder height is 200 dusts or littler.
5. integrated circuit according to claim 1 comprises that a more complete depleted silicon on insulator transistor is formed in this semiconductor layer.
6. integrated circuit according to claim 1, wherein this buried dielectric layer comprises silica, nitriding and oxidizing layer, hydrogenation oxide layer, carborundum or Al
2O
3
7. integrated circuit according to claim 1, wherein this first application is the core application with one first critical voltage, and this second application is to have an I/O of one second critical voltage to use, and wherein the gap between this first critical voltage and this second critical voltage is 0.45eV or littler.
8. semiconductor wafer, wherein this semiconductor wafer has one first district and one second district, and this semiconductor wafer comprises at least:
One base material;
Semi-conductor layer is positioned on this base material;
One buried dielectric layer is formed under this semiconductor layer, and this buried dielectric layer that is positioned at this first district has one first thickness, and this buried dielectric layer that is positioned at this second district has one second thickness;
In this first district, form a first transistor with one first gate electrode and a transistor seconds with one second gate electrode; And
In this second district, form one the 4th transistor that one the 3rd transistor AND gate with one the 3rd gate electrode has one the 4th gate electrode.
9. semiconductor wafer according to claim 8, wherein:
9. semiconductor wafer according to claim 8, wherein:
This first gate electrode is to be formed by one first material, and in one first impurity that wherein has one first concentration, and this second gate electrode is to be formed by one second material, and in one second impurity that wherein has one second concentration; And
The 3rd gate electrode is to be formed by one the 3rd material, and in one the 3rd impurity that wherein has one the 3rd concentration, and the 4th gate electrode is to be formed by one the 4th material, and in one the 4th impurity that wherein has one the 4th concentration.
10. semiconductor wafer according to claim 9, wherein this first and the 3rd gate electrode has included a metal silicide and one first metal, and wherein this second and the 4th gate electrode has included a metal silicide and one second metal.
11. semiconductor wafer according to claim 9 more comprises:
One first brake-pole dielectric layer has one first brake-pole dielectric layer thickness, and be positioned at this first and second gate electrode below; And
One second brake-pole dielectric layer has one second brake-pole dielectric layer thickness, and be positioned at the 3rd and the 4th gate electrode below, wherein this second thickness can change with a scheduled volume according to this first thickness.
12. semiconductor wafer according to claim 9, wherein this first transistor has a brake-pole dielectric layer thickness, and this brake-pole dielectric layer thickness is also thinner than the brake-pole dielectric layer thickness of this transistor seconds.
13. semiconductor wafer according to claim 9, wherein this first and the 3rd gate electrode comprises titanium.
14. a method of making more than one critical semiconductor wafers, this method comprises:
Form on the insulating barrier and cover semiconductor substrate, comprise the following steps:
Form one first cover curtain in one first district of semiconductor base material;
Implant one second district of one first material to this semiconductor substrate, this implantation step forms a buried dielectric materials layer in this semiconductor substrate, this the buried dielectric materials layer that is arranged in this second district has one second thickness, uses this semiconductor substrate to be become on the insulating barrier cover semiconductor substrate;
Remove this first cover curtain to expose whole semiconductor substrate;
Implant one second material to this semiconductor substrate this first with this second district, this implantation step forms a buried dielectric materials layer in this semiconductor substrate, this buried dielectric materials layer that is arranged in this first district has one first thickness; And
Carry out first drawing process to covering semiconductor substrate on this insulating barrier.
15. method according to claim 14, more comprise step in order to form a gate dielectric material in cover on this insulating barrier semiconductor substrate this first and second the district on.
16. method according to claim 15 more comprises the following steps:
Deposit a polycrystalline silicon material on this gate dielectric material;
The top surface of this polycrystalline silicon material of planarization;
Implant in one first material this polycrystalline silicon material to the first in this first district, and
Deposit one first metal on this polycrystalline silicon material;
Deposit one second metal on this first metal;
Remove this second metal in this second district; And
Carry out second drawing process to covering semiconductor substrate on this insulating barrier.
17. method according to claim 15 more comprises the following steps:
Remove the part of this gate dielectric material in this second district, use making this gate dielectric material have one the 3rd thickness and have one the 4th thickness in this first district in this second district.
18. method according to claim 16, wherein the execution of this second drawing process is to carry out in a smelting furnace 10 minutes with the temperature of 500 degree Celsius, use in this first district this first partly form one first polysilicon metal alloy in, partly form in one second of this first district one second polysilicon metal alloy in, this first part in this second district form one the 3rd polysilicon metal alloy in, and form one the 4th polysilicon metal alloy in one second part in this second district.
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| US56604004P | 2004-04-28 | 2004-04-28 | |
| US60/566,040 | 2004-04-28 | ||
| US11/093,593 | 2005-03-29 |
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| CN110391233B (en) * | 2018-04-17 | 2022-10-14 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN109841561B (en) * | 2019-01-07 | 2021-01-12 | 中国科学院微电子研究所 | SOI device structure and preparation method thereof |
| CN112201656A (en) * | 2020-12-02 | 2021-01-08 | 晶芯成(北京)科技有限公司 | Method for forming CMOS integrated device |
| WO2022178773A1 (en) * | 2021-02-25 | 2022-09-01 | Innoscience (Suzhou) Technology Co., Ltd. | Semiconductor device and method for manufacturing thereof |
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