CN100419835C - Pixel circuit and display apparatus - Google Patents

Abstract

A selecting TFT (20) and a correcting TFT (22) are turned on, thereby causing a data voltage on a data line to be held, as a gate voltage of a driving TFT (24), by a hold capacitor (28). After the selecting TFT (20) is turned off, the voltage of a capacitance line (SC) is caused to rise, thereby turning on the driving TFT (24) to cause a driving current to flow through an organic EL element (26). Here, the correcting TFT (22) is on before the rise of the capacitance line (SC), while it is turned off at a midpoint during the fall of the capacitance line (SC). Accordingly, the capacitance value of the correcting TFT (22) varies during the rise of the gate voltage, and the slope of the rise of the gate voltage of the driving TFT (24) varies, whereby the gate voltage after a fall of the capacitance line (SC) can be set in accordance with the variation of the threshold value of the driving TFT (24). Particularly, the driving TFT (24) and the correcting TFT (22) are disposed such that they are adjacent to each other, whereby their characteristics can be treated as the same and hence the correction can be effectively performed.

Description

Image element circuit and display device

Technical field

The present invention is about comprising organic EL (Electro Luminescence: the image element circuit of luminescence component such as assembly and this organic el element is configured to rectangular display device electroluminescence).

Background technology

The known organic EL panel that the use organic el element is arranged as luminescence component, and its exploitation also makes progress to some extent.In this organic EL panel, organic el element is configured to rectangular, control the luminous of this organic el element individually, show and carry out.Especially in active-matrix formula organic EL panel, each pixel all has the TFT that control shows usefulness, controls the action of this TFT thus, and just each pixel of may command is luminous, so can carry out the very high demonstration of precision.

What Figure 13 was represented is an example of the image element circuit of active-matrix formula organic EL panel.The data line of the data voltage of supply display pixel brightness is connected in the selection TFT 10 of the n raceway groove of gate line via grid, and is connected in the grid of drive TFT 12.In addition, be connected with the end that the other end is connected in the maintenance electric capacity 14 that keeps electric capacity line SC, and keep the grid voltage of drive TFT 12 at the grid of drive TFT 12.

The source electrode of drive TFT 12 is connected in the EL power lead, and drain electrode is connected in the anode of organic el element 16, and the negative electrode of organic el element 16 is connected in cathode power.

This image element circuit is configured to rectangular, makes according to scheduled timing (timing) to be arranged at each horizontal gate line and to become the H current potential, and the selection TFT 10 of this row becomes conducting (ON) state.Under this state, for can be to data line supply data voltage in regular turn, this data voltage be supplied and remains in and keeps electric capacity 14, even if gate line changes the L current potential into, and the voltage when still keeping this.

Then, corresponding this keeps the voltage that kept in electric capacity 14, makes drive TFT 12 produce action, and corresponding drive current flows into cathode power from the EL power lead via organic el element 16, and organic el element 16 is corresponding data voltage and carry out luminous just.

Then, transfer gate line to the H current potential in regular turn, the vision signal of being imported (video signal) is used as data voltage is supplied to pairing pixel in regular turn, be configured to whereby rectangular organic el element 16 just corresponding data voltage carry out luminously, carry out demonstration about vision signal.

But, in this kind image element circuit, be configured to the drive TFT of rectangular image element circuit, if the uneven words of its threshold value voltage, brightness will be inhomogeneous state, and the problem that causes display quality to reduce takes place.So the TFT at the image element circuit that constitutes whole display panel is difficult to its characteristic is become equal state, and is difficult to prevent that the threshold value of its conducting or shutoff from uneven phenomenon not taking place.

So just expectation prevents that the threshold value inequality of drive TFT from impacting for demonstration.

At this,, various schemes (for example special table of Jap.P. 2002-514320 communique) are arranged just from the past at circuit in order to prevent that change impacts to the TFT threshold value.

But, in this scheme, need to be provided with in order to carry out the circuit of threshold value change compensation.So if use sort circuit, the package count that image element circuit just can take place increases, the problem that aperture opening ratio diminishes takes place.In addition, when appending the circuit of compensation usefulness, the problem that the peripheral circuit that generation driving image element circuit is used must change.

Summary of the invention

The invention provides a kind of with simple change, the just effective image element circuit of the threshold value variation in voltage of compensation for drive transistor.

A kind of image element circuit involved in the present invention, it has: an end is connected in data line, and to the selection transistor of control end input select signal; One end is connected in this and selects the transistorized other end, and control end is connected in the correction transistor of the 1st power supply of predetermined voltage; Control end is connected in this and revises the transistorized other end, and an end is connected in the driving transistors as the 2nd power supply of electric current source of supply; One end is connected in the control end of this driving transistors, and the other end is connected in the maintenance electric capacity of Pulse Electric line ball; And utilize the electric current circulate in described driving transistors and luminous luminescence component; At the magnitude of voltage that utilizes the described Pulse Electric line ball of change and in the process of the described driving transistors of conducting, make described correction transistor turns or shutoff, control end voltage during the controlling and driving transistor turns, described driving transistors and described correction transistor formation adjacency state simultaneously whereby.

Moreover preferably, described data line and power lead extend towards vertical scanning direction, and described correction transistor is formed between described data line and the power lead.

Moreover described driving transistors preferably clips described power lead, and is formed at the transistorized opposition side of described correction.

Moreover, preferably, under state with described selection transistor turns, supply makes the data voltage of revising transistor turns to data line, and the voltage of corresponding data voltage is remained on the control end of driving transistors, then, described selection transistor is turn-offed, under this state, the voltage of Pulse Electric line ball is changed, and make the control end voltage shift of driving transistors, make whereby and revise the transistor shutoff, make the driving transistors conducting simultaneously, and the current flowing that makes corresponding data voltage is in driving transistors.

Moreover preferably, described the 1st power supply and the 2nd power supply are same power supply.

Moreover described correction transistor AND gate driving transistors is a p type channel transistor, and preferably, described Pulse Electric line ball is varied to electronegative potential from noble potential after described selection transistor turn-offs.

Another embodiment of the present invention relates to some plurality of pixels and is arranged in rectangular display device, and each pixel has: the display module that corresponding supply electric power moves; The 1st conductive region is connected in data line, and to the selection transistor of control end input select signal; The 1st conductive region is connected in power lead, electric power supply is given the driving transistors of described display module; Control end is connected in the 1st power supply of predetermined voltage, and the 1st conductive region is connected in transistorized the 2nd conductive region of described selection, and the 2nd conductive region is connected in the correction transistor of the control end of described driving transistors; And the 1st electrode is connected in the control end and transistorized the 2nd conductive region of described correction of described driving transistors, and the 2nd electrode is connected in the maintenance electric capacity of Pulse Electric line ball.In addition, the variation in voltage of the corresponding described Pulse Electric line ball of the control end voltage of described driving transistors changes, and change the described control end voltage when corresponding its action threshold value of described correction transistor is controlled described driving transistors and become conducting state corresponding to this.In addition, the described driving transistors of described correction transistor AND gate is made of same conductive-type transistor, and the channel region at least of the described driving transistors of described correction transistor AND gate, by through laser annealing and the semiconductor layer of multiple crystallization constitutes, this channel region is mutually near configuration.

Another embodiment of the present invention is in described image element circuit and display device, the orientation of transistorized orientation of described correction and described driving transistors, the direction of scanning of the linear pulse laser that is shone when being configured to be parallel to described multiple crystallization laser annealing, and the channel region of transistorized channel region of described correction and described driving transistors, its at least a portion all are positioned on the same line that described pulse laser direction of scanning orthogonal directions pulled out.

In the related display device of another embodiment of the present invention, the described driving transistors of described correction transistor AND gate is made of same conductive-type transistor, and at least a portion that adopts the transistorized active layers of described correction is being situated between insulation course and is being formed on the structure of described power lead lower floor position at the interlayer folder.

Moreover among the present invention, in described display device, described the 1st power supply is also used as power lead, also can be formed with the transistorized control end of described correction that is connected in described power lead at the interlayer of transistorized active layers of described correction and described power lead.In addition, described correction transistor also can possess to be had between the line of described data line and described power lead, forms at least with a side line wherein to be the active layers that the state of overlapping extends.

Another embodiment of the present invention is in described display device, and the transistorized channel region of described correction possesses to be had in its orientation, the part of channel width inequality.

As previously discussed, according to the present invention, make in the process of driving transistors conducting at the magnitude of voltage that utilizes change Pulse Electric line ball, transistorized conducting or off state, the control end voltage when coming the controlling and driving transistor turns are whereby revised in change.So, can correspondingly revise transistorized threshold value voltage, different voltages are set in the control end of pairing driving transistors.In addition, because driving transistors and correction transistor are formed adjacency state, thereby can easily driving transistors be made as identical voltage with the transistorized threshold value voltage of correction, and can utilize the threshold value voltage of revising the transistor compensation for drive transistor, and can make the magnitude of current that circulates in luminescence component be uniform state.

Moreover, data line and power lead extend towards vertical scanning direction, and will revise between the line that transistor is formed at data line and power lead, and folder is being situated between power lead and is revising transistorized opposition side formation driving transistors etc., can efficiently dispose whereby, and can increase display module such as luminescence component as much as possible, and realize the display device of high aperture.

For example, in the lower region of power lead, be situated between insulation course and the transistorized active layers of overlay configuration correction can promote the configuration degree of freedom in 1 pixel whereby more at interlayer folder.In addition, when revising transistorized control end (gate electrode) when being connected in power lead, be positioned at the power lead below even if revise transistorized active layers, apply the voltage identical because still can bring in, so can reduce influence to transistor action with power lead to its channel region utilization control.

Moreover, revising transistorized orientation, the part of channel width inequality is set, also can promote the configuration degree of freedom of each transistor in 1 pixel etc. whereby.

Moreover because the variation in voltage of Pulse Electric line ball, driving transistors transfers conducting state to from shutoff, and revises transistorized conducting or off state switching, and its capacitance will change.So, changing in response to revising transistorized threshold value, the grid voltage of driving transistors is just changing the switching that utilizes certain voltage to implement transistorized conducting of correction or shutoff.In addition, the variation of the grid voltage of the driving transistors that the respective pulses pressure-wire changes is caused by revising transistorized capacitance, the transistorized threshold value change of therefore corresponding correction, and grid voltage will produce change.So, owing to, the grid voltage of driving transistors is changed, therefore can integrate as far as possible and revise characteristics of transistor that control is become is easy in the mode of the threshold value change of offsetting driving transistors.

So, when the channel region of revising the transistor AND gate driving transistors, by through laser annealing and the semiconductor layer of multiple crystallization when constituting, to this channel region of major general mutually near disposing, integration characteristic easily whereby.

For example, when adopting and during the active layers of multiple crystallization through laser annealing, the orientation of transistorized orientation and driving transistors will be revised, shine the linear pulse laser direction of scanning when being configured to be parallel to the multiple crystallization laser annealing, whereby can be to the bigger orientation of transistorized electric degree of excursion influence, shine the laser pulse of several times, can reduce each transistor characteristic departure of each pixel.In addition, the position of the channel region by will revising transistorized channel region and described driving transistors, all being arranged at least a portion is positioned on the same line that the orthogonal directions of described pulse laser direction of scanning pulls out, can be because of these 2 transistorized channel regions of same laser beam irradiation, and make its characteristic more approaching.

Moreover, if described the 1st power supply and the 2nd power supply are made as same power supply, just do not need to be provided with individually power lead.

Moreover in the time will revising the transistor AND gate driving transistors and be set at same p type channel transistor, described Pulse Electric line ball by being varied to electronegative potential from noble potential, just can effectively utilize the grid capacitance of p type channel transistor after described selection transistor turn-offs.

Description of drawings

Fig. 1 is the related image element circuit structural map of the embodiment of the invention.

Fig. 2 is in the embodiment of the invention, to the sequential chart of gate lines G L, electric capacity line signal that SC applies.

Fig. 3 is the related grid voltage Vg24 variable condition figure of the embodiment of the invention.

Fig. 4 is in the related image element circuit of the embodiment of the invention, the key diagram of existing electric capacity.

Fig. 5 is that the related pixel planes of the embodiment of the invention is constructed an illustration.

Fig. 6 A is the summary insight structural map along Fig. 5 A-A line.

Fig. 6 B is the summary insight structural map along Fig. 5 B-B line.

Fig. 7 is in the embodiment of the invention, in the time of will revising the polarization of TFT multiple-grid, and the equivalent circuit diagram of average per 1 pixel.

Fig. 8 is layout one a routine general view of realizing equivalent electrical circuit shown in Figure 7.

Fig. 9 is in the embodiment of the invention, the equivalent circuit diagram when the two implements multiple-grid polarization with selection TFT and correction TFT.

Figure 10 is layout one illustration of realizing equivalent electrical circuit shown in Figure 9.

Figure 11 is another illustration of layout shown in Figure 10.

Figure 12 is another routine circuit structure figure of the embodiment of the invention.

Figure 13 is the known pixel circuit structural map.

Symbol description

10 select TFT 12 drive TFT

14 keep electric capacity 16 organic el elements

20 select TFT 22 to revise TFT

24 drive TFT, 26 organic el elements

28 keep electric capacity 30 to suppress leakage current TFT

100 transparent (insulation) substrate, 102 cushions

104 gate insulating films (layer), 106 interlayer dielectrics (layer)

108 complanation insulation courses 110 the 2nd complanation insulation course

120 semiconductor layers, 122 active layers

124 semiconductor layers 262 the 1st electrodes (anode)

264 the 2nd electrodes (negative electrode), 270 luminescence component layers

272 hole transporting layers, 274 luminescent layers

276 electron supplying layer 22-1 the 1st repair TFT

22-2 the 2nd repaiies TFT 20c channel region

20d drain region 20g (20g1,20g2) gate electrode

20s source region 22c channel region

22d drain region 22g (22g1,22g2) gate electrode

22s source region 24c channel region

24d drain region 24e connection electrode

24g grid 24s source region

24w metal wiring 28e capacitance electrode (the 1st electrode)

Cs keeps capacitance CV cathode power

Cw1 stray capacitance Cw2 stray capacitance

DL data line GL gate line

PL power lead SC electric capacity line

Embodiment

Below, at the embodiment of the invention, describe with reference to accompanying drawing.

Fig. 1 is the image element circuit structural map of 1 related pixel of embodiment.At the data line DL that extends towards vertical scanning direction, be connected with the 1st conductive region (drain electrode) that n type raceway groove is selected TFT 20.The grid (control end) of this selection TFT 20 is connected in the gate lines G L that extends towards horizontal scan direction, and the 2nd conductive region (source electrode) is connected in the 1st conductive region (source electrode) of p type raceway groove correction TFT 22.In addition, this selection TFT 20 also can be p type raceway groove, when being p type raceway groove, as long as will be to the polarity (H current potential or L current potential) of the selection signal (signal) of gate lines G L output just opposite driving can.

The control end (grid) of revising TFT 22 is connected in power lead PL (voltage Pvdd), and the 2nd conductive region (drain electrode) then is connected in the control end (grid) of p type raceway groove drive TFT 24.In addition, grid in drive TFT 24 connects an end (the 1st electrode) that keeps electric capacity 28, and the other end of this maintenance electric capacity 28 (the 2nd electrode) then is connected in maintenance electric capacity line (the to call the electric capacity line in the following text) SC with Pulse Electric line ball function of utilizing the pulse-like voltage driving.This electric capacity line SC is the line that extends towards horizontal scan direction as gate lines G L.In addition, other power lead is set, and the grid that will revise TFT 22 is connected in other power lead, just can adjusts arbitrarily and will repair TFT 22 switches to shutoff (OFF) from conducting (ON) sequential.

The 1st conductive region (source electrode) of drive TFT 24 is connected in the power lead PL that extends towards vertical scanning direction, and the 2nd conductive region (drain electrode) then is connected in the anode of organic el element 26.In addition, the negative electrode of organic el element 26 is connected in the cathode power CV of predetermined low voltage.At this, during general case, the negative electrode of organic el element 26 will become the common state of all pixels, and this negative electrode is connected in cathode power CV.

Organic EL panel is rectangular configuration with this image element circuit, and in the sequential of this horizontal vision signal of input, this horizontal gate line will transfer the H current potential to, and the selection TFT 20 of this row just will become conducting state.Whereby, the source electrode of correction TFT 22 just becomes the current potential of data line DL.

At this, to data line DL supply data voltage.This data voltage Vdata for example, shows from the white appliances position to the black appliances position according to about 3 to 5V corresponding to the vision signal person who shows respective pixel.On the other hand, the voltage Pvdd of power lead PL is set in about 0V.So, as conducting selection TFT 20, and, revising TFT 22 and just will be conducting state revising TFT 22 (is source electrode at this) when applying the data voltage Vdata of data line DL, data voltage Vdata just is set in the grid (node Tg 24) of drive TFT 24.In other words, each pixel is write data voltage Vdata during, the voltage with about 3 to 5V is set in the grid of drive TFT 24.In addition, this moment keep the electric capacity line SC of the other end of electric capacity 28 to be set at+8V about.

This data voltage Vdata to the writing after the end of drive TFT 24 grids, just the voltage drop with electric capacity line SC for example is low to moderate-4V.In view of the above, the grid that drives TF T24 will reduce about 12V, and drive TFT 24 is conducting, just be supplied to organic el element 26 and luminous via drive TFT 24 from power lead PL corresponding to the electric current of data voltage.

At this, revise TFT 22 electric capacity line SC from+8V be reduced to-4V about, the voltage of its drain electrode (node Tg 24) just transfers the negative voltage (as described later, this voltage a little difference) of basic-9V to the-7V to from 3 to 5V, and is changed to off state from conducting state.Because corresponding revise TFT 22 conducting from then on and be changed to shutoff, the grid capacitance of revising TFT 22 will change, so this changes in capacitance sequential is promptly revised the threshold value V of TFT 22 _Th22Just with about the grid potential of final drive TFT 24.So, just can utilize and revise the threshold value voltage V that TFT 22 compensates drive TFT 24 _Th24Uneven.

At this, drive TFT 24 is corresponding to supply voltage Pvdd and grid voltage V _G24Difference, i.e. conducting and the pairing drive current that circulates corresponding to Vgs24.This Vgs24 works as greater than the threshold value voltage V that is determined by its TFT characteristic _Th24In, drive TFT 24 electric current that just goes into circulation, amount of drive current is by grid voltage V _G24With threshold value voltage V _Th24Difference and determine.On the other hand, than the threshold value voltage V of difficulty with each drive TFT 24 of most pixels of rectangular configuration on the substrate _Th24Be made as identical state, how many threshold value voltage V has the deviation situation because of location of pixels unavoidably.And because organic el element 26 is luminous to carry out corresponding to the brightness of the amount of drive current of being supplied, so the luminosity of each pixel is just with the threshold value voltage V of corresponding drive TFT 24 _Th24Deviation and change.The capacitance variations of the structure utilization correction TFT 22 that present embodiment is related, and the deviation of compensation luminosity.

Below, the deviation compensation principle at luminosity describes with reference to Fig. 2 and Fig. 3.Figure 3 shows that the magnifying state when the electric capacity line SC shown in the ellipse descends among Fig. 2.At first, as shown in Figure 2, gate lines G L works as in its row (horizontal line) of selection, just becomes initiatively (H) current potential.In this example, selecting TFT 20 be n type raceway groove, gate lines G L be set at the L current potential=-4V about, about H current potential=8V, when selection (initiatively), just be set at 8V.

In addition, the voltage Vsc of electric capacity line SC than select gate lines G L (H current potential) during long slightly during in will be the H current potential.In other words, before gate lines G L becomes the H current potential, just will transfer the H current potential to, after gate lines G L is the L current potential, just transfer the L current potential to.

Gate lines G L be the H current potential during, corresponding to the selection TFT 20 of this gate lines G L with revise TFT 22 with conducting, just will see through and select TFT 20 with correction TFT 22 impose on node Tg 24 the data voltage Vdata of data line DL output this moment.That is, the grid voltage Vg 24 of drive TFT 24 will be set to data voltage Vdata.

Transfer the L current potential at gate lines G L, and after data voltage Vdata write, the voltage of electric capacity line SC descended just, corresponding this situation, the current potential of node Tg 24 just will reduce, and in the near future revise TFT 22 and just will turn-off.The grid voltage V of drive TFT 24 _G24The reduction part of corresponding electric capacity line SC (be the 12V from 8V to-4V in this example) transfers the low voltage that only reduces predetermined voltage than data voltage Vdata to, and the drive current of this voltage of circulation correspondence.

Revise TFT 22 and be arranged at each pixel, and form drive TFT 24 states in abutting connection with this pixel, and via making with drive TFT 24 same steps as.Especially as described later, select TFT 20 when comprising, for example as drive TFT 24 and the active layers of revising TFT 22, employing is implemented laser annealing with amorphous silicon and during polysilicon that multiple crystallization obtained etc., by active layers zone to drive TFT 24 and correction TFT 22, the same laser pulse that multiple crystallization is used is carried out in irradiation simultaneously, just can integrate the TFT characteristic.In addition, the impurity concentration of implantation active layers also can be much at one.So, revise TFT 22 and just form the also roughly the same state of threshold value voltage with drive TFT 24.In addition, be connected in power lead PL (at this Pvdd=0V), therefore along with the voltage V of node Tg 24 because revise the grid of TFT 22 _G24Reduction, and be varied to off state from conducting.

According to this, when electric capacity line SC descended, for the correction TFT 22 of p type channel TFT is changed to off state from conducting, in addition, 24 of drive TFT were changed to conducting state from shutoff.The grid capacitance value Cg of TFT can change with the state of conducting or shutoff.So, the grid voltage V of drive TFT 24 _G24Variation be subjected to the influence that the conducting of 2 TFT 22,24 or off state change.In other words, TFT particularly, when the TFT conducting state, Cg is bigger, and is then less when off state.Because electric capacity will be than when turn-offing when conducting, so the change in voltage state just will be subjected to the influence of capacitance variations.

In other words, transfer shutoff to, its grid capacitance value C if revise TFT 22 from conducting _G22Diminish voltage V _G24The slope α that reduces just will become big.

So, the switched voltage that switches to off state from conducting state as the correction TFT 22 of certain pixel for as the situation of Fig. 3 (switched voltage A) time, the voltage of node Tg 24 (grid voltage V _G24) just changing shown in solid line among the figure.That is, before arriving switched voltage A, grid voltage V _G24Will be from the data voltage V of temporary transient setting _Data, according to the 1st slope α ₁Change (reduction), after arriving switched voltage A, just according to the 2nd slope α ₂Change (reduction).Then, if drive TFT 24 changes into conducting, just according to the 3rd slope α ₃Change (reduction), after the voltage of electric capacity line SC is the L current potential and passes through the scheduled period, voltage V _G24Just be set to and revise voltage VcA.

At this, revise TFT 22 and be changed to the switched voltage of shutoff from conducting, as mentioned above, if revise the supply voltage Pvdd=0 of TFT 22 grid voltages, just by the poor V of its source voltage _Gs22Decide.So switched voltage A, B equal supply voltage Pvdd and add the threshold value voltage V that revises TFT 22 _Th22Voltage (Pvdd+|V after the absolute value _Th22|).

In addition, as the threshold value voltage V that revises TFT 22 _Th22When being lower than [the switched voltage B] of [switched voltage A], grid voltage V _G24Just shown in the dotted line among Fig. 3, change.That is grid voltage V, _G24At data voltage Vdata from temporary transient setting, arrive before the switched voltage B, will be according to the 1st slope α ₁Change (reduction), after arriving, rise just according to the 2nd slope α ₂Change (reduction), if drive TFT 24 conductings, just according to the 3rd slope α ₃Change (reduction), when the voltage of electric capacity line SC is the L current potential and after the scheduled period, voltage V _G24Just be set to and revise voltage VcB.

Mode whereby is for node Tg 24, even if supply identical data voltage Vdata at first, the grid voltage V of last drive TFT 24 _G24Just it is low more to form threshold value voltage, just is set in high more correction voltage Vc.

As above-mentioned, the threshold value voltage V of drive TFT 24 _Th24Corresponding to the threshold value voltage V that revises TFT 22 _Th22So, if the threshold value voltage V of drive TFT 24 _Th24Be [V _Th24A], grid voltage V _G24Just will become corresponding to threshold value voltage V _Th24If the correction voltage VcA of A is [V _Th24B], grid voltage V _G24Just will be set at corresponding to this threshold value voltage V _Th24The correction voltage VcB of B.In this example, threshold value voltage V _Th24With revised grid voltage V _G24Poor, no matter threshold value voltage is V _Th24The situation of A or threshold value voltage are V _Th24The situation of B is identical.In other words, according to the setting of the size of the size of revising TFT 22, supply voltage value Pvdd, drive TFT 24, the capacitance Cs of maintenance electric capacity 28 etc., if data voltage Vdata is identical, even if the threshold value voltage V of drive TFT 24 _Th24According to each pixel and different, threshold value voltage V _Th24With grid voltage V _G24Difference can be certain state, and can get rid of the threshold value voltage V that is subjected to drive TFT 24 _Th24The influence of deviation situation.

At this is can carry out as above-mentioned compensation, preferably, and according to the 2nd slope α ₂Be the 1st slope α ₁2 times mode carry out condition enactment.At this condition enactment, describe according to shown in Figure 3.As shown in Figure 3, when correction TFT 22 is the situation of conducting state, because its capacitance C _G22Greater than turn-offing time so grid voltage V _G24Variation just will suppress the influence that produced because of the pulsed drive change in voltage, slope α ₁Just will diminish.In addition, when correction TFT 22 is the situation of off state, capacitance C _G22Less, bigger because the pulsed drive change in voltage exerts an influence, so slope α ₂Bigger.In addition, because condition enactment is become slope α ₂Be slope α ₁2 times of sizes, so the grid voltage V of pulsed drive voltage when reaching the L current potential _G24The minimizing part, just will form 2 times that revise when being conducting state when TFT 22 is off state.

In other words, comply with the poor Δ V of the threshold value voltage of 2 drive TFT 24 _Th24Equal 2 poor Δ V that revise the threshold value voltage of TFT 22 _Th22Mode, constitute TFT, be made as 2 times by revising the slope of TFT 22 when conducting becomes shutoff, just become Δ V _Th22=Δ V _Th24, 2 poor Δ Vc that revise voltage (VcA, VcB) just satisfy Δ Vc=Δ V _Th24

That is, in Fig. 3, following (i) is to (iv) will all equating:

(i) revise the switched voltage A of TFT 22 and poor (the Δ V of B for 2 _Th22),

(ii) switched voltage B (the slower person of switching sequence: at this is lower voltage), the node Tg 24B of pixel arrives in the switched voltage B therewith, possesses the voltage V of node Tg 24B of pixel of the correction TFT 22 of switched voltage A _G24Poor (Δ V between A _Th22');

(iii) poor (the Δ V of the switched voltage of 2 drive TFT 24 _Th24);

(iv) revise voltage VcA, VcB poor (Δ Vc).

In addition, even under the situation that sampling (sampling) voltage of the voltage that writes as data voltage Vdata changes, because slope no change still, so switched voltage difference Δ V _Th22With revise situation that voltage difference delta Vc equates with no change, and can often compensate the change of threshold value voltage.

Moreover, according to experiment, in the correction voltage of the potential difference (PD) of data voltage behind compensating movement, will be enlarged into 2 times.So, can dwindle the scope of data voltage, and keep the grid voltage of enough drive TFT 24 poor, have the effect of the load that can obtain to make easily the circuit that dwindles supply data voltage.

In addition, as above-mentioned, when the voltage of electric capacity line SC descended, the grid voltage of drive TFT 24 changes can be revised TFT 22 grid capacitance value C especially _G22, drive TFT 24 grid capacitance value C _G24, the capacitance Cs, and the influence of the stray capacitance Cw of distribution that keep electric capacity 28.

About above-mentioned V _G24The mechanism that changes describes according to the electric charge amount of movement.This will keep the capacitance of electric capacity 28 to be made as Cs, the grid capacitance that will revise TFT 22 is made as C _G22, the grid capacitance of drive TFT 24 is made as C _G24, the threshold value voltage that will revise TFT 22 is made as V _Th22, the threshold value voltage of drive TFT 24 is made as V _Th24, and be set at the grid capacitance C that the capacitance Cs=that keeps electric capacity 28 revises TFT 22 _G22

(i) at first, if from drive TFT 24 grid voltage V _G24The state of=Vdata is with electric capacity line SC decline 12V, the voltage V of node Tg 24 _G2412V also should descend.If will only consider the V of this variation _G24Be expressed as V _G24', just become:

V _g24′＝Vdata-12

(ii) be made as C if will revise the grid capacitance of TFT 22 _G22, from then on revise TFT 22 and flow out, and flow into the quantity of electric charge Q that keeps in the electric capacity 28 _F22Just be:

Q _f22＝C _g22×(Vdata-|V _th22|)

At this, in the present embodiment, as above-mentioned C _G22=Cs, the voltage V of node Tg 24 _G24(Vdata-|V only rises _Th22|).So, through considering the voltage V of this rising part _G24" just become

V _g24″＝2Vdata-12-|V _th22|

(iii) then, also flow into electric charge to keeping electric capacity 28 from the grid of drive TFT 24.This quantity of electric charge Q _F24The final grid voltage of drive TFT 24 is made as V _G24, and become

Q _f24＝-C _g24′×(V _g24+|V _th24|)

Wherein, C _G24' drive TFT 24 is the capacitance difference during with conducting when turn-offing, the C that employing is calculated with the MEYER formula of SPICE (SPICE emulator) _G24'=C _G24* 2/3 value.

The (iv) grid voltage V of drive TFT 24 _G24Only to be set at the skew charge Q _F24Flow into and keep the voltage of the deal in the electric capacity 28 just can.So,

V _g24＝V _g24″+Q _f24/C _g22

＝V _g24″-C _g24′(V _g24+|V _th24|)/C _g22

If this formula is rearranged, final V _G24Just be following formula:

(1+C _g24′/C _g22)V _g24

＝2Vdata-12-|V _th22|-(C _g24′/C _g22)|V _th24|

If V _Th22=V _Th24=V _Th, just be following formula:

V _g24＝-|V _th|+(2Vdata-12)/(1+C _g24′/C _g22)

Second on the right of this formula is because according to the fixed value that layout dimension produced, so V _G24By only departing from V _ThEven if, the threshold value voltage V of drive TFT 24 _ThHave and depart from, also can compensate it.

In addition, strictly speaking, also must consider, consider that the words that this situation is set just can at the stray capacitance of distribution.In addition, when supply voltage Pvdd is non-when being the situation of 0V, just can if consider the words of this numerical value.

Moreover, as the threshold value voltage V that revises TFT 22 _Th22, with the threshold value voltage V of drive TFT 24 _Th24During different situation, preferably, its grid voltage V _G24Only be offset the threshold value voltage V of drive TFT 24 _Th24So, if the C in the adjustment following formula _G24'/C _G22Just can.But difficulty is carried out too big adjustment, preferably, and as far as possible according to V _Th22=V _Th24Mode form TFT.

Then, the relation at various electric capacity in the related image element circuit of the embodiment of the invention describes with reference to Fig. 4.The image element circuit of present embodiment also is connected with the grid capacitance C of above-mentioned correction TFT 22 except that keeping capacitor C s _G22, drive TFT 24 grid capacitance C _G24, and various stray capacitances.For example, as shown in Figure 4, between tie point (node) Tg 24 and power lead PL of the drain electrode of correction TFT 22 and the grid of driving transistors 24, have stray capacitance C _W1, between the connecting portion of the source electrode of revising TFT 22 and the source electrode of selection TFT 20 and power lead PL, have stray capacitance C _W2The voltage V of the node Tg 24 of these stray capacitances and Fig. 3 _G24The pass of the slope α that reduces, in Fig. 3, the slope α during from data voltage Vdata arrival switched voltage (A or B) ₁Just can represent by following formula:

α ₁＝Cs/(C _w1+C _w2+Cs+C _g22)

These stray capacitances (C _W1, C _W2, C _G22) all from the state of certain electric charge that charges respectively, make electric charge flow into maintenance capacitor C s, so, grid voltage V _G24The slope α that reduces ₁Just represent with this formula.

Then, in Fig. 3, arrive after the switched voltage, till drive TFT 24 conductings during in the voltage V of node Tg 24 _G24The slope α that reduces ₂Represent with following formula:

α ₂＝Cs/(Cs+C _w1)

Because after arriving switched voltage, revise TFT 22 and will be shutoff, its grid capacitance C _G22, and source electrode and power lead PL between stray capacitance C _W2, will be electrically from keeping electric capacity 28 (capacitance Cs) to cut off.

At this, as mentioned above, be set at α ₂=2 * α ₁So, satisfy Cs=C by complying with _G22-C _W1+ C _W2Mode set the capacitor C s that keeps electric capacity 28, when the voltage of electric capacity line SC descends, switch to shutoff from conducting by revising TFT 22, just can be with the grid voltage V of drive TFT 24 _G24The slope α that descends ₂Be set at α ₁2 times, and can carry out the adequate compensation of the threshold value variation in voltage of drive TFT 24.

Moreover, the slope α after drive TFT 24 conductings shown in Figure 3 ₃, will represent with following formula:

α ₃＝Cs/(Cs+C _w1+C _g24)

C _G24Be the grid capacitance of drive TFT 24 as mentioned above, by conducting drive TFT 24, this capacitor C _G24Be connected in and keep electric capacity 28, the slope α that voltage descends ₃Also will be subjected to this capacitor C _G24Influence.The sequential t of these drive TFT 24 conductings _On244 as mentioned above, not because of the switched voltage of drive TFT 24, also is threshold value voltage V _Th24And different, each pixel is simultaneously.Particularly, utilize correspondence respectively to revise TFT 22 its threshold value voltage V _Th22The sequential of deviation is made as shutoff respectively, in each image element circuit, and grid voltage V _G24To only reduce V separately from supply voltage Pvdd with the sequential that arrives simultaneously _Th24Corresponding part low voltage.

Then, at the pixel layout that possesses this image element circuit (layout), describe with reference to Fig. 5 and 6A figure, 6B figure.Figure 5 shows that the summary planar configuration figure of 1 pixel, Fig. 6 A and Fig. 6 B show the A-A line along Fig. 5, the summary profile construction of B-B line respectively.

On transparent insulation substrate such as glass 100, form cushion 102, form above it and by each TFT active layers that polysilicon constituted and the semiconductor layer (120,124,28e) that constitutes capacitance electrode, in Fig. 5 by shown in the dotted line.In addition, in Fig. 5, be formed at more top of more above-mentioned semiconductor layer, adopt the contour melting point metal material of Cr gate lines G L, electric capacity line SC, and revise TFT 22 grid 22g, and the grid 24g of drive TFT 24 line of meeting each other by actual situation represent.In addition, be formed at top more than semiconductor layer, above-mentioned GL, SC, adopt low-resistance metal material such as Al data line DL, power lead PL, represent with solid line for metal wiring 24w with these with layer.

In layout shown in Figure 5, the formation of each pixel is positioned at the position in the ranks of the formed gate lines G L of horizontal scanning (H) direction along display device, and probably along the position in the ranks of the formed data line DL of vertical scanning (V) direction of display device.In addition, power lead PL be formed at data line DL roughly side by side and towards vertical scanning direction (matrix column direction), in each pixel region, by data line DL, and be connected between the organic el element 26 of pixel of this data line DL.Then, as described later, select TFT 20, revise TFT 22 and keep electric capacity 28 to be disposed between data line DL and the power lead PL, drive TFT and organic el element 26 are disposed between the data line DL of power lead PL and adjacent column.

Select TFT 20 to be formed near the point of crossing of gate lines G L and data line DL.L forms teat towards pixel region from gate lines G, at the interlayer folder gate insulating film 104 that is being situated between, and is covered in the mode across the part of the semiconductor layer 120 that extends along gate lines G L.From then on the outstanding teat of gate lines G L just becomes the gate electrode 20g of TFT 20, and the zone that is covered by this gate electrode 20g of semiconductor layer 120 will become channel region.

The correction TFT 22 that is connected in selection TFT 20 is configured at the state of its orientation along the bearing of trend (vertical scanning direction) of data line DL in the zone by data line DL and power lead PL institute double team.In addition, the active layers of this correction TFT 22 is formed at the lower floor of data line DL to partially overlap the mode of data line DL.This correction TFT 22, and the electric capacity line SC that disposed near next line gate lines G L between, more specifically, keep electric capacity 28 along this electric capacity line SC configuration.In addition, drive TFT 24 folder is being situated between power lead PL and is being disposed at and revises TFT 22 and form the zone and be opposition side zone (organic el element zone 26 sides), and the 24c of channel region at least that constitutes the semiconductor layer 124 of its active layers is configured to as far as possible near the channel region 22c state of revising TFT22 in addition layout.

At this, in this example, select TFT 20 active layers, revise TFT 22 active layers, and keep the capacitance electrode 28e of electric capacity 28 to utilize single semiconductor layer 120 and integrated formation (certainly, can respectively be independent stratum also, and electrically connect according to being scheduled to distribution respectively).

In selecting the formation zone of TFT 20, data line DL and semiconductor layer 120 are connected in running through the contact hole (contact hole) that gate insulating film 104 forms with interlayer dielectric 106.Then, this semiconductor layer 120 is from the lower region (with the contact area of data line DL) of data line DL, extend to and power lead PL position overlapped place along gate lines G L, and from the lap position with the lower floor of power lead PL bearing of trend along power lead PL, extend towards vertical scanning direction.In addition, this semiconductor layer 120 is the place ahead near the contacting of the grid 22g that revises TFT 22 and power lead PL, and from the lower floor position of power lead PL, court is parallel to the direction bending of gate lines G L bearing of trend, and extends towards data line DL.

In addition, in the formation zone of selecting TFT 20, semiconductor layer 120, the impurity that is connected in data line DL (for example: drain region 20d) is implanted zone formation the 1st conductive region, the intrinsic region (intrinsic range) that is overlapped in the inclusion-free implantation of grid 20g will constitute channel region 20c, at the be situated between opposition side of this channel region 20c of folder, constitute through implanting the 2nd conductive region (for example source region 20s) with the impurity of the 1st conductive region same conductivity.

The semiconductor layer 120 that extends from the lower floor of power lead PL towards data line DL, with data line DL intersect once again near (select TFT 20 the 1st conductive region 20d near), will be towards the bending of data line DL bearing of trend, and at least a portion is overlapped in power lead PL and forms the zone (in this example, DL is all overlapped with data line), and with the zone between data line DL and power lead PL, till extending to electric capacity line SC and form the zone towards vertical scanning direction.

Moreover, semiconductor layer 120 constitutes the active layers of revising TFT 22 along the zone of data line DL configuration, folder be situated between this active layers gate insulating film 104 above dispose the gate electrode 22g that revises TFT22, this gate electrode 22g sees through and is formed at the contact hole of interlayer dielectric 106 and is connected in power lead PL.This gate electrode 22g extends towards data line DL from the contact position with power lead PL, and with semiconductor layer 120 (revise TFT22 active layers) position overlapped place bending, bearing of trend towards data line DL extends, and the upper strata of covering semiconductor layer 120, and, be formed at these lower floor according to the mode of segment overlap data line DL and power lead PL.

The zone that is covered by gate electrode 22g of semiconductor layer 120 forms the channel region 22c that does not implement doping impurity that revises TFT 22, folder is being situated between channel region 22c and is selecting the TFT20 side to form through implanting the 1st conductive region with the impurity of this selection TFT 20 different conductivity types (at this, source region 22s for example), forming through implanting with the 1st conductive region 22s in electric capacity line SC side is the 2nd conductive region (is drain region 22d at this) of identical impurity.In addition, data line DL, power lead PL, and this revise the 22c of channel region at least of TFT 22, to overlap with these lines, and be formed at these lower floor, can efficiently will revise TFT 22 whereby and be disposed between data line DL and the power lead PL very in the narrow region.In addition, by gate electrode 22g being disposed at the interlayer of this channel region 22c and data line DL and power lead PL, channel region 22c just will electrically be shielded from data line DL, and the action that can prevent to revise TFT 22 is subjected to putting on the influence of the data-signal of data line DL.In addition, be connected in power lead PL because revise the gate electrode 22g of TFT 22 at least, even if therefore should revise the active layers of TFT 22, special channel region 22c is configured to be overlapped in the state of power lead PL, and voltage that channel region 22c is applied and the situation of cover gate electrode 22g do not have substantial variations.So, just more than half zone of revising the active layers of TFT 22 can be formed at the lower floor of power lead PL, according to this configuration, the aperture opening ratio in 1 pixel promptly helps the formation area of luminous organic el element 26 just can form greatest limit.

Semiconductor layer 120 forms the zone from the 2nd conductive region of revising TFT 22 and extends towards electric capacity line SC, in the position bending that intersects with electric capacity line SC, at the bearing of trend towards electric capacity line SC is horizontal scan direction, be situated between gate insulating film 104 and overlapping mode of electric capacity line SC and folder therebetween implemented patterned process (patterning) according to this, the zone that is overlapped in electric capacity line SC of semiconductor layer 120 just has the function of capacitance electrode (the 1st electrode) 28e, electric capacity line SC (the 2nd electrode) and this capacitance electrode 28e press from both sides Jie's gate insulating film 104 betwixt and the zone that is relative to the configuration just forms and keeps electric capacity 28.

Between the capacitance electrode 28e of the 2nd conductive region 22d that revises TFT 22 and maintenance electric capacity 28, see through the contact hole that is formed at interlayer dielectric 106 and gate insulating film 104, connect metal wiring 24w.This metal wiring 24w forms along the bearing of trend of electric capacity line SC, in the contact hole that is formed at interlayer dielectric 106, is connected with the gate electrode 24g of drive TFT 24.

The formation direction of the gate electrode 24g of drive TFT 24 from the join domain of itself and metal wiring 24w along voluntarily gate lines G L (the figure for direction) up extension, and halfway across the lower floor of power lead PL, the bearing of trend in organic el element 26 sides of power lead PL along this power lead PL forms.

At this, power lead PL will from the contact area of the gate electrode 22g that revises TFT 22 near, crooked near data line DL, near above-mentioned metal wiring 24w, form the zone towards bent circuitous this of organic el element 26 lateral bendings, and it is neighbouring to contact from the semiconductor layer 124 with the active layers that constitutes drive TFT 24, and one-row pixels extends vertical scanning direction down.Then, drive TFT 24 is passed through power lead PL near data line DL side, and forms the compartment (space) of 26 of organic el elements.

Constitute the semiconductor layer 124 of the active layers of drive TFT 24, the zone that is covered by gate electrode 24g is formed with channel region 24c up, be formed with the 1st conductive region (being source region 24s) with the side that is connected of power lead PL, more forming the 2nd conductive region (being drain region 24d) at this with the side that is connected of organic el element 26 at this.Channel region 24c is the intrinsic region of impurity not, is formed at the 1st and the 2nd conductive region (24s and 24d) of its both sides, and then doping is the impurity of same conductivity with above-mentioned correction TFT 22.In addition, the 1st conductive region 24s of drive TFT 24 is in the contact hole that is formed at interlayer dielectric 106 and gate insulating film 104, and PL is connected with power lead.In addition, the 2nd conductive region 24d of drive TFT 24 is in being formed at the contact hole of interlayer dielectric 106 and gate insulating film 104, and for example by being connected for the connection electrode 24e that same material constituted with said power PL etc.

Moreover, shown in Fig. 6 A and Fig. 6 B, on whole of the substrate of cover data line DL, power lead PL, above-mentioned metal wiring 24w, connection electrode 24e, be formed with so that the top flat and complanation insulation course 108 that constitutes by organic resin etc. changed.Then, in this complanation insulation course 108, form in the connection electrode 24e that is connected in above-mentioned drive TFT 24 and to form contact hole in the zone, and see through this contact hole, the 1st electrode 262 (being anode at this) that is formed at the organic el element 26 on this complanation insulation course 108 is connected with connection electrode 24e.In addition, when the situation of connection electrode 24e is not set, the 2nd conductive region 24d in drive TFT 24 forms in the zone, formation run through complanation insulation course 108, interlayer dielectric 106, with the contact hole of gate insulating film 104, directly the 1st electrode 262 with organic el element 26 is connected with the 2nd conductive region 24d.

Shown in Fig. 6 B, organic el element 26 is formed at substrate-side, and for each pixel that is connected in drive TFT 24, between the 1st electrode 262 and the 2nd electrode 264 of pattern separately, is provided with luminescence component layer 270.The 1st electrode 262 can adopt such as ITO transparent conductive metal oxides such as (Indium Tin Oxide) etc. formation, have the function of anode (hole implant electrode) at this.The 2nd electrode 264 is by as work function (Shi Shi Seki numbers such as Al, Ag) less metal material, or the lamination of this metal material and above-mentioned ITO etc. structure constitutes, and has the function of negative electrode (electronics implant electrode) at this.In addition, each pixel is formed the marginal portion of the 1st electrode 262 of pattern separately, utilization be formed on complanation insulation course 108 more the upper strata the 2nd complanation insulation course 110 and cover, to prevent forming on the extremely thin luminescence component layer 270 formed the 2nd electrode 264 262 phenomenons that are short-circuited of the 1st electrode therewith.

Luminescence component layer 270 is 3 layers of structure such as hole transporting layer 272, luminescent layer 274, electron supplying layer 276 in this example.Be not limited only to 3 layers of structure,, can be the individual layer that possesses lighting function, can be bilayer, can be the lamination structure more than 4 layers with employed organic material etc.When luminescence component layer 270 is adopted the situation of multi-ply construction, but holostrome forms the common situation of each pixel, a part or holostrome in also can multilayer, and for example shown in Fig. 6 B, only luminescent layer 274 forms as the 1st electrode 262, sets indivedual patterns according to each pixel.

The organic el element 26 of this structure, in the present embodiment the electric current that is supplied to the 1st electrode 262 via drive TFT 24 from power lead PL and the 2nd electrode 264 between circulation, and, in the luminescence component layer, cause luminous with the briliancy of corresponding current amount.In addition, luminous be by being implanted from the 1st electrode 262 the hole, with the electronics of being implanted from the 2nd electrode 264, combination again in the luminescence component layer, the light emitting molecule that is excited whereby when returning basic unit's state, just carry out luminous and, in this example, recognize light and penetrated the 1st transparent electrode 262 and substrate 100, and penetrate in the outside from substrate.

In the present embodiment, as above-mentioned, press from both sides be situated between power lead PL and above-mentioned correction TFT 22 and drive TFT 24 and be configured to as close as possible layout.The special channel region 22c of TFT 22 and the channel region 24c of drive TFT 24 of revising, at least a portion of its channel region forms mutual state side by side on vertical scanning direction.

In the present embodiment, be formed at the active layers of each TFT in the pixel, starch formed amorphous silicon layers such as CVD for utilizing electricity, the pulse laser (with reference to Fig. 5) that will be shaped as wire (line) is set its length direction at the state of horizontal scan direction for unanimity, in the be separated by preset space length skew and implement irradiation in regular turn of its Width, and use low temperature polycrystalline silicon (LTPS) layer that is obtained through multiple crystallization annealing.The Width of this laser beam of direction of scanning of laser beam, and to make its bearing of trend with data line DL etc. be that vertical scanning direction is consistent.As shown in Figure 5, revising TFT 22 and each channel region 22c, 24c of drive TFT 24, to be configured to its orientation consistent with the bearing of trend of data line DL etc., and promptly unanimity is in the state of the direction of scanning of laser beam.So, be made as less than revising the channel length of TFT 22 by sweep span with drive TFT 24 with laser beam, just can be to arbitrary channel region 22c, 24c, in its orientation, according to mode (channel width dimension), must shine the several times laser beam across raceway groove.Whereby, even if produce under the situation of deviation, because, therefore just can in any pixel, the deviation of energy total amount received in all orientation be dwindled to arbitrary channel region 22c, 24c irradiation several times laser beam at the energy of each laser beam.

Moreover, the polysilicon layer that will form when utilizing so-called laser annealing uses when the situation of the active layers of TFT, just according to the mode that same pulse laser beam is radiated at simultaneously the zone that constitutes the channel region 22c, the 24c that revise TFT 22 and drive TFT 24, with the close mutually configuration of channel region 22c, 24c, whereby can be easily on two TFT, equal formation has the multiple crystallization state of quite big influence to TFT characteristic (special threshold value).

Wherein, 1 irradiation area of pulse laser through being shaped as wire, for example the pulse length direction is the length of 10cm to 30cm, its pulse width is about 300 μ m.Then, the sweep span of the pulse laser of this size promptly, on one side with the irradiation position every 25 μ m shift pulse laser, carries out multiple crystallization with amorphous silicon on one side for example with about 25 μ m.In addition, with revise TFT 22 channel region 22c, with the channel region 24c of drive TFT 24, not only mutually close configuration, and by intersect at the telescopic same straight line of direction of vertical scanning direction in court, at least a portion is configured to state side by side, whereby can be with same pulsed laser irradiation in each channel region 22c, 24c.In addition, the both sides of TFT 22 with drive TFT 24 will be revised, all be set at its channel length at least more than 30 μ m, preferably more than the 40 μ m, pulse laser as above-mentioned size can be complied with aforesaid spacing whereby, vertical scanning direction along pixel scans the channel formation region territory, and the same pulsed laser irradiation of general more than at least 1 that whereby just can be certain is in channel region 22c, the 24c of 2 TFT.

Moreover, the impurity of same conductivity type is shielding (mask) with each grid 22g, 24g, and be implanted in semiconductor layer 120 and 124 simultaneously, because it is very approaching to form the position, therefore just can integrate impurity implantation condition (implant concentration, implant energy etc.), viewpoint also can be revised TFT 22 and with the characteristic of drive TFT 24 it equated thus.

By forming as above-mentioned illustrated layout in the pixel region, at the one-sided zone (the pixel left side of Fig. 5) of the horizontal scan direction of pixel region configuration data line DL, power lead, and TFT20,22, circuit units such as 24, at remaining one-sided (the pixel right side of Fig. 5) configuration organic el element 26, integral body just can form efficient configuration.Particularly,, just can be in each pixel region organic el element 26 be formed bigger as far as possible, and help to promote aperture opening ratio as display device by this layout.In addition, when considering luminescence efficiency and demand brightness, switch elemental area according to each glow color, and when integrating the situation in life-span of each pixel, the area or the layout that also can not must change TFT 20,22,24, maintenance electric capacity 28 etc., the area of organic el element 26 can be only changed easily, and the effect that promotes design efficiency can be reached.

Moreover, layout as shown in Figure 5, the pixel of matrix configuration takes the homochromy location of pixels of every row only to arrange towards the so-called triangle (デ Le ) of horizontal scan direction skew preset space length, when a data line DL when data-signal Vdata being supplied to the situation with color pixel, as shown in Figure 5, data line DL is towards the extension of crawling of matrix column direction, and is connected in the selection TFT 20 of the interconnected same color pixel in the online left and right sides.By adopting this layout, in the next line pixel of pixel shown in Figure 5, what above-mentioned organic el element 26 was opposite with Fig. 5 is disposed on the left of the pixel, and TFT 20,22,24 etc. then is disposed at the pixel right side.Certainly, in the layout of above-mentioned explanation, be not limited only to rounded projections arranged, also can be line spread, in this case, the organic el element of every row, with close not in order to the position of the TFT that controls this organic el element etc. about counter-rotating.

At this, the related correction TFT 22 of present embodiment is changed in its orientation by the width (channel width) of the channel region 22c that semiconductor layer constituted as shown in Figure 5.Particularly, in Fig. 5, TFT 20 (upside among the figure) width is wide more the closer to selecting, keep electric capacity 28 and drive TFT 24 to be connected side (downside among the figure) width narrow with stenosis.The channel width of revising TFT 22 according to this is provided with the part that is different from other at least in its orientation, just can increase the configuration degree of freedom of revising TFT 22.In addition, the characteristic of revising TFT 22 can consider that with the narrowest channel width be benchmark.According to this, by improve revising the configuration degree of freedom of TFT 22, just can effectively carry out the layout etc. of grid 24g of the drive TFT 24 of other circuit unit.In addition, for asking the degree of freedom that can increase configuration, preferably, change forms the width (channel width dimension) of the semiconductor layer of channel region, and also variable other selected the channel width of TFT 20, drive TFT 24 etc., improves the degree of freedom of configuration more.

Moreover, as mentioned above, implement the related pixel circuit configuration of shape example and become rectangular, and constitute display device.Most cases is on glass substrate, formation comprises the pixel region of organic el element, and in its periphery in order to drive the peripheral drive circuit of each pixel, the order that forms is, at first on substrate, form circuit unit and the peripheral drive circuit beyond the organic el element in the pixel region, then, above these circuit units, form organic el element, make base plate for packaging cover glass substrate 100 and adhesion from components side again, and obtain organic EL panel.In addition, the related image element circuit of embodiment is not limited in this organic EL panel, applicable to other various display device.When being applicable to the situation of the circuit (TFT) that in each pixel, forms current drive-type display module and this assembly of control, still can obtain identical effect especially.

Then, in the present embodiment, preferably, select TFT 20, revise the polarization of TFT 22 multiple-grids.This is because especially with the TFT of polysilicon layer as the active layers use, can effectively reduce the event of more leakage current.Leakage current when revising TFT 22, when selecting TFT 20 for shutoff, seeing through these TFT, flows to the electric current of data line DL in the present embodiment, by with these TFT multiple-grid polarization, just can suppress leakage current.As shown in Figure 7, also can only implement the multiple-grid polarization, perhaps also can only will select TFT 20 to implement the multiple-grid polarization revising TFT 22.Certainly, also can as shown in Figure 9 the two be implemented the multiple-grid polarization.

Shown in Figure 7ly will revise the TFT 22 multiple-grids equivalent electrical circuit in when polarization, Figure 8 shows that the planimetric map of an example that realizes this equivalence circuit layout.In the example of Fig. 7, revise TFT 22 and adopt so-called double gated architecture.Particularly, setting between node Tg24 and selection TFT 20: drain electrode is connected in the 1st of node Tg24 and revises TFT 22-1, and is arranged on this 1st two assemblies of revising between TFT 22-1 and the selection TFT 20 such as the 2nd correction TFT 22-2.The the 1st and the 2nd grid of revising TFT 22-1,22-2 all is connected in power lead PL, and the 1st and the 2nd source drain of revising TFT22-1,22-2 electrically is connected in series in to be selected between TFT 20 and the node Tg24.Form this annexation thus, improving drive TFT 24 and the non-conduction leakage current patience of selecting between the TFT 20, and can effectively prevent to remain in the grid voltage V of the drive TFT 24 of maintenance electric capacity 28 _G24Leak into data line DL and take place from the effect of the change of suitable numerical value skew.

Specify, revise TFT 22,, will select the voltage V of the source side of TFT 20 at the tie point of the 1st and the 2nd correction TFT 22-1 and 22-2 by cutting apart _S20(revise the source voltage V of TFT 22-2 _D22-2) with the voltage V of node Tg24 _G24Give dividing potential drop, the voltage V of numerical value therebetween _mJust become the source voltage of the 1st correction TFT 22-1.When the non-conduction leakage current of TFT reduces 1V as the drain source voltage across poles Vds of TFT, just will reduce about 1 figure place.So, to cut apart by revising TFT 22, the 1st drain source voltage across poles Vds that revises TFT22-1 that just drain electrode can be connected in node Tg24 dwindles, and reduces non-conduction leakage current.

In addition, as shown in Figure 7, when will revising TFT 22 multiple-grids when polarization, its conductive region (being drain electrode) at this be connected in drive TFT 24 grid the 1st revise TFT 22-1, its channel region size is necessary, and for example the 2nd to revise the channel region of TFT 22-2 measure-alike with the opposing party.

For example, the 1st channel region size of revising TFT 22-1 is made as the channel region size that is smaller than the 2nd correction TFT 22-2, can reduces the grid capacitance Cg22-1 of the 1st correction TFT 22-1 whereby.When revising TFT 22 when turn-offing, if from then on grid capacitance Cg22 flow in keep electric capacity 28 the quantity of electric charge more for a long time, the current potential of node Tg24 still can be maintained at higher state through for a long time, the voltage decline rate that descends with electric capacity line SC will laten slow.So,, when turn-offing, flow into will reducing of maintenance electric capacity 28, and can reduce the voltage of node Tg24 rapidly from the 1st quantity of electric charge of revising the grid capacitance Cg22-1 of TFT 22-1 by dwindling the channel dimensions of the 1st correction TFT 22.In this case, if with the 1st channel length of revising the channel region of TFT 22-1 be made as L1, channel width be made as W1, with the 2nd channel length of revising the channel region of TFT 22-2 be made as L2, when channel width is made as W2, preferably, satisfy W1 * L1＜W2 * L2.

The 1st revises the channel length L1 of TFT 22-1, under the prerequisite that satisfies the lowest limit degree that reduces non-conduction leakage current requirement, shortens as much as possible, and channel width W1 then in the scope that layout restrictions is allowed, widens as much as possible.The 2nd to revise the channel length L2 of TFT 22-2 long more, though it is slow to make the 2nd grid capacitance Cg22-2 that revises TFT 22-2 from then on flow into the outflow of electric charge of node Tg24, but thus, the conducting resistance of TFT will become greatly, and the data write time will be elongated.So preferably, according to the mode that the value of L2/W2 diminishes, promptly L2 increases deal and just widens deal for width W 2.Viewpoint preferably, satisfies above-mentioned W1 * L1＜W2 * L2 thus.

Shown in Figure 8 as above-mentioned, a routine planar configuration of the layout during with the polarization of correction TFT 22 multiple-grids.In the example of Fig. 8, select the active layers and the active layers of revising TFT 22 of TFT 20, utilize integrally formedly with semi-conductor layer, but for convenience of description, mark legend 122 for constituting the 1st semiconductor layer of revising the active layers of TFT22-1,22-2.This semiconductor layer 122 extends along data line DL and towards adjacent lines direction (below among the figure) as the layout of above-mentioned Fig. 5.

The common lower region at power lead PL of grid 22g (22g1,22g2) of revising TFT 22-1,22-2 is connected with this power lead PL.So, this gate electrode 22g is just from being contacted with the position of power lead PL, DL extends horizontal scan direction towards data line, to constitute the gate electrode 22g2 of the 2nd correction TFT 22-2 across the zone of active layers 122 tops, more extend to the formation zone of data line DL from here, just fold back after just across data line DL, and pierce below the data line DL.Near after piercing data line DL, gate electrode 22g will be according to the mode that covers active layers 122 tops again, along the bearing of trend one-row pixels direction extension down of data line DL, just become the gate electrode 22g1 of the 1st correction TFT 22-1 in this zone that is overlapped in active layers 122.In addition, this 1st gate electrode 22g1 that revises TFT 22-1 is formed at the interlayer of power lead PL and active layers 122, and active layers 122 just electrically intercepts side's formed thereon power lead PL and data line DL.

According to this, gate electrode 22g fold back is become the U-shaped pattern, can cover along data line DL towards vertical scanning direction for example 2 places, semiconductor layer 122 tops of extending whereby, can be at position each self-forming channel region 22c2,22c1 of being covered by gate electrode 22g respectively.Semiconductor layer 122 is from being connected in the 2nd source region 20s side of revising the selection TFT20 of TFT22-2, forms source region 22s1, channel region 22c1 (lower floor of gate electrode 22g1) that drain region 22d2 and the 1st that source region 22s2, channel region 22c2 (lower region of gate electrode 22g2), the 2nd revise TFT 22-2 revises TFT 22-1, and the 1st drain region 22d1 that revises TFT 22-1 in regular turn.Then, the 1st drain region 22d1 that revises TFT 22-1 connects the capacitance electrode 28e (same semi-conductor layer) that keeps electric capacity 28, and is connected with the gate electrode 24g of drive TFT 24 through metal wiring 24w.

If adopt layout shown in Figure 8,, still can do one's utmost to suppress the increase that it is provided with area even if will revise TFT 22 multiple-grids polarization (being [double grid polarization]) at this.

Not only correction TFT 22 shown in Figure 9 is even 20 pages of the above-mentioned selection TFT circuit structure example when implementing multiple-grid polarization situation.In addition, shown in Figure 10 is practical layout one routine planimetric map when adopting circuit structure shown in Figure 9.In the example of Fig. 9, select TFT20-1,20-2 to constitute by 2 that are connected in series in data line DL and select TFT.In addition, select the grid of TFT 20-1,20-2 all to be connected in gate lines G L for 2.

For selecting TFT 20 to implement the multiple-grid polarization, to the single gate configuration layout of the selection TFT 20 shown in Fig. 5 etc., can be corresponding easily just apply simple change.For example shown in Figure 10, the semiconductor layer 120 that constitutes the active layers of selecting TFT 20 is near the formation zone of selecting TFT 20, and forming from data line DL is the shape of U-shaped (ㄈ shape) at power lead PL fold back.So, only to form as shown in phantom in Figure 10 from the pattern of the outstanding gate electrode 20g that forms of gate lines G L, further prolong and be overlapped in from the semiconductor layer 120 of power lead PL fold back the words of layer state and just can.Extend gate electrode 20g according to this, near the side gate lines G L of the semiconductor layer 120 that takes the shape of the letter U near fold back, 2 local gate electrode 20g1,20g2 of forming with the fold back side, and, just can form the double gated that its active layers electrically is connected in series in data line DL easily and select TFT20 by forming channel region 20c1,20c2 in lower floor separately.In addition, again as shown in figure 10,20g more is provided with teat towards horizontal scan direction midway from gate electrode, just can be covered the mode of this teat by the upper strata with the U-shaped base part of active layers, obtains three grid types that 3 active layers are connected in series in data line DL and selects TFT 20.

Another layout example that the multiple-grid utmost point (bigrid) of correction TFT 22 shown in Figure 11 is changed.In the layout of Figure 11, from the gate lines G L that extends towards horizontal scan direction, rise by contact area, towards horizontal scan direction configuring semiconductor layer 120, give prominence to formation 2 gate electrode 20g1,20g2 side by side towards this semiconductor layer 120 along this gate lines G L with data line DL.In this example, the bearing of trend that channel region 20c1, the 20c2 of multigrid selection TFT 20 is disposed at gate lines G L side by side is a horizontal scan direction.

As above-mentioned Fig. 9 and Figure 10 or shown in Figure 11, not only revise TFT 22, even will select the polarization of TFT 20 multiple-grids, whereby can the non-conduction leakage current of more effective inhibition.

Figure 12 shows that another circuit structure example.In the equivalent electrical circuit structure of average 1 pixel shown in Figure 12, at one end (the 1st conductive region: for example drain electrode) is connected between the 1st conductive region (for example source electrode) of the other end (the 2nd conductive region: for example source electrode) of the selection TFT 20 of data line DL and above-mentioned correction TFT 22, has more to have the inhibition leakage current TFT 30 that grid is connected in electric capacity line SC.This suppresses leakage current TFT 30 is n channel-types, and TFT 22 is opposite polarity with correction.

Just conducting when this inhibition leakage current TFT 30 electric capacity line SC are the H current potential is just turn-offed when being the L current potential.So, gate lines G L conducting during the H current potential, aspect the grid that is written into drive TFT 24 about data voltage Vdata with data line DL, all unlikely generation problem.In addition, after data writes end,, thereby turn-off because electric capacity line SC is reduced to the L current potential.That is, when electric capacity line SC decline, when the grid potential of drive TFT 24 transferred the situation of low-voltage to, this inhibition leakage current TFT 30 just kept off state, just can effectively suppress the leakage current of the grid circulation from data line DL at this moment towards drive TFT 24.So, can promote the even situation of each glorious degrees of the some pixels in the display device more.In addition, in structure shown in Figure 12, though can just can reduce non-conduction leakage current more, but the increase of circuit unit will cause aperture opening ratio to descend more with revising the polarization of TFT 22 multiple-grids.So, get greatest limit at aperture opening ratio, and can reach in the uniform scope of each pixel glorious degrees, it is comparatively suitable whether decision further will revise the polarization of TFT multiple-grid.

Utilizability on the industry

Can utilize display unit that has display module in each pixel etc.

Claims (19)

1. image element circuit is characterized in that it has:

One end is connected in data line, and by the selection transistor of control end input select signal;

One end is connected in the transistorized other end of described selection, and control end is connected in the correction transistor of the 1st power supply of predetermined voltage;

Control end is connected in the transistorized other end of described correction, and an end is connected in the driving transistors as the 2nd power supply of electric current source of supply;

One end is connected in the control end of described driving transistors, and the other end is connected in the maintenance electric capacity of Pulse Electric line ball; And

Utilization circulates in the electric current of described driving transistors and luminous luminescence component;

At the magnitude of voltage that utilizes the described Pulse Electric line ball of change and in the process of the above-mentioned driving transistors of conducting, make described correction transistor turns or shutoff, control end voltage when controlling described driving transistors conducting whereby, described driving transistors and described correction transistor abut to form simultaneously.

2. image element circuit according to claim 1 is characterized in that,

Under state with described selection transistor turns, supply makes the data voltage of revising transistor turns to data line, and the voltage of corresponding data voltage remained on the control end of driving transistors, then, described selection transistor is turn-offed, under this state, the voltage of Pulse Electric line ball is changed, and make the control end voltage shift of driving transistors, make whereby and revise the transistor shutoff, make the driving transistors conducting simultaneously, and the current flowing that makes corresponding data voltage is in driving transistors.

3. image element circuit according to claim 1 is characterized in that, described the 1st power supply and the 2nd power supply are same power supply.

4. image element circuit according to claim 1 is characterized in that, described correction transistor AND gate driving transistors is the p channel transistor, and described Pulse Electric line ball is varied to electronegative potential from noble potential after described selection transistor turn-offs.

5. image element circuit according to claim 1 is characterized in that, the active layers of described correction transistor and described driving transistors constitutes by the many crystal semiconductors that obtained through the multiple crystallization laser annealing,

The orientation of transistorized orientation of described correction and described driving transistors, the direction of scanning of the linear pulse laser that is shone when being configured to be parallel to described multiple crystallization laser annealing, and the channel region of transistorized channel region of described correction and described driving transistors, its at least a portion all are positioned on the crisscross same straight line of pulling out in described pulse laser direction of scanning.

6. image element circuit according to claim 1 is characterized in that described data line and power lead extend towards vertical scanning direction, and described correction transistor is formed between described data line and the power lead.

7. image element circuit according to claim 6 is characterized in that, described driving transistors presss from both sides the described power lead that is being situated between, and is formed at the transistorized opposition side of described correction.

8. image element circuit according to claim 6, it is characterized in that, under state with described selection transistor turns, supply makes the data voltage of revising transistor turns to data line, and the voltage of corresponding data voltage is remained on the control end of driving transistors, then, described selection transistor is turn-offed, under this state, the voltage of Pulse Electric line ball is changed, and make the control end voltage shift of driving transistors, make whereby and revise the transistor shutoff, make the driving transistors conducting simultaneously, and the current flowing that makes corresponding data voltage is in driving transistors.

9. image element circuit according to claim 6 is characterized in that, described the 1st power supply and the 2nd power supply are same power supply.

10. image element circuit according to claim 6 is characterized in that, described correction transistor AND gate driving transistors p channel transistor, and described Pulse Electric line ball is varied to electronegative potential from noble potential after described selection transistor turn-offs.

11. image element circuit according to claim 6 is characterized in that, the active layers of described correction transistor and described driving transistors constitutes by the many crystal semiconductors that obtained through the multiple crystallization laser annealing,

The orientation of transistorized orientation of described correction and described driving transistors, the direction of scanning of the linear pulse laser that is shone when being configured to be parallel to described multiple crystallization laser annealing, and the channel region of transistorized channel region of described correction and described driving transistors, its at least a portion all are positioned on the crisscross same straight line of pulling out in described pulse laser direction of scanning.

Be arranged in rectangular display device 12. a display device, described display device are plurality of pixels, it is characterized in that, each pixel has:

The display module that the corresponding electric power of being supplied moves;

The 1st conductive region is connected in data line, and to the selection transistor of control end input select signal;

The 1st conductive region is connected in power lead, electric power supply is given the driving transistors of described display module;

Control end is connected in the 1st power supply of predetermined voltage, and the 1st conductive region is connected in transistorized the 2nd conductive region of described selection, and the 2nd conductive region is connected in the correction transistor of the control end of described driving transistors; And,

The 1st electrode is connected in the control end and transistorized the 2nd conductive region of described correction of described driving transistors, and the 2nd electrode is connected in the maintenance electric capacity of Pulse Electric line ball;

Corresponding its action threshold value of described correction transistor, and the variation in voltage of corresponding described Pulse Electric line ball change the control end voltage of described driving transistors, in view of the above and the described control end voltage of control when described driving transistors is conducting state;

The described driving transistors of described correction transistor AND gate is made of same conductive-type transistor;

And the channel region at least of the described driving transistors of described correction transistor AND gate, by through laser annealing and the semiconductor layer of multiple crystallization constitutes, this channel region is mutually near configuration.

13. display device according to claim 12, it is characterized in that, the orientation of transistorized orientation of described correction and described driving transistors, the direction of scanning of the linear pulse laser that is shone when being configured to be parallel to described multiple crystallization laser annealing, and the channel region of transistorized channel region of described correction and described driving transistors, its at least a portion all are positioned on the same straight line that described pulse laser direction of scanning orthogonal directions pulled out.

14. display device according to claim 12 is characterized in that, the transistorized channel region of described correction possesses to be had in its orientation, the part of channel width inequality.

15. display device according to claim 12 is characterized in that, described correction transistor possesses to be had between the line of described data line and described power lead, extends in partly overlapping mode with a side line wherein at least and the active layers that forms.

Be arranged in rectangular display device 16. a display device, described display device are plurality of pixels, it is characterized in that, each pixel has:

The display module that corresponding supply electric power moves;

The 1st conductive region is connected in data line, and to the selection transistor of control end input select signal;

The 1st conductive region is connected in power lead, electric power supply is given the driving transistors of described display module;

Control end is connected in the 1st power supply of predetermined voltage, and the 1st conductive region is connected in transistorized the 2nd conductive region of described selection, and the 2nd conductive region is connected in the correction transistor of the control end of described driving transistors; And,

The 1st electrode is connected in the control end and transistorized the 2nd conductive region of described correction of described driving transistors, and the 2nd electrode is connected in the maintenance electric capacity of Pulse Electric line ball;

Corresponding its action threshold value of described correction transistor, and the variation in voltage of corresponding described Pulse Electric line ball change the control end voltage of described driving transistors, in view of the above and the described control end voltage of control when described driving transistors is conducting state;

The described driving transistors of described correction transistor AND gate is made of same conductive-type transistor;

And at least a portion of the transistorized active layers of described correction is pressed from both sides the lower floor position that is being situated between insulation course and is being formed at described power lead at interlayer.

17. display device according to claim 16 is characterized in that,

Described the 1st power supply dual-purpose power lead,

Interlayer at transistorized active layers of described correction and described power lead is formed with the transistorized control end of described correction that is connected in described power lead.

18. display device according to claim 16 is characterized in that,

The transistorized channel region of described correction possesses to be had in its orientation, the part of channel width inequality.

19. display device according to claim 16 is characterized in that,

Described correction transistor possesses to be had between the line of described data line and described power lead, extends in partly overlapping mode with a side line wherein at least and the active layers that forms.

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