CN100416858C - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
CN100416858C
CN100416858C CNB2005100651357A CN200510065135A CN100416858C CN 100416858 C CN100416858 C CN 100416858C CN B2005100651357 A CNB2005100651357 A CN B2005100651357A CN 200510065135 A CN200510065135 A CN 200510065135A CN 100416858 C CN100416858 C CN 100416858C
Authority
CN
China
Prior art keywords
mentioned
interarea
type
groove
grid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB2005100651357A
Other languages
Chinese (zh)
Other versions
CN1665034A (en
Inventor
中村勝光
楠茂
中村秀城
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to CNB2005100651357A priority Critical patent/CN100416858C/en
Publication of CN1665034A publication Critical patent/CN1665034A/en
Application granted granted Critical
Publication of CN100416858C publication Critical patent/CN100416858C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present invention relates to a semiconductor device which comprises semiconductor substrates having a first main face and a second main face, and an element of an insulated gate type field effect transistor, wherein the first main face and the second main face are mutually opposite; the element of an insulated gate type field effect transistor has an insulated gate structure on the first main face side and has a main current flowing between the first main face and the second main face. The element has an impurity diffusion layer (8) which is formed on the second main face and has an impurity activation ratio lower than 50%.

Description

Semiconductor device
The application is that application number is dividing an application of 01809999.8 original bill application, and the applying date of this original bill application is February 1 calendar year 2001.
Technical field
The present invention relates to semiconductor device and manufacture method thereof, relate to the collector structure and the manufacture method thereof at the Semiconductor substrate back side in the filming of Semiconductor substrate.
Background technology
In the field of control,, therefore, require to suppress heating, the i.e. device property of suppression loss because its handled electric current is also very big above the high-voltage semiconductor device of hundreds of V voltages.Also have, as the type of drive of the grid of controlling those electric current and voltages, hope is that drive circuit is little, at the little voltage driven element of the loss at drive circuit place.
In recent years, because above-mentioned reason, as can using driven, the little device of loss in this field, igbt, promptly IGBT is just becoming main flow.The structure of this IGBT the impurity concentration that reduces the transistorized leakage of MOS (Metal-oxide-semicondutor), keep withstand voltage in, adopted and can regard the structure of diode as in order to reduce ohmic leakage leaking side.
In such IGBT, carry out bipolar operation in order to make diode, in this application, the source of the MOS transistor of IGBT is called emitter, will leak side and be called the collector electrode side.
In IGBT as voltage driven element, generally be the voltage that between collector electrode and emitter, applies hundreds of V, this voltage is by the grid voltage control of ± number V～tens of V.Also have, IGBT uses as phase inverter, when grid is in conducting state, though the voltage between collector emitter is lower, there is big electric current to flow through, when grid is in the state of disconnection, though do not have electric current to flow through, the voltage increases between collector emitter.
Usually, owing to be the work of under above-mentioned pattern, carrying out IGBT, the switching loss when its loss can be divided into the fixed loss of the current/voltage product under conducting state and conducting state with off state switching transition.Because the current/voltage product under the off state is very little, can ignore.
On the other hand, for example under the abnormality of load short circuits situation etc., the puncture that prevents device also is important.In this case, still apply the supply voltage of hundreds of V between collector emitter, gate turn-on flows through big electric current.
Be connected in series among the IGBT of structure having MOS transistor and diode, by the saturation current restriction maximum current of MOS transistor.Therefore, when above-mentioned short circuit, the electric current restriction is also worked, and can prevent to cause because of constant time heating the puncture of element.
Figure 75 is the profile that the structure of conventional semiconductor device roughly is shown.Have mutually in opposite directions the 1st interarea and the Semiconductor substrate of the 2nd interarea on form IGBT.At n -The 1st interarea side of silicon layer 101 forms P type tagma 102, forms n type emitter region 103 and P on the 1st interarea in this P type tagma 102 + Impurity diffusion zone 106.
With this n type emitter region 103 of break-through and p type tagma 102, arrive n -The mode of silicon layer 101 forms grid groove 101a.With along the mode of this grid, form gate insulating film 104a, and form gate electrode 105a with the mode in the groove 101a to imbed grid with the inner surface of groove 101a.On the upper surface of gate electrode 105a, form the dielectric film 122A that constitutes by oxide-film.
By this n -Silicon layer 101, n type emitter region 103 and gate electrode 105a constitute n - Silicon layer 101 as leak, n type emitter region 103 is as the insulated-gate type field effect transistor (being MOS transistor here) in source.
On the 1st interarea, form dielectric film 109 and 122B, on this dielectric film 109,122B, form and arrive n type emitter region 103 and P +The contact hole 109a on the surface of impurity diffusion zone 106.On the upper surface of dielectric film 109,122B and contact hole 109a inner surface, form barrier metal layer 110, on the contact site of barrier metal layer 110 and Semiconductor substrate, form silicide layer 121a.On the 1st interarea, form emitter electrode 111 by this barrier metal layer 110 and silicide layer 121a, so as with n type emitter region 103 and p + Impurity diffusion zone 106 is electrically connected.
At n -Form n type buffering area 107 and p type collector region 108 on the 2nd interarea of silicon layer 101.For example the collector electrode 112 that is made of aluminium compound is electrically connected with this p type collector region.
In such conventional semiconductor device, the thickness t of Semiconductor substrate 2Being 300～400 μ m, is 500 μ m in some cases.
Secondly, the manufacture method of the conventional semiconductor device shown in Figure 75 is described.
Figure 76～Figure 85 is the summary section that the manufacture method of conventional semiconductor device is shown by process sequence.With reference to Figure 76, at first, becoming on the p N-type semiconductor N substrate 108 of collector region with epitaxial growth method formation n type buffering area 107 and n -Silicon layer 101.At this n -Form p type tagma 102 on the 1st interarea of silicon layer 101, on it, form the dielectric film 131 that for example constitutes by silicon oxide film.
With reference to Figure 77, this dielectric film 131 is graphical with common photomechanical process technology and lithographic technique.As mask ion injection etc. is carried out in p type tagma 102 with this graphical dielectric film 131, formed n type emitter region 103.Then, remove dielectric film 131.
With reference to Figure 78, after forming heat oxide film 132 and CVD (chemical vapor deposition) oxide-film 133 on whole of the 1st interarea successively, that it is graphical.As mask, Semiconductor substrate is implemented anisotropic etching with this graphical heat oxide film 132 and CVD oxide-film 133.Thus, arrive n with break-through n type emitter region 103 and p type tagma 102 -The mode of silicon layer 101 forms grid groove 101a.
With reference to Figure 79, carry out the processing of isotropism plasma etching and sacrificial oxidation etc.Thus, make grid become circle, and make the concavo-convex planarization of grid with the sidewall of groove 101a with peristome and the bottom of groove 101a.And then, to form sacrificial oxidation film 132a with the mode of the inner surface of groove 101a, make it and heat oxide film 132 integrated along grid.Then, remove CVD oxide-film 133, heat oxide film 132 and sacrificial oxidation film 132a.
With reference to Figure 80, the surface of Semiconductor substrate is exposed by removing above-mentioned oxide-film.
With reference to Figure 81, grid with the inner surface of groove 101a on and form the gate insulating film 104a that constitutes by silicon oxide layer etc. on the 1st interarea of Semiconductor substrate.And then, on the 1st interarea of Semiconductor substrate, form the conductive layer 105 that imports the formations such as polysilicon of phosphorus with high concentration, so that conductive layer 105 is imbedded grid with in the groove 101a.After this, remove this conductive layer 105, till the upper face of gate insulating film 104a exposes.
With reference to Figure 82, thus, with the mode in the groove 101a conductive layer 105 is remained to imbed grid, form gate electrode 105a.Then, the upper surface at gate electrode 105a forms dielectric film 122A.
With reference to Figure 83, for example form the dielectric film 109 that constitutes by silicate glass successively and the dielectric film 122B that constitutes by the CVD oxide-film after, it is graphical, offer contact hole 109a.
With reference to Figure 84, on whole surface, form barrier metal layer 110.Then, by implementing mild annealing, at the contact portion formation silicide layer 121a of barrier metal layer 110 with Semiconductor substrate.On barrier metal layer 110, form emitter electrode 111.
With reference to Figure 85, grind and remove p type collector region 108.
Then, on the 2nd interarea,, finish the conventional semiconductor device shown in Figure 75 to form collector electrode 112 with p type collector region 108 ways of connecting.
In the structure shown in Figure 75, owing on the 2nd interarea of Semiconductor substrate, there is the p type collector region 108 of thick high concentration, when break-over of device, uprise from the injection efficiency in the hole of collector electrode side (the 2nd interarea side).Thus, can realize low conducting voltageization (low R ONChange).
But in the structure shown in Figure 75, the principal current that flows through when break-over of device is very big, and saturation current increases, consequently, can not be by device self Control current, be difficult to guarantee and improve at the non-loaded down puncture capacity when device is worked.
Also have, in the structure shown in Figure 75, owing on the 2nd interarea, there is the p type collector region 108 of thick high concentration, when break-over of device, very high from the injection efficiency in the hole of collector electrode side (the 2nd interarea side).Therefore, the voltage V between collector electrode-emitter CESwitching loss when (carrying out under the situation of switch) under the high situation disconnecting under high voltage increases.
And then, in the manufacture method shown in Figure 76～Figure 85, just there are p type collector region 108 and n type buffering area 107 in the 2nd interarea side from the initial of technology, and, n type buffering area 107 and n -Silicon layer 101 is formed by epitaxial growth.Therefore, cause the high price of substrate to be formatted, and the degree of freedom of substrate thickness is also restricted.
Summary of the invention
One object of the present invention is to provide: realize low conducting voltageization, when guaranteeing to puncture capacity, can be reduced in the semiconductor device and the manufacture method thereof of the switching loss of high-voltage side.
Also have, another object of the present invention is to provides: can prevent to bring semiconductor device and manufacture method thereof to the baneful influence of device property because of the change in the technology.
Also have, another purpose of the present invention is to provide: the degree of freedom restriction of substrate thickness tails off, and is suitable for the manufacture method of the semiconductor device of low price.
The semiconductor device of one aspect of the present invention possesses: have mutually in opposite directions the 1st interarea and the Semiconductor substrate of the 2nd interarea; And be included in the 1st interarea side and have insulated gate structure, and between the 1st interarea and the 2nd interarea, flow through the element of the insulated-gate type field effect transistor portion of principal current, the thickness (n of Semiconductor substrate -The thickness of drift layer) be more than the 50 μ m, below the 250 μ m.
In addition, in this application, the thickness of Semiconductor substrate has identical meaning with the thickness of drift layer.
Semiconductor device according to one aspect of the present invention, because the thickness of Semiconductor substrate is thinner than conventional example, the resistance components of thickness direction tails off, and, in order to obtain low conducting voltageization, on the 1st interarea, possess the insulated-gate type field effect transistor structure, thereby can realize low conducting voltageization (low R ONChange).
Also have, because the thickness of Semiconductor substrate is more than the 50 μ m, below the 250 μ m, and, having had both the isolated-gate field effect transistor (IGFET) structure that can improve the puncture capacity, in the puncture capacity in the time can guaranteeing device work, can reduce the wastage.
Under the situation of thickness less than 50 μ m of Semiconductor substrate, because the thin excessively puncture capacity when being difficult to guarantee device work.Also have, when the thickness of Semiconductor substrate surpasses 250 μ m, V ONJust uprise.Thus, fixed loss E DCBecome big, reducing the wastage becomes very difficult.
In aspect above-mentioned one, ideal situation is: insulated-gate type field effect transistor portion has the source diffused layer of the 1st conductivity type and leaks diffusion layer, the source diffused layer of the 1st conductivity type be formed on the 1st interarea and also with leak diffusion layer phase to, the tagma of the 2nd conductivity type in clamping therebetween.
The present invention is very suitable for having the element of such insulated-gate type field effect transistor portion.
In aspect above-mentioned one, ideal situation is: also possess the impurity diffusion layer that is formed on the 2nd conductivity type on the 2nd interarea, the impurity surface concentration on the 2nd interarea of impurity diffusion layer is 5 * 10 15Cm -3More than.
Thus, can suppress V ON, V CESAging, can prevent because of its aging baneful influence that device property is brought.
In aspect above-mentioned one, ideal situation is: the diffusion depth apart from the 2nd interarea of impurity diffusion layer is below the 1 μ m.
Like this, because impurity diffusion layer forms thinlyyer, can make the reduced thickness of Semiconductor substrate.
In aspect above-mentioned one, ideal situation is: the impurity activation rate in impurity diffusion layer is below 50%.
Thus, can prevent the baneful influence that the change because of process conditions brings to device property.
In aspect above-mentioned one, ideal situation is: impurity diffusion layer constitutes the pn knot with the leakage diffusion layer, leak diffusion layer with zone that impurity diffusion layer is connected on have the 1st high concentration region of the 1st conductivity type, the 1st high concentration region has the impurity concentration peak value of the following concentration of impurity concentration peak value of impurity diffusion layer.
Thus, with the main junction leakage characteristic of minimizing, when rising is withstand voltage, make the I when disconnection CSmear electric current minimizing, switching loss E in the waveform OffReduce.Also have, have inhibition because of V CEIncrease cause E OffThe effect that changes.
In aspect above-mentioned one, ideal situation is: the 1st high concentration region is positioned at apart from the scope of the following degree of depth of the 2nd interarea 2 μ m.
Like this, because the 1st high concentration region can form shallowly, the thickness of Semiconductor substrate can attenuate.
In aspect above-mentioned one, ideal situation is: form the grid groove on the 1st interarea of Semiconductor substrate, the gate electrode of insulated-gate type field effect transistor portion is imbedded grid with in the groove, and the upper surface of gate electrode is used in the groove outstanding from grid.
Like this, the present invention is suitable for groove MOS grid type element.
In aspect above-mentioned one, ideal situation is: form the grid groove on the 1st interarea of Semiconductor substrate, the gate electrode of insulated-gate type field effect transistor portion is embedded in the grid usefulness groove, and the upper surface of gate electrode will retreat in the groove under the 1st interarea.
Like this, the present invention is suitable for groove MOS grid type element.
In aspect above-mentioned one, ideal situation is: also possess the source electrode that is electrically connected with source diffused layer on the 1st interarea.
Thus, can adjust the current potential of source diffused layer by the source electrode.
In aspect above-mentioned one, ideal situation is: Semiconductor substrate has source electrode groove on the 1st interarea, and the conductive layer that is electrically connected with the source electrode is embedded in the source electrode with in the groove.
Like this, the groove of the conductive layer by the landfill source electric potential is set can reduce effective grid width, thereby has the effect that suppresses saturation current.Also have,, when device carries out switch under no-load condition, keep electric current arbitrarily in the time that can all grow than conventional example by means of the effect that reduces saturation current.That is, have the saturation current of suppression device, and improve the effect of puncture capacity.Can also be suppressed under the no-load condition carry out switch the time vibration.
In aspect above-mentioned one, ideal situation is: multiple source lateral electrode groove is set, imbeds the multiple source lateral electrode with each of the conductive layer in the groove by integrated formation of single layer.
Thus, can the integrated multiple source lateral electrode of imbedding of enough single layers use in the groove.
In aspect above-mentioned one, ideal situation is: the source electrode is formed on the 1st interarea that groove is not set, and the 2nd high concentration region that the 2nd conductivity type is set on the 1st interarea of groove be not set, and makes it possible to be electrically connected with the source electrode.
Like this, by guaranteeing not to be provided with the part broad of groove, effective grid width is reduced.
In the semiconductor device in another aspect of this invention, possess: have mutually in opposite directions the 1st interarea and the Semiconductor substrate of the 2nd interarea; And has insulated gate structure in the 1st interarea side, and, be included in the element that flows through the insulated-gate type field effect transistor portion of principal current between the 1st interarea and the 2nd interarea, this element have be formed on the 2nd interarea, the impurity activation rate is the impurity diffusion layer below 50%.
Semiconductor device according to a further aspect in the invention can prevent the baneful influence to device property that the change because of process conditions causes.
When the impurity activation rate of impurity diffusion layer surpasses 50%, V ONChange to the collector layer injection rate becomes big, and, because V ONChange the change of ion injection rate is become big, the designs difficulty that also becomes.
Above-mentioned on the other hand in, ideal situation is: the impurity surface concentration on the 2nd interarea of impurity diffusion layer is 5 * 10 15Cm -3More than.
Thus, can suppress V ON, V CESAging, can prevent because of its aging baneful influence device property.
Above-mentioned on the other hand in, ideal situation is: the diffusion depth apart from the 2nd interarea of impurity diffusion layer is below the 1 μ m.
Like this, because impurity diffusion layer forms thinlyyer, can make the reduced thickness of Semiconductor substrate.
Above-mentioned on the other hand in, ideal situation is: the leakage diffusion layer of impurity diffusion layer and insulated-gate type field effect transistor portion constitutes the pn knot, leak diffusion layer with zone that impurity diffusion layer is connected on have the 1st high concentration region of the 1st conductivity type, the 1st high concentration region has the impurity concentration peak value of the following concentration of impurity concentration peak value of impurity diffusion layer.
Thus, when reducing main junction leakage characteristic, rising is withstand voltage, make smear electric current minimizing, switching loss E in the Ic waveform when disconnecting OFFReduce.Also have, have inhibition because of V CEIncrease cause E OFFThe effect that changes.
Above-mentioned on the other hand in, ideal situation is: the 1st high concentration region is positioned at the scope apart from the 2nd interarea 2 μ m following degree of depth.
Like this, because can simple formation the 1st high concentration region, the thickness of Semiconductor substrate can attenuate.
Above-mentioned on the other hand in, ideal situation is: form the grid groove on the 1st interarea of Semiconductor substrate, the gate electrode of insulated-gate type field effect transistor portion is embedded in grid with in the groove, the upper surface of gate electrode from grid with outstanding in the groove.
Like this, the present invention is applicable in the groove MOS grid type element.
Above-mentioned on the other hand in, ideal situation is: grid is formed on groove on the 1st interarea of Semiconductor substrate, the gate electrode of insulated-gate type field effect transistor portion is embedded in grid with in the groove, the upper surface of gate electrode is stepped back the 2nd interarea side by the 1st interarea.
Like this, the present invention is applicable to the element of groove MOS grid type.
Above-mentioned on the other hand in, ideal situation is: in the 1st interarea side, also possess the source electrode that is electrically connected with the source diffused layer of insulated-gate type field effect transistor portion.
Thus, can adjust the current potential of source diffused layer by the source electrode.
Above-mentioned on the other hand in, ideal situation is: Semiconductor substrate has source electrode groove on the 1st interarea, the conductive layer that is electrically connected with the source electrode is embedded in the source electrode with in the groove.
Like this, because the groove of the conductive layer by being provided with the landfill source electric potential can reduce effective grid width, thereby has the effect that suppresses saturation current.Also have,, when device carries out switch under no-load condition, can keep electric current arbitrarily in the long time than conventional example by reducing the effect of saturation current.That is the effect that, has the saturation current and the raising puncture capacity of suppression device.And then, can be suppressed at the vibration when carrying out switch under the no-load condition.
Above-mentioned on the other hand in, ideal situation is: multiple source lateral electrode groove is set, by the integrated landfill multiple source lateral electrode that forms of single layer with each of the conductive layer of groove.
Thus, become possibility with the single integrated landfill multiple source lateral electrode of layer with groove.
Above-mentioned on the other hand in, ideal situation is: the source electrode is formed on the 1st interarea that groove is not set, and the 2nd conductivity type the 2nd high concentration region is set not being provided with on the 1st interarea of groove, so that be electrically connected with the source electrode.
Like this, by guaranteeing not to be provided with the part broad of groove, can reduce effective grid width.The manufacture method of semiconductor device of the present invention possesses following operation.
At first, prepare to have mutually in opposite directions the 1st interarea and the Semiconductor substrate of the 1st conductivity type of the 2nd interarea.Then, on the 1st interarea of Semiconductor substrate, form the tagma of the 2nd conductivity type.Then, form the source diffused layer of the 1st conductivity type on the 1st interarea in the tagma.Then, on the tagma of the 1st conductive area that is become the Semiconductor substrate of leaking diffusion layer and source diffused layer clamping, form gate electrode opposite to each other by gate insulating film.Then, have the insulated-gate type field effect transistor portion of leaking diffusion layer, source diffused layer and gate electrode in formation after, remove the 2nd interarea of drift layer (leakage diffusion layer), make the thickness of Semiconductor substrate become 50 μ m above, below the 250 μ m.
The semiconductor device according to the invention manufacture method can enough polishing attenuate Semiconductor substrate.
Also have, owing to subtract the thickness of Semiconductor substrate thinner than the conventional example, the resistive component of thickness direction tails off, and can realize low conducting voltageization (low R ONChange).
Also have, since with the thickness of Semiconductor substrate be located at more than the 50 μ m, below the 250 μ m, and have both the insulated-gate type field effect transistor structure that improves the puncture capacity, in the puncture capacity when the withstand voltage of main that can guarantee device and device work, can reduce the wastage.
In aspect above-mentioned, ideal situation is: after removing the 2nd interarea of drift layer, also possess the operation that forms the impurity diffusion layer of the 2nd conductivity type on the 2nd interarea of Semiconductor substrate.
Thus, owing to heat treated influence that can not be subjected to apply in the technology way forms impurity diffusion layer, can be apart from the simple formation impurity diffusion layer of the 2nd interarea.Thus, Semiconductor substrate can attenuate.
In aspect above-mentioned, ideal situation is: form impurity diffusion layer with ion implantation.
Thus, can be with good controlled formation impurity diffusion layer.
In aspect above-mentioned, ideal situation is: the operation that forms high concentration region with 1st conductivity type also higher than the impurity concentration of leaking diffusion layer on the 2nd interarea that has also possessed in the grinding of leaking diffusion layer.Impurity diffusion layer is formed on the 2nd interarea, constitutes the pn knot with high concentration region.High concentration region has the impurity concentration peak value of the following concentration of impurity concentration peak value of impurity diffusion layer.
Thus, when reducing main junction leakage characteristic, rising is withstand voltage, make smear electric current minimizing, switching loss E in the Ic waveform when disconnecting OFFReduce.Also have, have inhibition because of V CEIncrease cause E OFFThe effect that changes.
In aspect above-mentioned, ideal situation is: form high concentration region, make it to be positioned at the scope apart from the following degree of depth of the 2nd interarea 2 μ m.
Like this, because can simple formation high concentration region, the thickness of Semiconductor substrate can attenuate.
In aspect above-mentioned, ideal situation is: impurity diffusion layer is formed its impurity activation rate below 50%.
Thus, can prevent because of the baneful influence of process conditions change device property.
In aspect above-mentioned, ideal situation is: also possess the operation that forms grid usefulness groove on the 1st interarea of Semiconductor substrate, gate electrode is formed imbeds grid with in the groove.
Like this, the present invention is applicable to groove MOS grid type element.
In aspect above-mentioned, ideal situation is: gate electrode is formed its upper surface and uses in the groove outstanding from grid.
Like this, the present invention is applicable to groove MOS grid type element.
In aspect above-mentioned, ideal situation is: gate electrode is formed its upper surface and retreats into the 2nd interarea side of leaning on the 1st interarea.
Like this, the present invention is applicable to groove MOS grid type element.
In aspect above-mentioned, ideal situation is: also possess the operation that forms the source electrode that is electrically connected with source diffused layer in the 1st interarea side.
Thus, can adjust the current potential of source diffused layer by the source electrode.
In aspect above-mentioned, ideal situation is: also possess the operation that forms source electrode usefulness groove on the 1st interarea of Semiconductor substrate, the conductive layer that is electrically connected with the source electrode of formation makes it landfill source electrode groove.
Like this, because the groove of the conductive layer by being provided with the landfill source electric potential can reduce effective grid width, thereby has the effect that suppresses saturation current.Also have,, can keep electric current arbitrarily in the long time than conventional example when device carries out switch under no-load condition by reducing the effect of saturation current.That is, have the saturation current of suppression device, and improve the effect of puncture capacity.And then, can be suppressed at the vibration when carrying out switch under the no-load condition.
In aspect above-mentioned, ideal situation is: form multiple source lateral electrode groove, form on the 1st interarea source electrode with conductive layer in order to landfill multiple source lateral electrode with groove after, it is graphical, thereby with the integrated formation landfill multiple source lateral electrode of single layer each with the conductive layer of groove.
Thus, become possibility with the single integrated landfill multiple source lateral electrode of layer with groove.
Description of drawings
Fig. 1 is the profile that the semiconductor device structure in the invention process form 1 roughly is shown.
Fig. 2～11st illustrates the summary section of the manufacture method of the semiconductor device in the invention process form 1 by process sequence.
Figure 12 illustrates V CESPerhaps V ONGraph of a relation with Semiconductor substrate thickness.
Figure 13 illustrates V CEPerhaps I CWith time relation figure.
Figure 14 illustrates loss and V ONGraph of a relation.
Figure 15 is the graph of a relation that the ion implantation dosage of effective doping of p type collector electrode and p type collector electrode is shown.
Figure 16 illustrates V ONGraph of a relation with the ion injection rate of collector electrode.
Figure 17 illustrates and the corresponding impurities concentration distribution figure of part along the XVII-XVII line of Fig. 1.
Figure 18 illustrates V ONVariable quantity (| Δ V ON|) with the graph of a relation of stress time.
Figure 19 illustrates V behind the stress application CESVariable quantity (| Δ V ON|) figure.
Figure 20 illustrates logE OFFWith V CEGraph of a relation.
Figure 21 is the summary section that the collector structure of the semiconductor device in the invention process form 3 is shown.
Figure 22 is the figure that the junction leakage characteristic is shown.
Figure 23 is the V that illustrates when disconnecting CEPerhaps I CWith time relation figure.
Figure 24 is the plane graph that roughly is illustrated in the structure of the semiconductor device in the invention process form 5.
Figure 25 and Figure 26 are respectively along the XXV-XXV line of Figure 24 and the summary section of every line in the XXVI-XXVI line.
Figure 27 is the general view that another structure of the semiconductor device in the invention process form 5 is shown.
Figure 28 is the summary section along the XXVIII-XXVIII line of Figure 27.
Figure 29 is the general view that is illustrated in the another structure of the semiconductor device in the invention process form 5.
Figure 30 is the summary section along the XXX-XXX line of Figure 29.
Figure 31 is the general view that is illustrated in the another structure of the semiconductor device in the invention process form 5.
Figure 32 is the summary section along the XXXII-XXXII line of Figure 31
Figure 33 is the summary section that is illustrated in the manufacture method of the semiconductor device in the invention process form 5.
Figure 34 illustrates J CWith V CEGraph of a relation.
Figure 35 is the enlarged drawing that the region S 2 of Figure 34 is shown.
Figure 36 and Figure 37 illustrate V CEPerhaps I CWith time relation figure.
Figure 38 illustrates V CEWith time relation figure.
Figure 39～Figure 74 is the summary section that is illustrated in the structure of the various semiconductor device in the example 6 of the present invention.
Figure 75 is the profile that the structure of conventional semiconductor device roughly is shown.
Figure 76～Figure 85 is the summary section that the manufacture method of conventional semiconductor device is shown by process sequence.
Embodiment
Below, based on description of drawings example of the present invention.
(example 1)
Fig. 1 is the summary section that the semiconductor device structure in the example 1 of the present patent application is shown.With reference to Fig. 1, the semiconductor device of this example is to have for example thickness t of 50～250 μ m 1Semiconductor substrate on the groove-shaped IGBT that forms.n -Silicon substrate 1 has for example about 1 * 10 14Cm -3Concentration.At this n -The 1st interarea side of silicon substrate 1 forms for example by concentration about 1 * 10 15～1 * 10 18Cm -3, apart from p type tagma 2 that the p N-type semiconductor N of about 1.0～4.0 μ m of diffusion depth of the 1st interarea constitutes.On the 1st interarea in p type tagma 2, forming by for example concentration is 1 * 10 18～1 * 10 20Cm -3, apart from n type emitter region 3 that the n N-type semiconductor N of about 0.3～2.0 μ m of diffusion depth of the 1st interarea constitutes.On 1st interarea adjacent, be formed for obtaining p to the low resistance contact in p type tagma 2 with this n type emitter region 3 +Impurity diffusion zone 6, p +The concentration of impurity diffusion zone 6 for example is 1 * 10 18～1 * 10 20Cm -3The diffusion depth of degree, distance the 1st interarea is below the degree of depth of n type emitter region 3.
On the 1st interarea, break-through n type emitter region 3 and p type tagma 2 form and arrive n -The grid of silicon substrate 1 groove 1a.This grid has for example degree of depth of 3～10 μ m of distance the 1st interarea with groove 1a, and grid for example is 2.0 μ m～6.0 μ m with the pitch of groove 1a.On the inner surface of this grid usefulness groove 1a, form gate insulating film 4a.This gate insulating film 4a for example is to be purpose with the characteristic, reliability and the device yield that improve gate insulating film, have the silicon oxide film that forms with the CVD method and the silicon oxide film that forms with thermal oxidation method or nitrogen at Si/SiO 2The stepped construction of silicon oxynitride film of interface segregation.
Form for example by the polysilicon, the W/TiSi that import high concentration phosphorus 2Deng the gate electrode 5a that constitutes of metal material, make it landfill grid groove 1a.In addition, in order to make gate electrode 5a low resistanceization, also can (for example: TiSi on the surface of gate electrode 5a, form silicide layer 2, CoSi etc.).At the upper surface of this gate electrode 5a, form the dielectric film 22A that for example constitutes by silicon oxide layer.Also have, gate electrode 5a is electrically connected with the control electrode of supplying with grid current potential G.
Like this, constitute gate groove by grid with groove 1a, gate insulating film 4a and gate electrode 5a.Also have, by n -Silicon substrate 1, n type emitter region 3 and gate electrode 5a constitute with n -Silicon substrate 1 as leak, n type emitter region 3 is as the insulated-gate type field effect transistor portion (being MOS transistor here) in source.This MOS transistor portion disposes a plurality of on the 1st interarea.
On the 1st interarea, for example form the dielectric film 9 that constitutes by silicate glass and, the contact hole 9a of arrival the 1st interarea is set on these dielectric films 9,22B by the dielectric film 22B that constitutes by silicon oxide film that the CVD method forms.Form barrier metal layer 10 in mode along the upper surface of the inner surface of contact hole 9a and dielectric film 9,22b.At the coupling part formation silicide layer 21a of this barrier metal layer 10 with Semiconductor substrate.By this barrier metal layer 10 and silicide layer 21a, the emitter electrode 11 of supplying with emitter current potential E is electrically connected to n type emitter region 3 and p + Impurity diffusion zone 6.
Also have, at n -The 2nd interarea side of silicon substrate 1 forms p type collector region 8, and the collector electrode 12 of supplying with collector potential C is electrically connected to this p type collector region 8.The material of this collector electrode 12 for example is an aluminium compound.
In this example, the thickness t of Semiconductor substrate 1Be more than the 50 μ m, below the 250 μ m.
In the semiconductor device of this example, for example when phase inverter connects, with the emitter current potential is benchmark, the grid current potential G of control electrode is set under off state-control signal of the pulse type of 15V, be set under conducting state+15V, the collector potential C of collector electrode 12 according to grid current potential G show greatly supply voltage as and saturation voltage between voltage.
Secondly, the manufacture method of this example is described.
Fig. 2～Figure 11 is the summary section that the manufacture method of the semiconductor device in the invention process form 1 is shown by process sequence.At first, with reference to Fig. 2, by thick n -For example forming on the substrate surface that silicon substrate 1 constitutes, peak concentration is 1 * 10 15～1 * 10 18Cm -3, be the p type tagma 2 of 1.0～4.0 μ m apart from the diffusion depth of the 1st interarea.Secondly, on the 1st interarea, form masking layer 31.
With reference to Fig. 3, that masking layer 31 is graphical.As mask, for example by implementing ion injection etc., the formation surface concentration is 1.0 * 10 on the 1st interarea p type tagma 2 in this graphical masking layer 31 18～1.0 * 10 20Cm -3, be the n type emitter region 3 of 0.3 μ m～2.0 μ m apart from the diffusion depth of the 1st interarea.Then, remove masking layer 31.
With reference to Fig. 4, on the 1st interarea, for example form silicon oxide film 32 and form silicon oxide film 33 with thermal oxidation method successively with the CVD method.With common photomechanical process technology and lithographic technique that this silicon oxide film 32,33 is graphical.As mask Semiconductor substrate is implemented anisotropic etching by graphical silicon oxide film 32,33 with this.Thus, form break-through n type emitter region 3 and p type tagma 2 arrival n -The grid of silicon substrate 1 groove 1a.
With reference to Fig. 5,, make grid become circle, and make the concavo-convex planarization of grid with the sidewall of groove 1a with peristome and the bottom of groove 1a by carrying out the processing of isotropism plasma etching and sacrificial oxidation etc.Also have, by above-mentioned sacrificial oxidation, grid with the inner surface of groove 1a on sacrificial oxidation film 32a and heat oxide film 32 be integrally formed.Like this, become possibility by implementing isotropism plasma etching and sacrificial oxidation, make to be formed on grid with the raising of the characteristic of the gate insulating film on the inner surface of groove 1a.Then, remove oxide- film 32,32a, 33.
With reference to Fig. 6,, the 1st interarea of Semiconductor substrate and grid are exposed with the inner surface of groove 1a by removing above-mentioned oxide-film.
With reference to Fig. 7,, form the gate insulating film 4a that for example constitutes by silicon oxide film along the inner surface and the 1st interarea of grid with groove 1a.Form conductive layer 5 on whole surface, make it landfill grid groove 1a, conductive layer 5 is for example by the polysilicon that imports high concentration phosphorus or do not import material and W (the tungsten)/TiSi of the polysilicon of impurity with ion implantation importing phosphorus 2The metal material of (titanium silicide) etc. constitutes.
In addition, as gate insulating film 4a, with the characteristic, reliability and the device yield that improve as gate insulating film is purpose, wishes to use the silicon oxide film that formed by the CVD method and stepped construction that the silicon oxynitride film of the silicon oxide film that formed by thermal oxidation method or nitrogen segregation on the interface of silicon and silica constitutes.
Then, make conductive layer 5 graphical with common photomechanical process technology and lithographic technique.
With reference to Fig. 8, graphical by this, make conductive layer be retained in gate electrode with forming gate electrode 5a in the groove 1a.Here, in order to make gate electrode 5a low resistanceization also can on the surface of gate electrode 5a, form silicide layer (TiSi for example 2, COSi etc.).Then, by making the upper surface oxidation of gate electrode 5a, form the dielectric film 22A that for example constitutes by silicon oxide film.Then, for example forming, the surface concentration on the 1st interarea is 1.0 * 10 18～1.0 * 10 20Cm -3, apart from the diffusion depth of the 1st interarea p more shallow than n type emitter region 3 + Impurity diffusion zone 6.
With reference to Fig. 9, on the 1st interarea, form the dielectric film 22B that the dielectric film 9 for example be made of silicate glass, the silicon oxide film that forms with the CVD method constitute successively.On this dielectric film 9,22B, form contact hole 9a with common photomechanical process technology and lithographic technique.
With reference to Figure 10, form the barrier metal layer 10 that for example constitutes with sputtering method by metal level.Then, implement mild annealing at the contact site formation silicide layer 21a of barrier metal layer 10 with Semiconductor substrate.Then, form emitter electrode 11.
With reference to Figure 11, the n of the 2nd interarea side of grinding semiconductor substrate -Drift layer 1.By this kind grinding, with the thickness t of Semiconductor substrate 1Be adjusted into more than the 50 μ m, below the 250 μ m.
On the 2nd interarea after the grinding, for example after injecting p type impurity, make it diffusion with ion implantation, form p type collector region 8, and then, form the collector electrode 12 that for example constitutes by aluminium compound, finish semiconductor device shown in Figure 1.
In addition, in this example, as shown in figure 11, after forming emitter electrode 11, become and grind drift layer (n -The operation of the 2nd interarea layer 1).But, also can grind drift layer (n behind the opening of contact hole 9a or before the opening as shown in Figure 9 -Layer 1) the 2nd interarea, the thickness that makes Semiconductor substrate is more than the 50 μ m, below the 250 μ m.
Also has the thickness t of the Semiconductor substrate in this example 1N than the conventional example shown in Figure 75 -The thickness t of silicon layer 101 3Thick.
Secondly, the thickness that Semiconductor substrate in this example is described is in the reason more than the 50 μ m, below the 250 μ m.
Figure 12 illustrates V CESPerhaps V ONGraph of a relation with the thickness of Semiconductor substrate.With reference to Figure 12, under the high situation of substrate concentration, when the thickness of Semiconductor substrate is wanted hour V than 50 μ m CESSharply reduce.Thus, because the withstand voltage of main when being difficult to guarantee device work, so with the Semiconductor substrate thickness t 1Lower limit be located at 50 μ m.
Also have, even the thickness t of Semiconductor substrate 1Greater than 250 μ m, under the low situation of the concentration of substrate, V CESIllustrate and be roughly steady state value, do not have big effect to improving withstand voltage of main as can be known.Also have, when the thickness t of Semiconductor substrate 1Surpass under the situation of 250 μ m the fixed loss (E during IGBT work DC) sharply increase.Below, this point is described.
Figure 13 illustrates V CEPerhaps I CWith time relation figure.With reference to Figure 13, in general, the loss (E when power device is worked (switch) under inductive load Total) with the region representation of representing with hacures among the figure, and with following formulate.
E total＝E SW+E DC
Here, E DCBe the loss (fixed loss) of device when conducting state.Also has E SWBe the loss of device when conducting, shutoff, with following formulate.
E SW＝E ON+E OFF
E ONSwitching loss when being break-over of device, E OFFSwitching loss when being the device shutoff.
Fixed loss E in the following formula DC, be subjected to V ONInfluence, along with V ONRising and rise.This fixed loss E DCUsually account for overall loss E Total20～30%.But, as thickness thickening, the V of Semiconductor substrate ONDuring rising, E DCAccount for E TotalRatio just rise.Particularly, at V ONNear=the 2.6V, E DCAccount for E TotalRatio sharply rise, device is brought baneful influence.
Here, as shown in Figure 12, V ONThe thickness t of Semiconductor substrate when 2.6V 1Be about 250 μ m.This point in Figure 14 as can be known, when the thickness of Semiconductor substrate surpasses 250 μ m, fixed loss E DCTo overall loss E TotalIncrease sharp.
Like this, in order to reduce V ON, thereby E reduces the wastage Total, the upper limit of Semiconductor substrate thickness is set in 250 μ m.
As from the foregoing, by as this example with the thickness setting of Semiconductor substrate more than the 50 μ m, below the 250 μ m, can be to conducting voltage (V ON), withstand voltage of main (V CES), loss (E Total) wait device property not bring baneful influence, can obtain increasing the effect of the degree of freedom of Semiconductor substrate thickness again than existing method.
(example 2)
With reference to Fig. 1, in this example, the impurity activation rate of p type collector region 8 is below 50%.
In addition, because the structure of structure in addition and above-mentioned example 1 is roughly the same, its explanation of Therefore, omited.
Also have, because the manufacture method of manufacture method of this example and above-mentioned example 1 is roughly the same, so also omit its explanation.
In this example, after having formed each zone 1,2,3,6 shown in Figure 1, for example form p type collector region 8 with ion implantation.Therefore, p type collector region 8 is not made the influence of the high-temperature heat treatment of diffusion of impurities in each zone 1,2,3,6 etc.Therefore, the impurity activation rate of the p type collector region 8 of this example can rest on and be low to moderate below 50%.
In contrast, in the existing manufacture method shown in Figure 76～Figure 85, shown in Figure 76, begin p type collector region 108 from initial technology and existed.Therefore, p type collector region 108 is subjected to all heat treated influences in the manufacturing process.So existing p type collector region 108 has roughly 100% impurity activation rate, be difficult to activity ratio is accomplished that this is below value.
As mentioned above, as shown in figure 15, the impurity activation rate of the p type collector region 8 of this example is different with the impurity activation rate (100%) of the p type collector region 108 of conventional example, can accomplish below 50%.
In addition, Figure 15 illustrates the ion injection rate (transverse axis) of the reality of p type collector layer in the structure of Fig. 1 and the effective graph of a relation of doping (longitudinal axis).Also have, the black circles among Figure 15 is the measured value of the impurity activation rate of p type collector region 8 in the structure of Fig. 1 that the operation with Fig. 2 Figure 11 forms.
Secondly, the impurity activation rate that p type collector region 8 in this example is described is set at the reason below 50%.
Figure 16 is ion injection rate (injection rate when ion injects) and the V that p type collector layer is shown ONGraph of a relation.
In this example, reach below 50% because the impurity activation rate of p type collector region 8 is low, for the ion injection rate of actual set, the change in concentration of formed p type collector region 8 is reduced.Thus, for the ion injection rate of actual set, the variation of the concentration of the effective p type collector region 8 after the heat treatment reduces.That is, the allowance under the set point change conditions becomes big.Therefore, even injection rate change when ion injects, the concentration when the p type collector region 8 that forms in Semiconductor substrate is realized design also becomes possibility.
With reference to Figure 16, the concentration affects V of the p type collector region 8 of IGBT ONValue.Along with the ion injection rate of p type collector region from 1 * 10 14Cm -2Near ion injection rate, this V of reducing ONRise sharp.If existing p type collector region 108, then V with impurity activation rate of 100% ONChange to the collector region injection rate is bigger, and because the concentration change of ion shown in Figure 15 effective collector region the during change of ion injection rate when injecting is bigger, the V when ion injects during the change of ion injection rate ONChange increase the designs difficulty that becomes.
On the other hand, if the p type collector region 8 with low impurity activation rate of this example, then has the effect that suppresses the problems referred to above that existing collector region 108 run into, has the sufficient degree of freedom for designs, and also big for the change allowance in the technology, have and prevent to cause effect the device property baneful influence because of the change in the technology.
(example 3)
Figure 17 be illustrate along with the corresponding impurities concentration distribution figure of part of XVII-XVII line shown in Figure 1.With reference to Figure 17, solid line illustrates the structure A of the collector electrode side among Fig. 1, is shown in dotted line the collector structure B of example 4 described later (Figure 21), and the single-point chain-dotted line is each Impurity Distribution of the collector structure among Figure 75.
Among the structure A of the collector electrode side in Fig. 1, the surface concentration in the 2nd interarea of p type collector region 8 is 5 * 10 15Cm -3More than, be below the 1 μ m apart from the degree of depth of the 2nd interarea of p type collector region 8.The diffusion depth of p type collector region 8 is more shallow, is owing to form the cause of p type collector region 8 after forming other extrinsic region.That is, because this p type collector region 8 is not used to form the cause of influence of the high-temperature heat treatment of other extrinsic region.
Also have, owing to be located at 5 * 10 in the surface concentration of the 2nd interarea of p type collector region 8 15Cm -3More than, can realize the low resistance contact of p type collector region 8 and collector electrode 12, can prevent the instability of device property.
Figure 18 and Figure 19 show under the situation that the surface concentration of the p type collector region 8 in making this example changes, V behind the stress application ONAnd V CESOver time.By Figure 18 and Figure 19 as can be known, the surface concentration when p type collector region 8 is lower than 5 * 10 15Cm -3Situation under, V ONAnd V CESIncrease over time.Hence one can see that, when the surface concentration of p type collector region 8 is low excessively, hangs down and reach 5 * 10 15Cm -3When following, device property increases over time, and device property is brought ill effect.Therefore as can be known, as the structure A of the collector electrode side of this example, surface concentration is set in 5 * 10 15Cm -3When above, just has the effect that the suppression device reliability reduces.
Also have, Figure 20 shows main junction leakage characteristic under the 398K temperature, and (main knot is p type tagma 2 and n -The knot portion of silicon substrate 1).As shown in Figure 20, in the existing collector structure shown in Figure 75, along with V CERising E OFFRise sharp.On the other hand, in the collector structure A of this example, by V CEThe E that causes of variation OFFVariation less, the effect that switching loss increases and changes when having the mains voltage variations of inhibition when device is worked.
This is that surface concentration in the 2nd interarea of p type collector region 8 low (perhaps impurity activation rate is low to be reached below 50%) and diffusion depth are shallower than 1 μ m, even V owing in the collector structure A of this example, compare with existing collector structure CERise, the charge carrier injection efficiency from collector region when break-over of device is littler than existing collector structure, is accumulated in n when device turn-offs -The cause that hole amount in the silicon substrate 1 reduces.
(example 4)
Figure 21 is the summary section of structure that the collector electrode side of the semiconductor device in the invention process form 4 is shown.With reference to Figure 21, the structure of this example is at n -It is different that silicon substrate 1 and p type collector region 8 constitutes near n type impurity diffusion zone 7 this point that have high concentration the zone of pn knot the structure with shown in Figure 1.N type impurity diffusion zone 7 among the structure B of the collector electrode side of this example has the impurity concentration peak value of the following concentration of impurity concentration peak value of p type collector region 8 as shown in figure 17.Also have, it is below the 2 μ m that n type impurity diffusion zone 7 is formed apart from the degree of depth of the 2nd interarea.
In addition, because the structure of in addition p type collector region 8 and MOS transistor side has the structure identical with example 1～3, its explanation of Therefore, omited.
In the manufacture method of this example, as shown in figure 11, grinding drift layer (n -Layer 1) behind the 2nd interarea, on the 2nd interarea, forms n type impurity diffusion zone 7, form p type collector region 8 then.In addition, because the method for in addition manufacture method and above-mentioned example 1 is roughly the same, its explanation of Therefore, omited.
In this example, why the diffusion depth of n type impurity diffusion zone 7 shoals, be to form n type impurity diffusion zone 7, thereby n type impurity diffusion zone 7 is not used to form the cause of influence of high-temperature heat treatment of the impurity range of MOS transistor side because the impurity range of MOS transistor side forms the back.
The collector structure B of this example compares with collector structure A shown in Figure 1, is the structure that can suppress from the injection efficiency in the hole of p type collector region 8.
In this example, owing to be provided with n type impurity diffusion zone 7, compare with collector structure A shown in Figure 1, can access following effect.
(1) as shown in figure 22, main junction leakage characteristic reduces, withstand voltage rising.
(2) as shown in figure 23, the I when disconnecting CThe electric current of smearing in the waveform reduces, consequently switching loss (E OFF) reduce.
Also have, in structure B,, as shown in figure 20, have inhibition because of V because p type collector structure 8 has the structure same with structure A CEVariation cause E OFFThe effect that changes.
(example 5)
Figure 24 is the plane graph that the structure of the semiconductor device in the invention process form 5 roughly is shown.Also have, Figure 25 and Figure 26 are the summary sections along each bar in the XXV-XXV of Figure 24 and the XXVI-XXVI line.
Mainly with reference to Figure 25, in this example, at n -The n type impurity diffusion zone 14 of higher concentration is set near the zone of silicon substrate 1 and p type tagma 2 formation pn knots.
Mainly, used on the 1st interarea of groove 1a clamping p by 2 fence electrodes with reference to Figure 24 + Impurity diffusion zone 6 above-below direction in the drawings is divided into a plurality of (for example 3).Each p of being divided of above-below direction in the figure + Impurity diffusion zone 6 is electrically connected with emitter electrode 11 by single contact hole 9a.
Mainly with reference to Figure 24 and Figure 26, the landfill grid also extends on the 1st interarea of grid with groove 1a outside with the gate electrode 5a of groove 1a, is electrically connected with the conductive layer 11 that becomes welding zone on this extension.Barrier metal layer 10 is positioned at the lower floor of the conductive layer 11 that becomes this welding zone, forms silicide layer 21a on barrier metal layer 10 and zone that gate electrode 5a is connected.
In addition, on conductive layer 11 that this welding zone constitutes and emitter electrode 11, form passivating film 15.
In addition, because the structure of structure in addition and above-mentioned example 1 is roughly the same, same member is marked with prosign, and omits its explanation.
The structure that n type impurity diffusion zone 14 is set is not limited to the structure of Figure 24～Figure 26, also can be Figure 27 and structure shown in Figure 28.That is, n type impurity diffusion zone 14 can be set also in being provided with the structure of emitter trench.
Figure 27 is the general view of structure that the change example of the semiconductor device in the example 5 of the present invention is shown, and Figure 28 is the summary section along the XXVIII-XXVIII line of Figure 27.
With reference to Figure 27 and Figure 28, in by the zone of 2 MOS transistor clampings, emitter trench is set.Emitter trench is made of with conductive layer 5b with dielectric film 4b, emitter with groove 1b, emitter emitter.Emitter arrives n with groove 1b break-through p type tagma 2 and n type impurity diffusion zone 14 -Silicon substrate.Emitter with dielectric film 4b to form along the mode of this emitter with the inner surface of groove 1b.Emitter is formed landfill emitter groove 1b with conductive layer 5b, is electrically connected with its emitter electrode 11 on upper strata.
Lower floor at emitter electrode 11 forms barrier metal layer 10, the formation silicide layer 21b between the conductive layer 5b in this barrier metal layer 10 and emitter.
Be formed for obtaining p on by the 1st interarea of 2 emitter trench clampings to the low resistance contact in p type tagma 2 + Impurity diffusion zone 6, formation silicide layer 21a on it.
In such structure, n -Silicon substrate 1 is constituting near the n type impurity diffusion zone 14 that higher concentration is set the zone of pn knot with p type tagma 2.
In addition, because the structure of structure in addition and above-mentioned Figure 24～Figure 26 is roughly the same, same member is marked with prosign, and omits its explanation.
Also having, the structure of Figure 29 and Figure 30 and Figure 27 and Figure 28 is compared, is being different on the sidewall of emitter trench, on interpolation n type impurity diffusion zone 3 this point on the 1st interarea.
In addition, because in addition structure and Figure 27 and structure shown in Figure 28 are roughly the same, same member are marked with prosign, and omit its explanation.
In Figure 27～Figure 30, be that the situation of emitter current potential is described with regard to the landfill emitter with the conductive layer 5b of groove 1b, this conductive layer 5b also can have floating potential.Its structure below is described.
With reference to Figure 31 and Figure 32, the conductive layer 5b of landfill groove 1b and emitter electrode 11 are isolated by electricity, have the current potential of floating.In this case, the dielectric film 22B that on the conductive layer 5b of landfill groove 1b, form the dielectric film 22A that constitutes by for example silicon oxide film, the dielectric film 9 that constitutes by for example silicate glass, constitutes by for example silicon oxide film.
In addition, because in addition structure and Figure 27 and structure shown in Figure 28 are roughly the same, same member are marked with prosign, and omit its explanation.
The n type impurity diffusion zone 14 that is provided with in this example was injected by ion like that as shown in figure 33 before forming p type tagma 2 and diffuses to form.After this, form p type tagma 2, and then through making various semiconductor device (Figure 24～Figure 32) of this example with the same subsequent handling of example 1.
Also have, each structure of mos transistor structure E (Figure 28), F (Figure 30), G (Figure 32) is compared effective grid width and is reduced owing to have the groove of emitter current potential or floating potential with mos transistor structure C (Fig. 1), D (Figure 25).Consequently such as shown in figure 34, structure E, F, G lack than the electric current that structure C, D flow through, and have the effect that suppresses saturation current.
And then with reference to Figure 35, structure E, F, G become big in the position conducting voltage than structure C, low-voltage/low current density (region S 2 of Figure 34) that D is low.Mos transistor structure C is because than its n of existing structure -Silicon substrate 1 is thick, low from the hole injection efficiency of p type collector region 8, so conducting voltage rises.Also have, in mos transistor structure D, why conducting voltage reduces, even be owing to n in collector structure A -Silicon substrate is thicker, also has at USP6 the cause by the hole build-up effect of n type impurity diffusion zone 14 of record in 040,599.In mos transistor structure D, even than its n of existing structure -Silicon substrate 1 is thicker, also has the effect that the conducting voltage of making reduces.
As shown in figure 34, in mos transistor structure E, F, G, owing to reduce the effect of saturation current, as shown in figure 36, when device carries out switch under no-load condition, can in time, keep electric current arbitrarily than existing structure and mos transistor structure C, D length.That is the effect that, in mos transistor structure E, F, G, has the saturation current and the raising puncture capacity of suppression device.
Further, in having the mos transistor structure D that reduces the conducting voltage effect,, produce oscillatory occurences when under no-load condition, carrying out switch as Figure 37 and shown in Figure 38.But, in mos transistor structure E, F, G, even there is n type impurity diffusion zone 14, also owing to existing the conductive layer 5b that becomes emitter current potential or floating potential to have the effect of the oscillatory occurences of preventing.
Also have, the above-mentioned effective effect of mos transistor structure E, F, G is even be under the situation of structure A shown in Figure 1, even and can both obtain comparably under the situation of structure B shown in Figure 21 at the collector structure of the 2nd interarea side.
Otherwise, the mos transistor structure C shown in the example 1～4 is altered to any one among other MOS transistor D～G, also can access the effect same with example 1～4.
(example 6)
Figure 39～Figure 74 illustrates the summary section that obtains with the various derivative strucures of the mos transistor structure of example 5 effect same.No matter in which structure shown in Figure 39～Figure 74, still those mos transistor structures and the some of collector structure A or B are combined, can both obtain the effect of the mos transistor structure shown in the example 5.
Also have, the effect of the example 1～4 that obtains from collector structure A or B, with the combination of which kind of mos transistor structure shown in Figure 39～Figure 73 in also can similarly obtain.
Below, each mos transistor structure shown in Figure 39～Figure 73 is described.
Structure shown in Figure 39 is set to an emitter trench this point of emitter current potential on by the zone of 2 MOS transistor portions clamping, and it is different only to form on 3 this point of n type emitter region the structure with shown in Figure 28 on the side side of groove 1a at grid.
In structure shown in Figure 40, a plurality of emitters with in the groove 1b by the emitter that constitutes by integrated simple layer with conductive layer 5b landfill.Also have, emitter is electrically connected with barrier metal layer 10 and emitter electrode 11 by silicide layer 21b with conductive layer 5b.This silicide layer 21b is formed on and connects each emitter with on the bridge between the groove 11b.Also have, use on the conductive layer 5b, form dielectric film 22A, 9,22B at the emitter beyond the zone that forms silicide layer 21b.
Because in addition structure and above-mentioned structure shown in Figure 28 are roughly the same, same member is marked with prosign, and omits its explanation.
The structure shown in Figure 41 structure with shown in Figure 40 on interpolation n type impurity diffusion zone 3 this point on the 1st interarea of the two side of using groove 1b as emitter is different.
It is different that structure shown in Figure 42 becomes on the floating potential this point structure with shown in Figure 40 at the landfill emitter with the conductive layer 5b of groove 1b.In this case, on whole of conductive layer 5b, form dielectric film 22A, 9,22B, conductive layer 5b and emitter electrode 11 electric insulations.
The structure shown in Figure 43 structure with shown in Figure 39 on interpolation n type impurity diffusion zone 3 this point on the 1st interarea of the two side of using groove 1b as emitter is different.
Structure shown in Figure 44 emitter give prominence to the upper surface of conductive layer 5b emitter with groove 1b above on this point structure with shown in Figure 39 different.In this case, emitter is electrically connected with barrier metal layer 10 and emitter electrode 11 by the silicide layer 21b that forms on its a part of surface with conductive layer 5b.Also have, use at the emitter beyond the zone that forms silicide layer 21b to form dielectric film 22A, 9,22B on the conductive layer 5b.
The structure shown in Figure 45 structure with shown in Figure 44 on interpolation n type impurity diffusion zone 3 this point on the 1st interarea of using groove 1b two sides as emitter is different.
Structure shown in Figure 46 p type tagma 2 only be formed on grid with the sidewall of groove 1a near on this point structure with shown in Figure 28 different.
Structure shown in Figure 47 p type tagma 2 only be formed on grid with the sidewall of groove 1a near on this point structure with shown in Figure 30 different.
It is different that structure shown in Figure 48 becomes on the floating potential this point structure with shown in Figure 46 at the landfill emitter with the conductive layer 5b of groove 1b.In this case, on conductive layer 5b, form dielectric film 22A, 9,22B.
It is different that structure shown in Figure 49 only forms on 2 this point of p type tagma the structure with shown in Figure 39 on by the zone of 2 gate trench clampings.
Structure shown in Figure 50 p type tagma 2 only be formed on grid with the sidewall of groove 1a near on this point structure with shown in Figure 40 different.
Structure shown in Figure 51 p type tagma 2 only be formed on grid with the sidewall of groove 1a near on this point structure with shown in Figure 41 different.
Structure shown in Figure 52 p type tagma 2 only be formed on grid with the sidewall of groove 1a near on this point structure with shown in Figure 42 different.
Structure shown in Figure 53 structure with shown in Figure 49 on interpolation n type impurity diffusion zone 3 this point on the 1st interarea of using groove 1b two sides as emitter is different.
It is different that structure shown in Figure 54 only forms on 2 this point of p type tagma the structure with shown in Figure 44 on by the zone of 2 gate trench clampings.
It is different that structure shown in Figure 55 only forms on 2 this point of p type tagma the structure with shown in Figure 45 on by the zone of 2 gate trench clampings.
Structure shown in Figure 56 is not form groove on the zone that emitter trench exists in Figure 28, make the identical structure of grid width (W) with above-mentioned mos transistor structure E～G and form gate trench, that is be to make to become the structure that the emitter current potential expands to arbitrary dimension like that between the gate trench.
In this case, be used to obtain p with the low resistance contact in p type tagma + Impurity diffusion zone 6 extends in by on the 1st interarea of 2 gate trench clampings.Silicide layer 21a is formed and this p + Impurity diffusion zone 6 and n type emitter region 3 connect.p + Impurity diffusion zone 6 and n type emitter region 3 are electrically connected with emitter electrode 11 by this silicide layer 21a and barrier metal layer 10.
In addition, because the structure of structure in addition and above-mentioned Figure 28 much at one, same member is marked with prosign, and omits its explanation.
Structure shown in Figure 57 is not form groove on the zone that emitter trench exists in Figure 39, and the formation gate trench, the identical structure of grid width of feasible and above-mentioned mos transistor structure E～G, that is be to make to become the structure that the emitter current potential expands to arbitrary dimension like that between the gate trench.
In this structure, in order to obtain the low resistance contact with p type tagma, p + Impurity diffusion zone 6 extends in by on the 1st interarea of gate trench clamping.Silicide layer 21a is formed and this p + Impurity diffusion zone 6 and n type emitter region 3 connect.p + Impurity diffusion zone 6 and n type emitter region 3 are electrically connected with emitter electrode 11 by this silicide layer 21a and barrier metal layer 10.
In addition, because the structure of in addition structure and above-mentioned Figure 39 is roughly the same, same member is marked with prosign, and omits its explanation.
Figure 58 only is formed on grid and uses near the sidewall of groove 1a different with the structure shown in Figure 56 on this point in p type tagma 2.
Structure shown in Figure 59 is different with the structure shown in Figure 57 on this point on p type tagma 2 only is formed on by the zone of 2 gate trench clampings.
In the above, be described with the situation of groove 1a though be positioned at grid with regard to the upper surface of gate electrode 5a, give prominence at grid also passable on groove 1a.Figure 60～Figure 70 shows the upper surface of gate electrode 5a and gives prominence in the structure of grid with the upper surface of groove 1a.
Figure 60 is in structure shown in Figure 28, Figure 61 is in structure shown in Figure 30, Figure 62 is in structure shown in Figure 32, Figure 63 is in structure shown in Figure 39, Figure 64 is in structure shown in Figure 40, Figure 65 is in the structure shown in Figure 51, Figure 66 is in structure shown in Figure 42, Figure 67 is in the structure shown in Figure 53, Figure 68 is in the structure shown in Figure 54, Figure 69 is in the structure shown in 55, Figure 70 is in structure shown in Figure 41, give prominence at grid corresponding with the upper surface of gate electrode 5a with the structure on the groove 1a.In addition, in the structure shown in Figure 62, the upper surface of the conductive layer 5b of landfill groove 1b is also given prominence on groove 1b.
In addition, in the above, though be described with regard to groove-shaped grid structure, the structure of example 1～5 also can be applied among the IGBT of planar gate type.Figure 71～Figure 74 shows the summary section of planar gate type IGBT structure.
With reference to Figure 71, planar gate type IGBT is formed on the Semiconductor substrate that for example thick about 50 μ m are above, 250 μ m are following.In for example concentration 1 * 10 14Cm -3N -The 1st interarea side of silicon substrate 1 forms the p type tagma 2 that is made of the p N-type semiconductor N selectively.P type tagma 2 for example has 1 * 10 15～1 * 10 18Cm -3Concentration, have diffusion depth apart from the 1st interarea about 0.3～4.0 μ m.Form for example by concentration 1 * 10 on the 1st interarea in p type tagma 18～1 * 10 20Cm -3More than, the n type emitter region 3 that the n N-type semiconductor N of about 0.3～2.0 μ m of diffusion depth of distance the 1st interarea constitutes.Contiguous place in this n type emitter region 3 is formed for obtaining the p to the low resistance contact in p type tagma 2 + Impurity diffusion zone 6, p +The concentration of impurity diffusion zone 6 for example is 1 * 10 18～1 * 10 20Cm -3Degree, the diffusion depth of distance the 1st interarea forms below the degree of depth of n type emitter region 3.
On the 1st interarea, form gate electrode 5a by gate insulating film 4a, make it with by n -The p type tagma 2 of silicon substrate 1 and 3 clampings of n type emitter region in opposite directions.
By this n -Silicon substrate 1, n type emitter region 3 and gate electrode 5a constitute with n -Silicon substrate 1 is as leaking, with the insulated-gate type field effect transistor portion (here be MOS transistor portion) of n type emitter region 3 as the source.
On by the 1st interarea of 2 MOS transistor portions clamping, become the conductive layer 5b of emitter current potential.The material of this conductive layer 5b and gate electrode 5a is used polysilicon, high melting point metal materials, refractory metal silicide or their composite membrane that for example imports high concentration phosphorus.
On the 1st interarea, form dielectric film 9, on this dielectric film 9, form the contact hole 9a on the part surface that reaches the 1st interarea.Barrier metal layer 10 is formed on the bottom at this contact hole 9a.The emitter electrode 11 of supplying with emitter current potential E by this barrier metal layer 10 is connected electrically in conductive layer 5b, p +On impurity diffusion zone 6 and the n type emitter region 3.
Also have, at n -The 2nd interarea side of silicon substrate 1 forms n type impurity diffusion zone 7 and p type collector region 8 successively.The collector electrode 12 of supplying with collector potential is electrically connected with p type collector region 8.The material of this collector electrode 12 for example is an aluminium compound.
In this example, the thickness t of Semiconductor substrate 1Be more than the 50 μ m, below the 250 μ m.Also have, the impurity activation rate of p type collector region 8 is below 50%.Also have, wish that the degree of depth apart from the 2nd interarea of p type collector region 8 is below 1 μ m.Also have, wish that n type impurity diffusion zone 7 has the impurity concentration peak value lower than the impurity concentration peak value of p type collector region 8.Also have, wish that this n type impurity diffusion zone 7 is forming apart from the degree of depth below the 2nd interarea 2 μ m.
In addition, to the structure of Figure 71, also can shown in Figure 72, add n type impurity diffusion zone 14 like that, also have, also can shown in Figure 73, omit n type impurity diffusion zone 7 like that, also have, also can shown in Figure 74, add n type impurity diffusion zone 14 like that and omit n type impurity diffusion zone 7.
In addition, in this example, be that example is illustrated, but be not limited to IGBT,, can both use the present invention so long as have the element of insulated-gate type field effect transistor with IGBT.
Should think that all aspects of the current example of announcing all are exemplary rather than restrictive.Scope of the present invention is not by above-mentioned explanation, but is intended to be represented by the scope of claim, is included in and the meaning of the scope equalization of claim and all changes in the scope.
The possibility of utilizing on the industry
The present invention relates to high withstand voltage element, the particularly structure of IGBT is especially at groove Brought into play to greatest extent its effect among the grid IGBT. Also have, the present invention is realizing low conducting Voltage, when guaranteeing to puncture capacity, can advantageously be applied to be reduced in the high-pressure side Semiconductor devices and the manufacture method thereof of switching loss. Also have, also can advantageously use In preventing that change because of process conditions from causing the semiconductor to the baneful influence of device property Device and manufacture method thereof. Also have, also can advantageously be applied to the free degree of substrate thickness Restriction is few, and is suitable for the manufacture method of the semiconductor devices of low price.

Claims (7)

1. semiconductor device is characterized in that:
Possess:
Semiconductor substrate, this Semiconductor substrate have mutual the 1st interarea and the 2nd interarea in opposite directions;
Insulated-gate type field effect transistor portion, this insulated-gate type field effect transistor portion has insulated gate structure in above-mentioned the 1st interarea side, and flows through principal current between above-mentioned the 1st interarea and above-mentioned the 2nd interarea; And
Impurity diffusion layer (8), this impurity diffusion layer (8) is formed on above-mentioned the 2nd interarea, and the impurity activation rate is below 50%.
2. semiconductor device as claimed in claim 1 is characterized in that:
The impurity surface concentration of the above-mentioned impurity diffusion layer (8) on above-mentioned the 2nd interarea is 5 * 10 15Cm -3More than.
3. semiconductor device as claimed in claim 1 is characterized in that:
The diffusion depth of above-mentioned impurity diffusion layer (8) is that above-mentioned the 2nd interarea of distance is not more than 1 μ m.
4. semiconductor device as claimed in claim 1 is characterized in that:
The leakage diffusion layer (1) of above-mentioned impurity diffusion layer (8) and above-mentioned insulated-gate type field effect transistor portion constitutes the pn knot,
Above-mentioned leakage diffusion layer (1) has the 1st high concentration region (7) of the 1st conductivity type in the zone that is connected with above-mentioned impurity diffusion layer (8),
Above-mentioned the 1st high concentration region (7) has the impurity concentration peak value of the following concentration of impurity concentration peak value of above-mentioned impurity diffusion layer (8).
5. semiconductor device as claimed in claim 1 is characterized in that:
On above-mentioned the 1st interarea of above-mentioned Semiconductor substrate, form grid groove (1a), the gate electrode (5a) of above-mentioned insulated-gate type field effect transistor portion is embedded in above-mentioned grid with in the groove (1a), the upper surface of above-mentioned gate electrode (5a) from above-mentioned grid with outstanding in the groove.
6. semiconductor device as claimed in claim 1 is characterized in that:
On above-mentioned the 1st interarea of above-mentioned Semiconductor substrate, form grid groove (1a), the gate electrode (5a) of above-mentioned insulated-gate type field effect transistor portion is embedded in above-mentioned grid with in the groove (1a), and the upper surface of above-mentioned gate electrode (5a) retreats in the groove under the 1st interarea.
7. semiconductor device as claimed in claim 1 is characterized in that:
Also possesses the source electrode (11) that is electrically connected with the source diffused layer (3) of above-mentioned insulated-gate type field effect transistor portion in above-mentioned the 1st interarea side.
CNB2005100651357A 2001-02-01 2001-02-01 Semiconductor device Expired - Lifetime CN100416858C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB2005100651357A CN100416858C (en) 2001-02-01 2001-02-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2005100651357A CN100416858C (en) 2001-02-01 2001-02-01 Semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CNB018099998A Division CN1268003C (en) 2001-02-01 2001-02-01 Semiconductor device and methdo of manufacturing the same

Publications (2)

Publication Number Publication Date
CN1665034A CN1665034A (en) 2005-09-07
CN100416858C true CN100416858C (en) 2008-09-03

Family

ID=35036006

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005100651357A Expired - Lifetime CN100416858C (en) 2001-02-01 2001-02-01 Semiconductor device

Country Status (1)

Country Link
CN (1) CN100416858C (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4600936B2 (en) * 2007-06-20 2010-12-22 三菱電機株式会社 Semiconductor device and manufacturing method thereof
JP6560059B2 (en) * 2015-08-20 2019-08-14 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
CN113764522B (en) * 2021-07-30 2023-11-21 广州华浦电子科技有限公司 Insulated gate bipolar transistor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57194583A (en) * 1981-05-27 1982-11-30 Hitachi Ltd Mos semiconductor device and manufacture thereof
JPH021985A (en) * 1988-06-10 1990-01-08 Mitsubishi Electric Corp Manufacture of semiconductor device
US4893165A (en) * 1988-02-24 1990-01-09 Siemens Aktiengesellschaft Bipolar transistor controllable by field effect
CN1148274A (en) * 1995-10-16 1997-04-23 三星电子株式会社 Trench DMOS and method of fabricating the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57194583A (en) * 1981-05-27 1982-11-30 Hitachi Ltd Mos semiconductor device and manufacture thereof
US4893165A (en) * 1988-02-24 1990-01-09 Siemens Aktiengesellschaft Bipolar transistor controllable by field effect
JPH021985A (en) * 1988-06-10 1990-01-08 Mitsubishi Electric Corp Manufacture of semiconductor device
CN1148274A (en) * 1995-10-16 1997-04-23 三星电子株式会社 Trench DMOS and method of fabricating the same

Also Published As

Publication number Publication date
CN1665034A (en) 2005-09-07

Similar Documents

Publication Publication Date Title
JP5025071B2 (en) Semiconductor device and manufacturing method thereof
CN1327524C (en) Semiconductor device and its making method
CN101083284B (en) Semiconductor device having trench charge compensation regions and method
US6462382B2 (en) MOS type semiconductor apparatus
CN100334731C (en) Trench DMOS transistor with embedded trench schottky rectifier
CN101983431B (en) Semiconductor device
KR100886420B1 (en) Semiconductor structure with improved smaller forward voltage loss and higher blocking capability
KR100679538B1 (en) A super-self-aligned trench-gate dmos with reduced on-resistance
CN101369532B (en) Structures of and methods of fabricating trench-gated mis devices
US10177221B2 (en) Integrated Schottky diode in high voltage semiconductor device
CN110718546B (en) Insulated gate semiconductor device and method of manufacturing the same
CN105185825A (en) Injection Control In Semiconductor Power Devices
US5895953A (en) Ohmic contact to lightly doped islands from a conductive rapid diffusion buried layer
CN1855543B (en) Power semiconductor device having improved performance and method
CN104332495B (en) A kind of igbt and its manufacture method
US20140070265A1 (en) Fast switching igbt with embedded emitter shorting contacts and method for making same
US5751022A (en) Thyristor
US6153473A (en) Method of symmetrically implanted punch-through stopper for a rugged DMOS power device
CN100416858C (en) Semiconductor device
JP2002299622A (en) Semiconductor element for power
JPH023980A (en) Perpendicular field effect transistor
JP6026767B2 (en) Semiconductor device and manufacturing method thereof
CN101097959A (en) Semiconductor device and method of manufacturing the same
CN113725295B (en) Reverse-conduction MOS gate-controlled thyristor and manufacturing method thereof
TWI472029B (en) Vertical capacitive depletion field effect transistor

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20080903