CN100405821C - Video signal processing circuit - Google Patents
Video signal processing circuit Download PDFInfo
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- CN100405821C CN100405821C CNB2005101291698A CN200510129169A CN100405821C CN 100405821 C CN100405821 C CN 100405821C CN B2005101291698 A CNB2005101291698 A CN B2005101291698A CN 200510129169 A CN200510129169 A CN 200510129169A CN 100405821 C CN100405821 C CN 100405821C
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Abstract
A video signal processing circuit is supplied with an analog composite video signal formed by combining at least a luminance signal with a sync signal, and processes the analog composite video signal. The video signal processing circuit has an analog filter which removes high-frequency components from the analog composite video signal, a sync separation circuit which separates a sync signal from an output signal from the analog filter, an AD converter which performs AD conversion on the analog composite video signal, and a digital video signal processing circuit which performs predetermined video signal processing on the composite video signal digitized by the AD converter, by using the sync signal obtained by the sync separation circuit.
Description
Technical field
The present invention relates to simulation composite video signals such as television broadcasting signal are carried out the AD conversion and the composite video signal after the digitlization is implemented the video processing circuit that vision signal is handled.
Background technology
In the past, will adopt the decoder (analog video decoder) of the analog form of BIP-IC as the video decoder that generates rgb signal from simulation composite video signals such as analog tv broadcast signals widely.Yet, in recent years, because the development of digital technology, and be accompanied by universal such as LCD (LCD) or plasma display panel (PDP) digital display of etc.ing, utilize the decoder (digital video transcoding device) of the digital form of MOS-IC to increase gradually.
Figure 11 is the block diagram that the structure of analog video decoder 70 is shown.In Figure 11, to analog video decoder 70 input simulation composite video signals, this signal is provided for simulation synchronizing separator circuit 71 and analogue video signal processing circuit 72 from the outside.Simulation synchronizing separator circuit 71 is isolated synchronizing signal from the simulation composite video signal, and provides it to analogue video signal processing circuit 72.Analogue video signal processing circuit 72 is provided by the synchronizing signal that provides from simulation synchronizing separator circuit 71, the simulation composite video signal is implemented various vision signals handle (as Y/C separation, colored demodulation etc.), generates analog rgb signal and output.
Figure 12 is the block diagram that the structure of digital video transcoding device 80 is shown.In Figure 12, simulate composite video signals from the outside to 80 inputs of digital video transcoding device.Utilizing AD converter (ADC) 81 should simulate after composite video signal converts digital signal to, provide it to digital synchronous split circuit 82 and digital video signal processing circuit 83.Isolate synchronizing signal the composite video signal of digital synchronous split circuit 82 after digital translation, and provide it to digital video signal processing circuit 83.Digital video signal processing circuit 83 is provided by the synchronizing signal that provides from digital synchronous split circuit 82, the composite video signal after the digitlization is implemented various vision signals handle (as Y/C separation, colored demodulation etc.), generates digital rgb signal and output.
In addition, open in the 2003-153298 communique and special opening has the relevant record of simulation composite video signal in the flat 10-254422 communique the spy.
Above-mentioned digital video transcoding device is compared with the simulation video decoder, has and follows digitized advantage.Yet, for the net synchronization capability during for weak electric field, just not as good as the analog video decoder.Below, be described at both difference of net synchronization capability.
Figure 13 A is the oscillogram of the simulation composite video signal under the muting state.In Figure 13 A, illustrated by luminance signal and the synthetic monochrome television signal of synchronizing signal.In addition, colour TV signal is exactly in monochrome television signal, goes up the stack chrominance pulse phasing signal (color burst) and the carrier chrominance signal that superposes in pulse back edge (back porch) on luminance signal.
Shown in the dotted line of Figure 13 A, the separation of synchronizing signal (separated in synchronization) is to be undertaken by utilizing comparator to cut (amplitude limit) composite video signal by the front end level (sync-tip level (sync tip level)) of synchronizing signal and the clip level between the pedestal level (pedestal level).By this separated in synchronization, synchronizing signal is separated shown in Figure 13 B.But, in Figure 13 C, obviously finding out, when weak electric field, occur high-frequency noise in the composite video signal, and this noise can exert an influence to separated in synchronization.
Figure 14 is the figure that the order of separated in synchronization is shown.The left side of Figure 14 shows an example of the order of using the analog video decoder, and the right side shows an example of the order of using the digital video transcoding device.Below, according to Figure 14, the separated in synchronization during at weak electric field comes analog video decoder and digital video transcoding device are compared.
Shown in the left side of Figure 14, the analog video decoder is removed radio-frequency component by utilizing simulation low-pass filter from the simulation composite video signal, cut out resulting signal by utilizing comparator by clip level, separates synchronizing signal.Thus, according to the analog video decoder, even when weak electric field, also can separate synchronizing signal well.
On the other hand, shown in the right side of Figure 14, the digital video transcoding device at first comes the simulation composite video signal is sampled by sampling clock, converts digital composite video signal again to.At this moment, owing to, cause containing in the composite video signal after digital translation digitized noise contribution because of weak electric field signal noise superimposed.Although this noise contribution is weakened to a certain extent by wave digital lowpass filter, the final or residual signal that has after the separated in synchronization, i.e. Zai Sheng synchronizing signal.
Like this, at present, the separated in synchronization of digital video transcoding device during at weak electric field is poorer than the analog video decoder.
At this because synchronizing signal is the timing information of composite video signal, thereby correctly do not reproducing under the situation of synchronizing signal, can produce such as so-called picture tremble, luminance signal or colour signal be by the problem the correct regeneration etc.
Summary of the invention
The invention provides a kind of video processing circuit, it receives and has synthesized the simulation composite video signal of luminance signal, colour signal and synchronizing signal at least, it is characterized in that, comprising: analog filter, it removes radio-frequency component from above-mentioned simulation composite video signal; Synchronizing separator circuit, it separates above-mentioned synchronizing signal from the output signal of above-mentioned analog filter; AD converter, it carries out the AD conversion to above-mentioned simulation composite video signal; And digital video signal processing circuit, it utilizes the above-mentioned synchronizing signal that is obtained by above-mentioned synchronizing separator circuit, from generate the tricolor signal of numeral through the digitized composite video signal of above-mentioned AD converter.
In addition, the present invention also provides a kind of video processing circuit, it receives and has synthesized the simulation composite video signal of luminance signal and synchronizing signal at least, and this simulation composite video signal handled, it is characterized in that, comprise: AD converter, it carries out the AD conversion to above-mentioned simulation composite video signal; The digital synchronous split circuit, it is from separating synchronizing signal through the digitized composite video signal of above-mentioned AD converter; Input terminal, it receives outside simulation synchronizing separator circuit is removed isolated synchronizing signal in the signal that obtains behind the radio-frequency component from utilize the above-mentioned simulation composite video signal of analog filter supply; Selector, it selects in synchronizing signal that is obtained by above-mentioned digital synchronous split circuit and the synchronizing signal that is provided to above-mentioned input terminal any one; And digital video signal processing circuit, it utilizes the synchronizing signal of being selected by above-mentioned selector, and the vision signal of implementing regulation through the digitized composite video signal of above-mentioned AD converter is handled.
Description of drawings
Fig. 1 is the block diagram that illustrates according to the structure of the video processing circuit of first execution mode.
Fig. 2 is the figure that an example of synchronizing separator circuit structure is shown.
Fig. 3 shows the oscillogram of the signal in the vertical synchronization split circuit.
Fig. 4 is the block diagram that illustrates according to the video processing circuit structure of second execution mode.
Fig. 5 is the figure that an example of digital synchronous split circuit structure is shown.
Fig. 6 is the block diagram that is illustrated in the structure of the video processing circuit that the appended synchronization split circuit forms in the video processing circuit of Fig. 4.
Fig. 7 is the figure that an example of simulation synchronizing separator circuit structure is shown.
Fig. 8 is the block diagram that is used to illustrate that the timing of clamp pulse is regulated.
Fig. 9 is the oscillogram of synchronizing signal and clamp pulse.
Figure 10 illustrates to have the block diagram of structure of video processing circuit that switches the function of synchronizing signal according to noise contribution.
Figure 11 is the block diagram that the structure of analog video decoder is shown.
Figure 12 is the block diagram that the structure of digital video transcoding device is shown.
Figure 13 A is the oscillogram of the simulation composite video signal under the noiseless state.
Figure 13 B is from the oscillogram of the isolated synchronizing signal of simulation composite video signal by separated in synchronization.
The oscillogram of the simulation composite video signal when Figure 13 C is weak electric field.
Figure 14 is the figure that the order of separated in synchronization is shown.
Embodiment
Below, embodiments of the invention are described with reference to the accompanying drawings.
[first execution mode]
Fig. 1 is the block diagram according to the structure of the video processing circuit 1 of first execution mode.This video processing circuit 1 is the output circuit that generates 3 primary colors (RGB) signal of numeral according to the simulation composite video signal from the outside input.Here, so-called simulation composite video signal is meant vision signal and the synthetic analog signals that form of synchronizing signal such as luminance signal or colour signal, for example TV signal such as TSC-system formula or pal mode.
In Fig. 1, video processing circuit 1 comprises: AD converter (ADC) 11, digital video signal processing circuit 12, low pass filter (LPF) 21 and synchronizing separator circuit 22.Preferably, also additional LPF 21 and synchronizing separator circuit 22 in the digital IC 10 that contains ADC 11 and digital video signal processing circuit 12.In this structure, be imported among ADC 11 and the LPF 21 from the simulation composite signal of outside.
Synchronizing separator circuit 22 separates synchronizing signal from the analog signal that provides from LPF 21, via the input terminal 13 of digital IC 10 resulting synchronizing signal is offered digital video signal processing circuit 12.Here, synchronizing signal is horizontal-drive signal (H-SYNC) and vertical synchronizing signal (V-SYNC), or the synthetic synchronizing signal (C-SYNC) with them after synthetic.In Fig. 2, show an example of the structure of synchronizing separator circuit 22.But, as synchronizing separator circuit, the various types of synchronizing separator circuits of cicada are not done special restriction to the type of the related synchronizing separator circuit 22 of present embodiment.Below, the synchronizing separator circuit shown in Fig. 2 22 is described.In addition, in the following description, the simulation composite video signal is made as the TV signal of TSC-system formula.
In Fig. 2, synchronizing separator circuit 22 comprises comparator 31, PLL circuit 32, frequency divider 33, vertical synchronization split circuit 34 and switching circuit 35.
The input of the output signal S1 of phase detectors 32a reception comparator 31 and the output signal S5 (H-SYNC of regeneration) of frequency divider 32d, both phase places are compared, and have and both the phase signal S2 of the corresponding magnitude of voltage of phase difference to loop filter 32b output.
VCO 32 changes the frequency of oscillation of its output signal S4, and offers frequency divider 32d according to the magnitude of voltage of the signal S3 that provides from loop filter 32b.Here, VCO 32c changes frequency of oscillation towards the direction that does not have phase difference between the output signal S5 of the output signal S1 of comparator 31 and frequency divider 32d.
The output signal S1 of above-mentioned comparator 31 also is provided for vertical synchronization split circuit 34 when being provided for above-mentioned PLL circuit 32.
Vertical synchronization split circuit 34 comprises integrating circuit 34a and comparator 34b.The oscillogram of the output signal S9 of the output signal S8 of the input signal S1, the integrating circuit 34a that are input to vertical synchronization split circuit 34 and comparator 34b has been shown among Fig. 3.
Switching circuit 35 with any one the signal-selectivity ground among the output signal S9 of the output signal S7 of frequency divider 33 and vertical synchronization split circuit 34 as the V-SYNC of regeneration and output to the input terminal 13 of digital IC 10.For example, switching circuit 35 is selected signal S9 at a certain series analog composite video signal always till the inceptive impulse of signal S9 is output, and selects signal S7 after this pulse of output.
In addition, the outside that also will output to video processing circuit 1 by C-SYNC, H-SYNC or the V-SYNC of above-mentioned synchronizing separator circuit 22 regeneration.
Turn back to Fig. 1,11 pairs of simulation composite video signals of being imported of ADC carry out the AD conversion, and resulting digital composite video signal is offered digital video signal processing circuit 12.
Digital video signal processing circuit 12 utilizes the synchronizing signal (H-SYNC and V-SYNC) that is provided to input terminal 13, just by the synchronizing signal of synchronizing separator circuit 22 regeneration, the vision signal of being implemented regulation by ADC 11 digitized composite video signals is handled, generate the rgb signal of numeral, and output to the outside.Here, vision signal as regulation is handled, for example be, generate the clamp pulse of the clamp circuit (not shown) be used to make the clamping of simulation composite video signal processing, according to digitized composite video signal generate luminance signal (Y) and colour signal (C) the Y/C separating treatment, come the colored demodulation process of demodulation color difference signal (R-Y, G-Y, B-Y) and generate processing or the like according to the colour signal that is generated according to the rgb signal that luminance signal and color difference signal generate rgb signal.
Operation to video processing circuit 1 with said structure is described simply.Simulation composite video signal from the outside is imported into ADC 11 and LPF 21.LPF 21 removes noise contribution from the simulation composite video signal, and resulting signal is outputed to synchronizing separator circuit 22.Extract synchronizing signal (H-SYNC and V-SYNC) the simulation composite video signal of synchronizing separator circuit 22 after removing denoising, and this synchronizing signal is offered digital video signal processing circuit 12.On the other hand, 11 pairs of simulations of ADC composite video signal carries out the AD conversion, and the composite video signal after digital translation is offered digital video signal processing circuit 12.The synchronizing signal that digital video signal processing circuit 12 utilizes by synchronizing separator circuit 22 correct regeneration generates the digital rgb signal, and is exported from digital composite video signal.
According to above-described present embodiment, obtained following effect.Just, the simulation composite video signal of being imported is being carried out the AD conversion, composite video signal after the digitlization is implemented in the video processing circuit of vision signal processing, the composite video signal after the AD conversion is not carried out separated in synchronization, but utilize analog filter from the simulation composite video signal, to remove radio-frequency component, and resulting signal is carried out separated in synchronization.Therefore, the net synchronization capability in the time of for the digital video transcoding device 80 in past, can improving weak electric field, thus can when weak electric field, obtain correct synchronizing signal.Consequently, can weaken owing to the asynchronous picture that causes trembles.In addition, owing to can use correct synchronizing signal, thereby can carry out the regeneration of signals such as luminance signal and colour signal well.
In addition, in video processing circuit (digital video transcoding device) with the AD converter of the simulation composite video signal of being imported being carried out the AD conversion and the digital video signal processing circuit that the digitized composite video signal enforcement vision signal by this AD converter is handled, the composite video signal after the AD conversion is not carried out separated in synchronization in inside, but from utilizing analog filter to remove radio-frequency component the composite video signal, and resulting signal is carried out receive in the external circuit of separated in synchronization the supply of synchronizing signal from simulation.Thus, according to present embodiment, the net synchronization capability in the time of for the digital video transcoding device 80 in past, can improving weak electric field, thus can when weak electric field, obtain correct synchronizing signal.Consequently, can weaken owing to the asynchronous picture that causes trembles.In addition, owing to can use correct synchronizing signal, thereby can carry out the regeneration of signals such as luminance signal and colour signal well.
[second execution mode]
Fig. 4 is the block diagram that illustrates according to the structure of the video processing circuit 2 of second execution mode.This video processing circuit 2 is to generate 3 primary colors (RGB) signal of numeral and the circuit of output according to the simulation composite video signal from the outside input.
In Fig. 4, video processing circuit 2 has AD converter (ADC) 111, digital synchronous split circuit 112, digital video signal processing circuit 113, input terminal 114 and selector 115.In a preferred embodiment, video processing circuit 2 is the digital video transcoding devices that are made of digital IC.In this structure, be imported among the ADC111 from the simulation composite video signal of outside.
The simulation composite video signal that ADC 111 conversions are imported offers digital synchronous split circuit 112 and digital video signal processing circuit 113 with the digital composite video signal that obtains.
Digital synchronous split circuit 112 is from separating synchronizing signal from the digital composite video signal that ADC 111 provides, and resulting synchronizing signal is offered digital video signal processing circuit 113 via the described selector 115 in back.Here, synchronizing signal is horizontal-drive signal (H-SYNC) and vertical synchronizing signal (V-SYNC).An example of the structure of digital synchronous split circuit 112 has been shown among Fig. 5.But, as digital synchronous split circuit 112, the various types of digital synchronous split circuits of cicada are not done special restriction to the type of the related digital synchronous split circuit 112 of present embodiment.Below, the digital synchronous split circuit 112 shown in Fig. 5 is described.In addition, in the following description, the simulation composite video signal is made as the TV signal of TSC-system formula.
In Fig. 5, digital synchronous split circuit 112 comprises wave digital lowpass filter (digital LPF) 130, comparator 131, PLL circuit 132, frequency divider 133, vertical synchronization split circuit 134 and switching circuit 135.
Numeral LPF 130 receives the supply of the composite video signal of numeral from ADC 111, and removes radio-frequency component from this signal.Then, digital LPF 130 offers comparator 131 with resulting signal S0 '.
Comparator 131 cuts the composite video signal S0 ' that (restriction) provides from digital LPF 130 by clip level L1 ' in accordance with regulations, and separation signal S1 ' (C-SYNC) from composite video signal S0 '.Then, resulting signal S1 ' is offered PLL circuit 132 and vertical synchronization split circuit 134.
Because PLL circuit 132, frequency divider 133, vertical synchronization split circuit 134 and switching circuit 135 are identical with the parts (symbol 32～35) of the synchronizing separator circuit 22 shown in Fig. 2, therefore omit description of them.But, in the present embodiment, be included in the output signal (H-SYNC of regeneration) of the frequency divider 132d in the PLL circuit 132 and the output signal (V-SYNC of regeneration) of switching circuit 135 and all be output to selector 115.
Return Fig. 4, digital video signal processing circuit 113 is provided by the synchronizing signal (H-SYNC and V-SYNC) that provides from selector 115, the vision signal of being implemented regulation by ADC 111 digitized composite video signals is handled, generated the rgb signal of numeral, and output to the outside.Here, handle as the vision signal of regulation, the same with above-mentioned first embodiment, for example be that processing, Y/C separating treatment, colored demodulation process, the rgb signal that generates clamp pulse generates processing or the like.
As mentioned above, the video processing circuit 2 of present embodiment can utilize inner digital synchronous split circuit 112 to extract synchronizing signal, and utilizes this synchronizing signal to generate the digital rgb signal from the simulation composite video signal.That is to say that above-mentioned video processing circuit 2 plays a role as the digital video transcoding device separately.
Yet, as previously mentioned, utilizing digital synchronous split circuit 112 to carry out can not when weak electric field, obtaining correct synchronizing signal in the middle of the structure of separated in synchronization.Therefore, when weak electric field, will produce the problem that the problem of trembling such as so-called picture and so-called luminance signal or colour signal are not correctly regenerated.And as previously mentioned, for the separated in synchronization when the weak electric field, the simulation synchronizing separator circuit is better than digital synchronous split circuit performance.
So in the present embodiment, the net synchronization capability when improving weak electric field in order to make becomes possibility, video processing circuit 2 becomes the structure that can utilize the synchronizing signal that is obtained by the simulation synchronizing separator circuit of outside.Specifically, in video processing circuit 2, be provided with: the input terminal 114 that from the simulation synchronizing separator circuit of outside, receives the supply of synchronizing signal; With the selector 115 of selecting any one signal in synchronizing signal that obtains by digital synchronous split circuit 112 and the synchronizing signal that is input to input terminal 114.Below, particularly this structure is described.
Fig. 6 is the block diagram that the structure of the video processing circuit 3 that forms to video processing circuit 2 additional simulation synchronizing separator circuits 120 is shown.In Fig. 6, when being imported into ADC 111, also be imported into simulation synchronizing separator circuit 120 from the simulation composite video signal of outside.
Simulation synchronizing separator circuit 120 utilizes analog filter to remove radio-frequency component from the simulation composite video signal, separates synchronizing signal from resulting signal, and this synchronizing signal is offered the input terminal 114 of video processing circuit 2.Here, synchronizing signal is horizontal-drive signal (H-SYNC) and vertical synchronizing signal (V-SYNC), or the synthetic synchronizing signal (C-SYNC) with them after synthetic.
An example of the structure of simulation synchronizing separator circuit 120 has been shown among Fig. 7.But, as the simulation synchronizing separator circuit, the various types of simulation synchronizing separator circuits of cicada are not done special restriction to the type of the related simulation synchronizing separator circuit 120 of present embodiment.Below, the simulation synchronizing separator circuit 120 shown in Fig. 7 is described.In addition, in the following description, the simulation composite video signal is made as the TV signal of TSC-system formula.
In Fig. 7, simulation synchronizing separator circuit 120 comprises simulation low-pass filter (simulation LPF) 140, comparator 141, PLL circuit 142, frequency divider 143, vertical synchronization split circuit 144 and switching circuit 145.
Because comparator 141, PLL circuit 142, frequency divider 143, vertical synchronization split circuit 144 and switching circuit 145 are identical with the parts (symbol 31～35) of the synchronizing separator circuit 22 shown in Fig. 2, thereby omit description of them.But, in the present embodiment, be included in the output signal (H-SYNC of regeneration) of the frequency divider 142d in the PLL circuit 142 and the output signal (V-SYNC of regeneration) of switching circuit 145 and all be output to selector 115 via input terminal 114.
Return Fig. 6, be provided for selector 115 via the input terminal 114 of video processing circuit 2 by simulation synchronizing separator circuit 120 isolated synchronizing signals.Therefore, provide by digital synchronous split circuit 112 isolated synchronizing signals (below, be called " synchronizing signal Sd ") with by simulation synchronizing separator circuit 120 isolated synchronizing signals (below, be called " synchronizing signal Sa ") to selector 115.
Any one that selector 115 is selected among synchronizing signal Sd and the synchronizing signal Sa.For example, in the time being " 0 ", select synchronizing signal Sd from the numerical value of the register 116 of outer setting, when be " 1 ", selection synchronizing signal Sa.Then, selector 115 selected synchronizing signal Sd or Sa are outputed to outside in, also provide it to digital video signal processing circuit 113.
Synchronizing signal Sd or the Sa that provides from selector 115 is provided digital video signal processing circuit 113, the composite video signal of numeral implemented the vision signal of regulation and handled, and generates the rgb signal of numeral, and exported.
Next, the preferred occupation mode to video processing circuit 2 with said structure is described.
The user (for example, the manufacturer of television receiver) is better than under the situation of paying attention to net synchronization capability at the attention cost, additional in addition simulation synchronizing separator circuit 120, and the video processing circuit shown in Fig. 42 is carried on the television receiver as video decoder.In this case, if the numerical value of register 116 is set to " 0 ", then the synchronizing signal Sd that is extracted by digital synchronous split circuit 112 just is provided for digital video signal processing circuit 113.Thus, under this occupation mode, for the little vision signal of relative noise, correct synchronizing signal can be accessed, for the big vision signal of relative noise (weak electric field signal etc.), then correct synchronizing signal can not be obtained.
On the other hand, the user is better than under the attention condition of cost at the attention net synchronization capability, added simulation synchronizing separator circuit 120 in addition for video processing circuit 2, the video processing circuit shown in Fig. 63 is carried on the television receiver as video decoder.In this case, if the numerical value of register 116 is made as " 1 ", then the synchronizing signal Sa that is extracted by simulation synchronizing separator circuit 120 is provided for digital video signal processing circuit 113.Thus, under this occupation mode, for the big vision signal of relative noise (weak electric field signal etc.), also can access correct synchronizing signal.That is to say that the user can improve the net synchronization capability of digital video transcoding device by adding simulation synchronizing separator circuit 120 in addition.
, supposed to provide the situation of synchronizing signal Sd here, the timing with synchronizing signal Sd just designs digital video signal processing circuit 113 as benchmark.Therefore, the user determines inconsistent with respect to the timeliness of the synchronizing signal Sa of synchronizing signal Sd under the situation of other additional simulation synchronizing separator circuit 120.Specifically, select under the situation of synchronizing signal Sd owing to the output of switching selector 115 the user and select under the situation of synchronizing signal Sa, by the signal on the comparison appropriate location (for example, the output signal of selector 115) waveform, thus determine inconsistent with respect to the timeliness of the synchronizing signal Sa of synchronizing signal Sd.Then, the user regulates the various timing signals that generated by digital video signal processing circuit 113 to eliminate the inconsistent mode of this timeliness.Therefore, the timing signal that is preferably generated by digital video signal processing circuit 113 can carry out the timeliness adjusting.
Below, to the adjusting of above-mentioned timing signal, describe with the example that is adjusted to of the timing of clamp pulse.Fig. 8 is the block diagram of adjusting that is used to illustrate the timing of clamp pulse.
In Fig. 8, the clamp pulse generative circuit 113a that digital video signal processing circuit 113 is comprised is according to the synchronizing signal Sd or the Sa that provide from selector 115, to clamp circuit 150 output clamp pulses.Clamp circuit 150 provide clamp pulse during, will simulate composite video signal and be fixed to specified level.
Fig. 9 is the oscillogram of synchronizing signal and clamp pulse.In Fig. 9, synchronizing signal Sd has been shown in (a), the clamp pulse CPd that generates according to synchronizing signal Sd has been shown in (b).As shown in these figures, clamp pulse generative circuit 113a begins to produce clamp pulse CPd through behind the stipulated time t1 from the trailing edge of synchronizing signal Sd.Here, stipulated time t1 is predetermined in order to make clamp pulse CPd best execution clamping, and sets in register 113.
In Fig. 9, synchronizing signal Sa has been shown in (c), the clamp pulse CPa that generates according to synchronizing signal Sa has been shown in (d).As shown in these figures, synchronizing signal Sa with respect to synchronizing signal Sd only time of delay t2, thus clamp pulse CPa with respect to clamp pulse CPd also only time of delay t2.Because the delay of this clamp pulse might influence best clamper.Therefore, the user measures t2 time of delay of synchronizing signal Sa with respect to synchronizing signal Sd, and changes the set point of register 113b into (t1-t2) from t1.Thus, as shown in Fig. 9 (e), clamp pulse generative circuit 113a will produce clamp pulse CPa ' after beginning the elapsed time (t1-t2) from the trailing edge of synchronizing signal Sa.Consequently, can make the timing unanimity of the desirable clamp pulse CPd shown in same Fig. 9 of timing (b) of the clamp pulse CPa ' that generates according to synchronizing signal Sa.In addition, time of delay t2 mensuration for example be under the situation of register 116 being arranged to " 0 " and be arranged to observe under the situation of " 1 " synchronizing signal, clamp pulse or clamp circuit 150 output signal waveform and undertaken by more resulting waveform.
The video processing circuit 2 related according to above-described present embodiment obtained following effect.Promptly, the simulation composite video signal of being imported is being carried out the AD conversion and digitized composite video signal is being implemented in the video processing circuit of vision signal processing, owing to be provided with the input terminal 114 that receives the supply of synchronizing signal from the external analog synchronizing separator circuit, therefore can improve the net synchronization capability when weak electric field, wherein the external analog synchronizing separator circuit utilizes analog filter to remove radio-frequency component from the simulation composite video signal, and separates synchronizing signal from resulting signal.
In addition, because in input terminal 114 with the supply that from the simulation synchronizing separator circuit, receives synchronizing signal, also have digital synchronous split circuit 112 and select to be provided to the synchronizing signal of input terminal 114 and one of them selector 115 of the synchronizing signal that obtains by digital synchronous split circuit 112, therefore the user can select following two kinds of occupation modes, that is: (A) is not provided with the occupation mode of simulating synchronizing separator circuit and carry out the attention cost of separated in synchronization in digital synchronous split circuit 112; (B) be provided with the occupation mode of simulating synchronizing separator circuit and in the simulation synchronizing separator circuit, carrying out the attention net synchronization capability of separated in synchronization.
In addition, because when having input terminal 114, also have digital synchronous split circuit 112 and selector 115, thereby when utilizing the simulation synchronizing separator circuit to select synchronizing signal and when utilizing digital synchronous split circuit 112 to select synchronizing signal, by comparing the waveform of synchronizing signal and clamp pulse etc., can be with respect to determining that by digital synchronous split circuit 112 resulting synchronizing signals the timeliness by the resulting synchronizing signal of simulation synchronizing separator circuit is inconsistent.And, simulate synchronizing separator circuit and digital video signal processing circuit 113 etc. by regulating, thereby can compensate by the timeliness of the resulting synchronizing signal of simulation synchronizing separator circuit inconsistent according to definite result.
In addition, the video processing circuit 3 related according to present embodiment just according to the structure of having added simulation synchronizing separator circuit 120 in video processing circuit 2, obtained following effect.Promptly, owing to the simulation composite video signal of being imported is being carried out the AD conversion and digitized composite video signal is being implemented in the video processing circuit of vision signal processing, be provided with and utilize analog filter from the simulation composite video signal, to remove radio-frequency component and from resulting signal, separate the simulation synchronizing separator circuit 120 of synchronizing signal, therefore can utilize simulation synchronizing separator circuit 120 to obtain correct synchronizing signal, thereby can improve the net synchronization capability when weak electric field.
In addition, owing to have simulation synchronizing separator circuit 120, digital synchronous split circuit 112, selector 115, thereby under this condition, can switch use by simulation synchronizing separator circuit 120 resulting synchronizing signals with by digital synchronous split circuit 112 resulting synchronizing signals.For example, for the little signal of relative noise, preferably use, and for the big signal of relative noise (weak electric field signal etc.), preferably use by simulation synchronizing separator circuit 120 resulting synchronizing signals by digital synchronous split circuit 112 resulting synchronizing signals.Illustrated among Figure 10 and had the structure of video processing circuit 4 of switching the function of synchronizing signal according to noisiness.In Figure 10, video processing circuit 4 has the noise detector 160 that detects the noisiness that is comprised in the simulation composite video signal.And selector 115 is selected synchronizing signal according to the testing result of noise detector 160.Specifically, utilizing noise detector 160 detected noisinesses not reach under the situation of specified level, selector 115 is selected by digital synchronous split circuit 112 resulting synchronizing signals, and under the situation more than the specified level, select by simulation synchronizing separator circuit 120 resulting synchronizing signals.
Moreover, the invention is not restricted to above-mentioned execution mode, in the scope that does not break away from purport of the present invention, can make various distortion.For example, in the above-described first embodiment, synchronizing separator circuit 22 also can offer digital video signal processing circuit 12 as synchronizing signal with C-SYNC.In this case, owing in synchronizing separator circuit 22, do not need from C-SYNC, to isolate H-SYNC and V-SYNC, thereby in Fig. 2, can omit the circuit except that comparator 31.Thus, must be useful on the circuit (for example, 32～35 of Fig. 2) of from C-SYNC, isolating H-SYNC and V-SYNC in digital video signal processing circuit 12 1 sides.
In addition, in the above-described 2nd embodiment, simulation synchronizing separator circuit 120 also can offer video processing circuit 2 as synchronizing signal with C-SYNC.In this case, owing to do not need from C-SYNC, to isolate H-SYNC and V-SYNC in the synchronizing separator circuit 120, thereby in Fig. 7, can omit and remove the part of simulating LPF 140 and the comparator 141 in simulation.Thus, must be useful on the circuit (for example, 142～145 of Fig. 7) of from C-SYNC, isolating H-SYNC and V-SYNC in video processing circuit 2 one sides.
In addition, in the above-described 2nd embodiment, when selecting, also can stop the operation of digital synchronous split circuit 112 by simulation synchronizing separator circuit 120 resulting synchronizing signals.On the contrary, when selecting, also can stop to simulate the operation of synchronizing separator circuit 120 by digital synchronous split circuit 112 resulting synchronizing signals.
In addition, in above-mentioned first and second execution modes, digital video signal processing circuit 12,113 preferably is used to generate the circuit of digital rgb signal, but is not limited to this, also can be the circuit that is used for the composite video signal of numeral is implemented the use synchronization signal processing.For example, digital video signal processing circuit 12,113 also can be the circuit that is used to generate luminance signal and colour signal and output, the circuit that is used to generate luminance signal and color difference signal and output, or generates circuit of clamp pulse and output or the like.
Claims (8)
1. video processing circuit, the simulation composite video signal of luminance signal, colour signal and synchronizing signal has been synthesized in its reception at least, it is characterized in that, comprising:
Analog filter, it removes radio-frequency component from above-mentioned simulation composite video signal;
Synchronizing separator circuit, it separates above-mentioned synchronizing signal from the output signal of above-mentioned analog filter;
AD converter, it carries out the AD conversion to above-mentioned simulation composite video signal; With
Digital video signal processing circuit, it utilizes the above-mentioned synchronizing signal that is obtained by above-mentioned synchronizing separator circuit, from generate the tricolor signal of numeral through the digitized composite video signal of above-mentioned AD converter.
2. video processing circuit, the simulation composite video signal of luminance signal, colour signal and synchronizing signal has been synthesized in its reception at least, it is characterized in that,
Also receive from by utilizing analog filter from above-mentioned simulation composite video signal, to remove isolated above-mentioned synchronizing signal in the signal that radio-frequency component obtains; This video processing circuit comprises:
AD converter, it carries out the AD conversion to above-mentioned simulation composite video signal; With
Digital video signal processing circuit, it utilizes above-mentioned synchronizing signal, from generate the tricolor signal of numeral through the digitized composite video signal of above-mentioned AD converter.
3. video processing circuit, the simulation composite video signal of luminance signal and synchronizing signal has been synthesized in its reception at least, and this simulation composite video signal is handled, and it is characterized in that, comprising:
AD converter, it carries out the AD conversion to above-mentioned simulation composite video signal;
The digital synchronous split circuit, it is from separating synchronizing signal through the digitized composite video signal of above-mentioned AD converter;
Input terminal, it receives outside simulation synchronizing separator circuit and utilizes analog filter to remove the supply of isolated synchronizing signal in the signal that obtains behind the radio-frequency component from above-mentioned simulation composite video signal;
Selector, it is selected by the resulting synchronizing signal of above-mentioned digital synchronous split circuit and is provided in the synchronizing signal of above-mentioned input terminal any one; With
Digital video signal processing circuit, it utilizes the synchronizing signal of being selected by above-mentioned selector, and the vision signal of implementing regulation through the digitized composite video signal of above-mentioned AD converter is handled.
4. video processing circuit according to claim 3 is characterized in that,
Comprise noise detector, it detects the noisiness that above-mentioned simulation composite video signal is comprised,
Above-mentioned selector is selected synchronizing signal according to the testing result of above-mentioned noise detector.
5. video processing circuit according to claim 4 is characterized in that, the noisiness that is comprised when above-mentioned simulation composite video signal is defined threshold when above, and above-mentioned selector is selected by the resulting synchronizing signal of above-mentioned simulation synchronizing separator circuit.
6. video processing circuit, the simulation composite video signal of luminance signal and synchronizing signal has been synthesized in its reception at least, and this simulation composite video signal is handled, and it is characterized in that, comprising:
AD converter, it carries out the AD conversion to above-mentioned simulation composite video signal;
The digital synchronous split circuit, it is from separating synchronizing signal through the digitized composite video signal of above-mentioned AD converter;
The simulation synchronizing separator circuit, it utilizes analog filter to remove radio-frequency component from above-mentioned simulation composite video signal, and separates synchronizing signal from resulting signal;
Selector, it is selected by the resulting synchronizing signal of above-mentioned digital synchronous split circuit with by in the resulting synchronizing signal of above-mentioned simulation synchronizing separator circuit any one; With
Digital video signal processing circuit, it utilizes the synchronizing signal of being selected by above-mentioned selector, and the vision signal of implementing regulation through the digitized composite video signal of above-mentioned AD converter is handled.
7. video processing circuit according to claim 6 is characterized in that,
Comprise noise detector, it detects the noisiness that above-mentioned simulation composite video signal is comprised,
Above-mentioned selector is selected synchronizing signal according to the testing result of above-mentioned noise detector.
8. video processing circuit according to claim 7 is characterized in that, when noisiness that above-mentioned simulation composite video signal comprised is the threshold value of regulation when above, above-mentioned selector is selected by the resulting synchronizing signal of above-mentioned simulation synchronizing separator circuit.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004292132A JP2006109029A (en) | 2004-10-05 | 2004-10-05 | Video signal processing circuit |
| JP2004292132 | 2004-10-05 | ||
| JP2004292645 | 2004-10-05 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1774036A CN1774036A (en) | 2006-05-17 |
| CN100405821C true CN100405821C (en) | 2008-07-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101291698A Expired - Fee Related CN100405821C (en) | 2004-10-05 | 2005-10-08 | Video signal processing circuit |
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| Country | Link |
|---|---|
| JP (1) | JP2006109029A (en) |
| CN (1) | CN100405821C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105933574B (en) * | 2016-05-20 | 2019-05-21 | 南京邮电大学 | It goes in video, the separation system of field sync signal |
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| US5225908A (en) * | 1991-01-12 | 1993-07-06 | Samsung Electronics Co., Ltd. | Video signal recording apparatus for electronic camera |
| JPH0884320A (en) * | 1994-09-13 | 1996-03-26 | Hitachi Ltd | Video disk reproduction device and display system using it |
| JPH09163291A (en) * | 1995-12-11 | 1997-06-20 | Nec Corp | Image synchronous control display device |
| US5777686A (en) * | 1994-06-30 | 1998-07-07 | Agfa-Gevaert N.V. | Video frame grabber comprising analog video signals analysis system |
| CN1331548A (en) * | 2000-06-26 | 2002-01-16 | 张培忠 | Symmetric TV image encryption/decryption device by line disturbance in whole frame |
| CN1510917A (en) * | 2002-12-25 | 2004-07-07 | 乐金电子（沈阳）有限公司 | Digital TV inputting signal processor |
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| JPH089190A (en) * | 1994-06-15 | 1996-01-12 | Hitachi Ltd | Synchronization discrimination circuit |
| JP4461522B2 (en) * | 1999-09-20 | 2010-05-12 | パナソニック株式会社 | Horizontal sync separator |
| JP4472098B2 (en) * | 2000-03-31 | 2010-06-02 | シャープ株式会社 | Synchronization signal processing circuit and display device |
| JP2002278495A (en) * | 2001-03-16 | 2002-09-27 | Fujitsu General Ltd | Sampling phase adjusting circuit |
| JP2003087602A (en) * | 2001-09-07 | 2003-03-20 | Fujitsu General Ltd | Video signal processing circuit |
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2004
- 2004-10-05 JP JP2004292132A patent/JP2006109029A/en active Pending
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- 2005-10-08 CN CNB2005101291698A patent/CN100405821C/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5225908A (en) * | 1991-01-12 | 1993-07-06 | Samsung Electronics Co., Ltd. | Video signal recording apparatus for electronic camera |
| US5777686A (en) * | 1994-06-30 | 1998-07-07 | Agfa-Gevaert N.V. | Video frame grabber comprising analog video signals analysis system |
| JPH0884320A (en) * | 1994-09-13 | 1996-03-26 | Hitachi Ltd | Video disk reproduction device and display system using it |
| JPH09163291A (en) * | 1995-12-11 | 1997-06-20 | Nec Corp | Image synchronous control display device |
| CN1331548A (en) * | 2000-06-26 | 2002-01-16 | 张培忠 | Symmetric TV image encryption/decryption device by line disturbance in whole frame |
| CN1510917A (en) * | 2002-12-25 | 2004-07-07 | 乐金电子（沈阳）有限公司 | Digital TV inputting signal processor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2006109029A (en) | 2006-04-20 |
| CN1774036A (en) | 2006-05-17 |
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