CN1331548A - Symmetric TV image encryption/decryption device by line disturbance in whole frame - Google Patents
Symmetric TV image encryption/decryption device by line disturbance in whole frame Download PDFInfo
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- CN1331548A CN1331548A CN 00118540 CN00118540A CN1331548A CN 1331548 A CN1331548 A CN 1331548A CN 00118540 CN00118540 CN 00118540 CN 00118540 A CN00118540 A CN 00118540A CN 1331548 A CN1331548 A CN 1331548A
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Abstract
A encryter/decrypter for TV image is disclosed. The active image parts of lines in a frame are mutually exchanged according to pedefined random order to obtain encrypted TV signals conforming the system standard (PAL or NTSC). The decrypter can restore the signals back to original signals in same way. Their random orders are symmetrical and the encrypter can be also used as its decrypter.
Description
The present invention relates to a kind of TV image enciphering/deciphering device, belong to TV technology.
At present, be toll administration, many satellite TVs, the closed-circuit television charging channel uses enciphering/deciphering equipment, and encryption device is installed on TV station, and decryption device is installed on user side.The said equipment can be divided into analog form and digital form two classes again.To the enciphering/deciphering of baseband signal, analog form is realized the TV signal nonstandardized technique of standard; Digital form has line disturbance, line displacement, row segmentation cutting, row inversion etc.Analog form is big to the video image damage, and deciphering easily; Digital form is then because little to video image damage, deciphering difficulty and being approved.The said equipment for digital enciphering/deciphering device, is principal and subordinate's working method, and encryption device is a main frame, and decryption device is a slave; Main frame is encrypted image, and key is passed to slave, slave according to key with visual decryption restoration.Its asymmetry of principal and subordinate's property decision, the host complex costliness works in building environment; Slave is simple relatively.The control encrypted random number is not according to there being a symmetrical feature, if thereby decipher leave encryption equipment, with utterly useless.TV signal after the encryption owing to comprise control key, can't be stored with common video tape recorder.In sum, existing enciphering/deciphering device is applicable to the satellite or the closed-circuit television field of general charge purpose.
In many close-circuit television,closed-circuft televishons are used, beholder, operator there is different security classification requirements.As bank vault is monitored, the general operation personnel can only have the video operation permission, must not watch interior details; And professional guard can only watch details, can not operate video.This just need carry out enciphering/deciphering and handle the signal of live camera.Encryption equipment is installed at the scene, the monitor camera video image signal is encrypted the back transmission, the vision signal of encryption is still the signal of standard, and available common video tape recorder is recorded, but watches the meaning that can not understand image on monitor; Have only and use corresponding decipher, after encrypting the picture intelligence deciphering, just can watch and the consistent TV image of original tv image.
Purpose of the present invention just provides the enciphering/deciphering device that satisfies above-mentioned application.
The present invention is achieved in that and respectively is provided with a circuit board in the enciphering/deciphering device machine, be embedded with video simulation digital quantizer A/D on the circuit board, digital video analog converter D/A, frame memory RAM, data buffering sequential and logic control circuit, row is disturbed the preface memory, synchronizing separator circuit, phase-locked clock circuit.Data buffering sequential and logic control circuit adopt asic chip to realize.Foregoing circuit is the center with the asic chip, connects.Video simulation digital quantizer A/D sends the video signal digitization of simulation into the input-buffer of asic chip; Asic chip frame memory is carried out addressing; Asic chip is read the frame memory data, is written to output buffers; Asic chip is written to frame memory with the input-buffer data; Asic chip is written to digital video analog converter D/A with the output buffers data; Said process is with the pipeline system synchronous working.
Enciphering/deciphering process of the present invention is to disturb changing frame by frame of preface read-write by row order read-write/row to realize that the read-write of row order is as row address read-write operation to be carried out in the frame memory addressing according to the linage-counter value; It is to disturb the preface memory according to row counting sequence addressed row that row is disturbed preface read-write, obtains to disturb order sequenced data and makes row address read-write operation is carried out in the frame memory addressing.The conversion frame by frame of disturbing preface read-write is read and write/gone to above line in proper order, and what sequence frames was read is to disturb the data that the preface frame writes, and what disturb that the preface frame reads is the data that sequence frames writes.If row is disturbed in the preface memory stores data sequence, X unit storage data Y, Y unit storage data X then passes through above-mentioned ciphering process, and arbitrary frame image shows the capable content of Y when X is capable, show the capable content of X when Y is capable; Above-mentioned exchange is at random and a large amount of, and encrypted image is beyond recognition content.Decrypting process is the same with ciphering process, exchanges the capable and capable content of Y of X once more, obtains with the same image of original picture content.Disturbing order sequenced data is the random number series of one group of symmetry, is stored in row in advance and disturbs in the preface memory.
Below in conjunction with drawings and Examples, introduce the present invention's (at PAL D system) in detail.
Fig. 1 is a systematic square frame schematic diagram of the present invention.
Fig. 2 is that ASIC controller address ram of the present invention forms block diagram.
Fig. 3 is a duty cycle block diagram of the present invention.
Fig. 4 is an example of the present invention figure, and wherein asic chip customizes to Actel company.Its label meaning is consistent with Fig. 1.
Fig. 5 is a kind of outline drawing of apparatus of the present invention.The 17th, video inputs, the 18th, video output terminals, the 19th, power input.
Please refer to Fig. 1, Fig. 1 is a system diagram of the present invention, comprises analog-digital converter (A/D) 1, frame memory 2, and digital analog converter (D/A) 3, sequencing control, data buffering ASIC4, row is disturbed preface memory 5, clock generator 6, sync separator 7.
TV signal input analog-digital converter (A/D) 1 is converted to digital signal, transports to the input-buffer of ASIC4; 4 pairs of frame memory 2 addressing of ASIC; With the data of storing originally, read output buffers; ASIC 4 writes frame memory 2 with the data of input-buffer; ASIC 4 writes digital analog converter (D/A) 3 with the data of output buffers.Said process is by pipeline system work.
Please refer to Fig. 2, Fig. 2 is the order of ASIC of the present invention 4 inside/disturb the preface row address to form part, comprises linage-counter 8, row sequence address latch 9, and address bus selector control logic circuit 10, row is disturbed sequence address latch 11, address bus selector 12.
Every frame begins, linage-counter 8 zero clearings, and to the row count count value write sequence address latch 9; The row of 9 couples of Fig. 1 of sequence address latch is disturbed 5 addressing of preface memory, obtains row and disturbs order sequenced data and write and disturb sequence address latch 11; By address bus selector 12 selecting sequence address latchs 9 or disturb sequence address latch 11 output.
The Dot Clock counter combines with address bus selector 12 to finish frame memory 2 is carried out addressing.
During sequential system work, address bus selector 12 is exported sequence address latch 9 data all the time;
During the work of disorderly sequential mode, the synchronous blanking of row period, address bus selector 12 output sequence address latchs 9 data; Efficient image period, sequence address latch 11 data are disturbed in 12 outputs of address bus selector.Blanking synchronously period, determined by the Dot Clock Counter Value.
The present invention disturbs order sequenced data and is stored in row in advance and disturbs in the preface memory 5, disturb order sequenced data and be one group of arithmetic progression 0,1 ..., 623, the random alignment again of 624} has following queueing discipline:
Except that the synchronous blanking of field synchronization be expert at fixing, the ordered series of numbers element can exchange the position at random one time, but after the exchange once, must not move again.
According to this rule, produce such result: then must place data X in the Y position if data Y is placed in the X position.Can be with X=Y, as a kind of special exchanged form.Therefore, disturb in the preface memory 5 and have:
574
*(574-2)
*(574-2
*2)
* *(574-2
*N),
* *2 kinds of possibilities.(annotate: 1. do not comprise the X=Y situation;
2. a frame image comprises 625 row, and parity field respectively has the synchronous and black-out intervals of 25 behavior fields, has 575 row to comprise pictorial information and can disturb preface.)
The present invention carries out enciphering/deciphering work by Fig. 3 circulation.
Row sequential read 13, row sequential write 14, row is disturbed preface and is read 15, and row is disturbed preface and is write 16.
If the n frame is the row sequential system, by row sequential addressing frame memory 2, order reads pictorial data, writes digital analog converter (D/A) 3; The data sequential write that analog-digital converter (A/D) 1 produces is gone into frame memory 2; For frame memory 2, when X was capable, addressing X was capable, write the capable content of X; When Y was capable, addressing Y was capable, write the capable content of Y;
The n+1 frame is disturbed sequential mode for row, by disturbing preface addressing frame memory 2, disturbs preface and reads pictorial data, exports digital analog converter (D/A) 3 to; The data that analog-digital converter (A/D) 1 produces are disturbed preface and are write frame memory 2; When X was capable, addressing Y was capable, and the capable content of output n frame Y writes the capable content of n+1 frame X; When Y was capable, addressing X was capable, and the capable content of output n frame X writes the capable content of n+1 frame Y; Therefore, D/A output be TV image signal after previous frame (n frame) row is disturbed preface, the capable content of output n frame Y when promptly X is capable, and Y capable content of output n frame X when capable.
The n+2 frame is for getting back to the sequential system of n frame again, and by row sequential addressing frame memory 2, the row order reads pictorial data, writes digital analog converter (D/A) 3; The data that analog-digital converter (A/D) 1 produces are gone into frame memory 2 by the row sequential write; When X was capable, addressing X was capable, and the capable content of output n+1 frame Y writes the capable content of n+2 frame X; When Y was capable, addressing Y was capable, and the capable content of output n+1 frame X writes the capable content of n+2 frame Y; Therefore, D/A output is still TV image signal after previous frame (n+1 frame) row is disturbed preface, the capable content of output n+1 frame Y when promptly X is capable, and Y capable content of output n+1 frame X when capable.
Row, field synchronization black-out intervals signal are not disturbed preface all the time, and be promptly consistent with original picture.
Said process moves in circles, and normal TV image row reconfigures with the order of disturbing 5 storages of preface memory, and promptly the capable content of the capable Y of X exchanges, the scrambled TV service image that acquisition can not understanding content.
Decrypting process exchanges the capable content of the capable Y of above-mentioned X once more with the same manner work, obtains the TV image of original contents.
The enciphering/deciphering process is symmetrical, a pair of enciphering/deciphering device, and the content of disturbing 5 storages of preface memory is the same.This consistency decision scrambled TV service image can encrypted device deciphering itself.
Above disclosure of the Invention should not be considered as a kind of restriction, and those skilled in the art when seeing the present invention, can know the correction and the change of a lot of apparatus of the present invention by inference: for example: can change NTSC into, Sequential Color and Memory system with being suitable for television system; ROM can be changed into EPROM, EEPROM, NVROM, serial EEPROM or ROM is put in the ASIC, is put in the MCU; Two device serial connections of the present invention can be used, obtain more scrambling combination; Also can three devices of the present invention are in parallel, be used for the encryption of component vide image.In view of the above, foregoing invention openly should be interpreted as limited by claims.
Compared with prior art, following advantages of the present invention: 1. the enciphering/deciphering device can be made living two single-ended black boxes, be single-ended advance single-ended Go out, need not anyly set; Enciphered data is solidified in hardware circuit, and is easy to use and reliable. 2. the capable order of disturbing of full frame, combined method is many, can't steal secret information by the analytic signal way. 3. the enciphering/deciphering device is interchangeable, can use flexibly, and cost is low.
Therefore, apparatus of the present invention are applicable to the occasion of special-purpose video image security applications, such as silver The row national treasury is monitored, and uses the city video monitoring of public network, the encrypting storing of camera tape.
Claims (7)
1. TV image enciphering/deciphering device comprises:
A simulated image digitalizer A/D is used for from gamma camera the analog picture signal digitlization of equipment such as player;
A random storage device (RAM) is used to store the digitized picture of a frame;
A digital conversion of signals becomes the device (D/A) of analog signal, and the digital signal that is used for encrypting (or deciphering) processing transfers analog picture signal to;
A control device is used to produce the control logic and the control timing of said apparatus;
One group of auxiliary circuit is used for audio video synchronization and separates, and system clock produces;
It is mobile to it is characterized in that frame by frame efficient image with standard television image (Phase Alternation Line system or TSC-system) scan line partly exchanges mutually by predetermined pseudorandom order, and arbitrary row can only move once (or 0 time).
2. according to the described TV image enciphering/deciphering of claim 1. device, it is characterized in that the address of random storage device (RAM) is organized into groups by visual ranks; Be listed as addressing in order; The efficient image part, the row addressing in order/disturb preface to change frame by frame; The addressing of other parts (blanking synchronously) row is carried out in order; To the memory cell write-after-read, sense data writes D/A, and the A/D data write this unit then.
3. according to the described TV image enciphering/deciphering of claim 2. device, it is characterized in that default random data is arranged, the control row is disturbed preface.
4. according to the described random data preinstall apparatus of claim 3., it is characterized in that as n unit deposit data m, then m unit deposit data n; In other words, the symmetry exchange is deposited at random; For the row at field synchronization, blanking place, n=m.
5. according to the described TV image enciphering/deciphering of claim 3. device, it is characterized in that a pairing decryption device of encryption device, its default random data is just the same; In other words, the pairing decryption device of encryption device can be just the same.
6. according to the described TV image enciphering/deciphering of claim 5. device, it is characterized in that the signal after the encryption and decryption still meets former standard, in other words, the picture intelligence behind available standard compliant traditional video tape recorder recording of encrypted.
7. according to the described TV image enciphering/deciphering of claim 6. device, it is characterized in that device output be the capable symmetry of image of previous frame input disturb after the preface vision signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 00118540 CN1331548A (en) | 2000-06-26 | 2000-06-26 | Symmetric TV image encryption/decryption device by line disturbance in whole frame |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 00118540 CN1331548A (en) | 2000-06-26 | 2000-06-26 | Symmetric TV image encryption/decryption device by line disturbance in whole frame |
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| CN1331548A true CN1331548A (en) | 2002-01-16 |
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| CN 00118540 Pending CN1331548A (en) | 2000-06-26 | 2000-06-26 | Symmetric TV image encryption/decryption device by line disturbance in whole frame |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100405821C (en) * | 2004-10-05 | 2008-07-23 | 三洋电机株式会社 | Video signal processing circuit |
| US7456903B2 (en) | 2004-10-05 | 2008-11-25 | Sanyo Electric Co., Ltd. | Video signal processing circuit |
| CN109327306A (en) * | 2018-09-20 | 2019-02-12 | 国家体育总局体育科学研究所 | A kind of data transmission method and system based on fixed message length |
-
2000
- 2000-06-26 CN CN 00118540 patent/CN1331548A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100405821C (en) * | 2004-10-05 | 2008-07-23 | 三洋电机株式会社 | Video signal processing circuit |
| US7456903B2 (en) | 2004-10-05 | 2008-11-25 | Sanyo Electric Co., Ltd. | Video signal processing circuit |
| CN109327306A (en) * | 2018-09-20 | 2019-02-12 | 国家体育总局体育科学研究所 | A kind of data transmission method and system based on fixed message length |
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