CN100405377C - Analog circuit data array description method - Google Patents
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- CN100405377C CN100405377C CNB2005100638761A CN200510063876A CN100405377C CN 100405377 C CN100405377 C CN 100405377C CN B2005100638761 A CNB2005100638761 A CN B2005100638761A CN 200510063876 A CN200510063876 A CN 200510063876A CN 100405377 C CN100405377 C CN 100405377C
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Abstract
The present invention provides an analog circuit data array description method which relates to the technical field of analog circuit design automation. 1, 16 sub circuits are summarized by experience, a topological property data array, a topological structure data array and a topological port data array are respectively used for describing the devices properties of each sub circuit, the topological connection relation and the port properties of the sub circuits; 2, during the description of an analog circuit, the 16 sub circuits are used as the reference, and devices of the analog circuit are divided into a plurality of circuit modules; 3, when the present invention is used for the topological automatic generation design of an operational amplifying circuit, the sub circuit port properties described by the topological port data array of the 16 sub circuits and the sub circuit device properties described by the topological property data array are used as the reference, and the topological automatic generation of the operational amplifying circuit is realized through editing the topological structure data array. The present invention can describe most of analog circuits, and has wide application range.
Description
Technical field
The present invention relates to the Analog Circuit Design technical field of automation, propose a kind of analog circuit data array description method.
Background technology
The Analog Circuit Design cycle is long, and requires the deviser to possess the characteristics of enough circuit base knowledge and the Analog Circuit Design experience of enriching, and becomes the obstacle that Analog Circuit Design develops.And one of method that solves these obstacles is exactly to realize the automatic Synthesis of mimic channel.Another problem of the thing followed is exactly in the mimic channel automatic Synthesis, how to describe mimic channel.
In the existing circuit automatic Synthesis algorithm, when utilizing genetic algorithm to carry out the design of mimic channel automatic Synthesis, adopt linear ordered series of numbers to describe mimic channel; When utilizing neural network to realize the design of mimic channel automatic Synthesis, mimic channel is described by the connection between the neuron of the device in the representative simulation circuit.These methods of describing mimic channel can only be reduced to the multiterminal device two terminal device and handle when realizing the connectivity problem of multiterminal devices (for example transistor), thereby are difficult to design complicated circuit structure, to satisfy the high performance requirements of user to circuit.
Summary of the invention
The objective of the invention is to, propose a kind of simple mimic channel describing method, can describe most mimic channels, and can realize that circuit topology generates automatically.Here propose a kind of analog circuit data array description method, can describe mimic channel easily; This circuit describing method is applied in the design of discharge circuit automatic Synthesis, the collaborative circuit design rule that proposes, can solve the connectivity problem of multiterminal device easily, and under the prerequisite that does not generate the idle circuit structure, guarantee circuit design process closure, can generate high-quality circuit structure, and the circuit topological structure that generates can be converted into efficiently the output of net sheet form.
The present invention is a kind of analog circuit data array description method.The basis of this circuit describing method is the experience electronic circuit set shown in the subordinate list a.By research summary to a large amount of simulation discharge circuits, conclusion extracts 16 experience electronic circuits, (transistor is an example with the mos transistor in the table shown in subordinate list a, in like manner can be applied to bipolar transistor), each electronic circuit is described with topological property data array, topology data array and topological port data array respectively in the table.
The topological property data array (if this device is a transistor device, also comprises length, the width ratio coefficient of each transistor device with the numbering of matrix form descriptor device that circuit comprises, type.If length, width ratio coefficient equal 0, for example ga output stage electronic circuit, vf output stage electronic circuit and ga/vf output stage electronic circuit represent that this scale-up factor is invalid.), its data array description grammer is as shown in table 1.Wherein, device number is the positive integer of inequality.Type of device sign indicating number value is that { 0,1,2,3,4,5,6} distinguishes corresponding { 0 → n channel transistor device, 1 → p channel transistor device, 2 → electric capacity, 3 → resistance, 4 → diode, 5 → independent voltage source, 6 → independent current }.
Topology data array descriptor circuit topology connects situation, and the data array description grammer is as shown in table 1.1～15 electronic circuit all comprises transistor device, when describing circuit, transistor device can be handled as four-terminal device or three terminal device (substrate links to each other with source electrode), uses 4x1 matrix or 3x1 matrix representation respectively; In the design of discharge circuit automatic Synthesis, transistor device is handled as three terminal device (substrate links to each other with source electrode), use the 3x1 matrix representation.The 16th electronic circuit is the two terminal device electronic circuit, topology data array 2x1 matrix representation.When describing electric capacity (perhaps resistance), the every row element of matrix is represented a port of this device; When describing diode (perhaps independent current source), first row element of matrix is represented forward voltage end (perhaps electric current flows into end), and second row element is represented negative voltage end (perhaps electric current outflow end).
The port character of topology port data array descriptor circuit.1～15 electronic circuit topology port character is described by 16 kinds of port types that provide in the table 2.The form of 1～15 electronic circuit topology port data array is according to from top to bottom, order from left to right is each transistor device in the descriptor circuit successively, and the character of port of every line description electronic circuit (not comprising transistorized substrate) of topological port data array.Wherein p/n channel transistor active pull-up electronic circuit comprises two topological port data arrays respectively, port character when first port data array is described this electronic circuit as active pull-up, the port character when second port data array described this electronic circuit and other electronic circuit composition biasing circuit.The 16th electronic circuit is the two terminal device electronic circuit, does not have the port property description, and port character data array is 0.
The present invention is when being applied to the generation of discharge circuit topology, and the topology design rule of use has following 8 points:
1. carry out before the topology design, the performance requirement that the user is proposed carries out performance evaluation, requires to drive the selection of topology design direction with circuit performance.
Totally nine kinds of the design directions of discharge circuit, by the structures shape of discharge circuit input stage, intergrade and output stage, as shown in table 3.Wherein GA (general amplifier) represents the common source amplifying circuit; CF (current follower) representative is the grid circuit altogether; VF (voltage amplifier) representative is drain circuit altogether.Number design direction shown in 1,2 in the table 3 and generate two stage amplifer, design direction generates three grades of amplifiers shown in the numbering 3～8, and design direction can generate multistage amplifier shown in the numbering 9.
Circuit performance requirement according to user's proposition, every kind of amplifier topology design direction selects the highest amplifier input stage, intergrade, the output stage structure of grade of fit to generate direction as circuit topology to the grade of fit of customer requirements from gain, bandwidth, noise, slewing rate, supply voltage, output voltage range, seven aspect reckoners 3 of load driving ability.The computing formula of topology grade of fit is as follows:
Wherein:
F
iRepresent the appropriateness of every kind of amplifier structure type, φ
jRepresent the harsh degree of j performance requirement, performance requirement is high more, φ
jMore near 1.f
SminjAnd f
SmaxjBe respectively the minimum value and the maximal value of j performance requirement, f
jBe user-defined j performance requirement numerical value.
2. as shown in Figure 2, by the indication of circuit design direction, according to the order generative circuit of amplifier input stage, intergrade, output stage, current source/circuit trap, active pull-up.
According to the order from the input stage to the active pull-up, the conventional amplifier topological structure of generation as shown in Figure 4.But in design process, the input stage of having only circuit is to exist, and the design of other each several part can be accepted or rejected according to the design direction that adopts.Circuit for example shown in Figure 6 only comprises input stage, intergrade, current source, current sink and active pull-up, is a simple two stage amplifer circuit.
The topology design process flow diagram of every grade of amplifier as shown in Figure 3.At first in optional electronic circuit scope, suitably select the plurality of sub circuit, and be that amplifier topology at the corresponding levels connects current source/current sink electronic circuit.The input/output end port that connects this grade amplifier then, wherein input port is the output port (the perhaps input port of whole discharge circuit) of upper level amplifier, and output port will be as the input port (the perhaps output port of whole discharge circuit) of next stage amplifier.Connection processing electronic circuit that amplifier comprises at the corresponding levels whole " directly handling " and partly " subsequent treatment " type port afterwards, and will remain " subsequent treatment " type port and deposit corresponding pending port data array TXXX wait subsequent treatment in.
3. when design circuit input stage, intergrade, output stage, circuit source/trap, active pull-up each several part circuit, observe and to select the electronic circuit scope.Referring to Fig. 3.
The electronic circuit that the design of circuit input stage can be selected is p channel transistor differential pair and n channel transistor differential pair; The electronic circuit that the design of circuit intergrade can be selected is current source a, current source c, current sink a, current sink c and n channel transistor and p channel transistor; The electronic circuit that the design of circuit output stage can be selected is ga output stage, vf output stage, vf/ga output stage, current source a, current sink a and n channel transistor and p channel transistor; The electronic circuit that the design of circuital current source can be selected is current source a, b and c electronic circuit, and n channel transistor and p channel transistor; The electronic circuit that the design of circuital current trap can be selected is current sink a, b and c electronic circuit, and n channel transistor and p channel transistor; The electronic circuit that the design of circuit active pull-up can be selected is p channel transistor active pull-up and n channel transistor active pull-up.
4. the selective rule of electronic circuit is when observing electronic circuit range of choice regulation, if in the time of can selecting n/p channel transistor electronic circuit or 1～13 electronic circuit, with one in big probability selection 1～13 electronic circuit, so that better utilization success circuit design experience realizes circuit design fast and accurately.
5. the connection type of electronic circuit port is divided into two kinds of direct processing and subsequent treatment.
The port data array of electronic circuit is described the character of this each port of electronic circuit, according to described character, directly the antithetical phrase circuit port carries out the connection processing between the port, also the node number of port can be deposited in the pending port data array of corresponding TXXX, waits for subsequent treatment.P channel transistor differential pair electronic circuit among the subordinate list a for example, the character of port 4 is acsi, it can be deposited among the corresponding pending port data array Tacsi and wait for subsequent treatment.In electronic circuit port type table 2, the electronic circuit port with port character 1～10 can directly be handled, and also can deposit in respectively among the corresponding pending port data array TXXX, waits for subsequent treatment; And the electronic circuit port with port character 11～16 can only directly be handled.
6. during the connexon circuit port,, connect according to following rule according to the character of port shown in the table 2:
{acso←→dcso；acsi←→dcsi；anvb←→dnvb；apvb←→dpvb；ang←→dng；apg←→dpg；avdd←→vdd；avss←→vss}
Promptly connect having port character acso and have between the port of port character dcso, all the other connect, and the rest may be inferred.
7. under the situation that satisfies rule 6, also to consider following three kinds of situations that can not connect during the connexon circuit port.
First kind of situation is under the situation that satisfies rule 6, avoids connecting between the port of same electronic circuit.Current source a electronic circuit among the subordinate list a for example, port one has port character acso, and port 3 has port character dcso, and two-port character satisfies the condition of contact of rule 6, but for avoiding producing the idle circuit topological structure, can not connect between these two ports.
Second kind of situation is can not carry out port between the electronic circuit that comprises in the same electronic circuit string to connect.In current source/current sink design process, successively with the current source/current sink electronic circuit that designs, and other electronic circuit of port connection is with it formed electronic circuit string.In the electronic circuit string synoptic diagram for example shown in Figure 5, the grid of pmos electronic circuit (node 7) is connected with the grid (node 3) of current source a electronic circuit, produces the current source circuit of cascade, and pmos electronic circuit and current source a electronic circuit form the electronic circuit string simultaneously.The port one of cascade current source circuit has port character acso, port 6 has port character dcso, two-port character satisfies the condition of contact of rule 6, but because these two ports are in same electronic circuit string, for avoiding producing the idle circuit structure, can not carry out port between these two ports and connect.
The third situation is that the port with two seed circuit port character can not carry out twice connection.For example the port one of the current source a electronic circuit among the subordinate list a has character acso and avdd, if this end points is connected with power supply vdd, port character acso is just invalid so, and this port is deleted from pending port data array Tacso.
8. handle unsettled port, guarantee circuit design process closure.
According to topology design process flow diagram shown in Figure 2, after input stage, intergrade, output stage topology generate and finish, check whether unsettled port is arranged, by processing, guarantee circuit topology generative process closure, thereby guarantee can not produce invalid design unsettled port.
According to the restriction of circuit design process flow diagram and electronic circuit port concatenate rule, last remaining unsettled port type only may be avdd, avss, acso, acsi, dcso and dcsi.When handling unsettled port, observing under the prerequisite of the 6th, 7 strip circuit port concatenate rules, at first with certain probability handle avdd ← → vdd; Avss ← → vss} between and acso ← → dcso; Acsi ← → connection between the dcsi}; If also have remaining port, can only be acsi (perhaps dcsi), acso (perhaps dcso) port is connected remaining port with the nmos/pmos active pull-up, links to each other with power supply vss/vdd again, be 0 up to the remaining port number.
Technical scheme
A kind of data array circuit describing method of mimic channel, application comprises: describe mimic channel with the data array mode; The collaborative circuit create-rule of this circuit describing method can be realized the automatic generation of discharge circuit topological structure, can solve the connectivity problem of multiterminal device easily, and can be under the prerequisite that does not generate idle circuit, guarantee the whole design process closure, finally generate high-quality discharge circuit topological structure, and with the circuit topological structure of net sheet form output design, specific implementation is as follows:
1. the step of describing mimic channel is as follows: referring to Fig. 1, Fig. 2.
1). with reference to 16 electronic circuits, mimic channel is divided into circuit module, each circuit module is identical with certain electronic circuit topological structure;
2). circuit module is applied mechanically the topological property data array and the topology data array of corresponding electronic circuit, generates self topological property data array and topology data array;
2. realize that the automatic step that generates of discharge circuit topological structure is as follows:
1). topology forms controller according to customer requirements, selects the discharge circuit design direction;
2). topology forms controller and utilizes topological formation rule and 16 classons circuit, designs input stage, intergrade and the output stage of discharge circuit successively;
3). the design procedure of every grade of amplifier is at first to select suitable electronic circuit in optional scope, current source/the current sink that connects every grade of circuit again, and handle the input/output end port of every grade of circuit, then according to the port character data array connexon circuit port of electronic circuit, and the port that will not connect is saved in corresponding pending port data matrix T XXX, the wait post-processed;
4). topology forms all unsettled ports in the controller treatment circuit generative process, makes the closing of circuit of generation.
16 electronic circuits of summarizing the experience out, and use the topological property data array, topology data array and topological port data array are described device property, topological connection relation and the electronic circuit port character of each electronic circuit respectively.
This invention adopts the data array mode to describe circuit.
When this invention was used to describe mimic channel, the data array of using was topological property data array and topology data array.
When this invention was applied to discharge circuit and generates automatically, applied topology character data array, topology data array and topological port data array were finished the discharge circuit design jointly.
The present invention can describe most mimic channels, and the scope of application is extensive.When this describing method is applied to the discharge circuit automatic Synthesis, can solve the connectivity problem of multiterminal device easily, and can work in coordination with the circuit design rule that proposes, under the prerequisite that does not generate the idle circuit structure, guarantee circuit topology generative process closure, finally generate high-quality discharge circuit topology, and the circuit topology of design can be converted into efficiently the output of net sheet form.
That mentions in the above-mentioned introduction is listed as follows:
Table 1 data array description grammer.
The topological port type of table 2.
Table 3 circuit topology design direction.
The data array circuit of table 4 discharge circuit shown in Figure 6 is described.
The circuit parameter configuration of table 5 amplifier a and amplifier b and performance are relatively.
Description of drawings
For further specifying technology contents of the present invention, below in conjunction with embodiment and accompanying drawing, tabulation, describe in detail as after, wherein:
Fig. 1 topology generates block diagram.
Fig. 2 topology design process flow diagram.
Every grade of topology design process flow diagram of Fig. 3.
Fig. 4 circuit topology mode chart.
Fig. 5 electronic circuit string synoptic diagram.
Fig. 6 discharge circuit synoptic diagram.
Fig. 7 ga-cf-ga discharge circuit synoptic diagram.
Fig. 8 ga-ga-ga discharge circuit synoptic diagram.
Fig. 9 data array description method is described the step of circuit.
Embodiment
1). circuit is described embodiment.
With discharge circuit shown in Figure 6 is that example illustrates the process of describing circuit with data array circuit describing method, and performing step as shown in Figure 9.Fig. 6 circuit comprises 9 mos devices, the circuit structure that draws the circuit module 1 that M1 and M2 form among Fig. 6 by analysis is identical with the p channel transistor differential pair structure among the subordinate list a, current source a structure is coincide among the circuit structure of the circuit module 2 that M3 and M4 form and the subordinate list a, current sink a structure is coincide among the circuit structure of the circuit module 3 that M5 and M6 form and the subordinate list a, the ga output stage structure coincide among the circuit structure of the circuit module 4 that M7 and M8 form and the subordinate list a, remaining device M9 is as circuit module 5, and n channel transistor active pull-up electronic circuit structure is coincide among its circuit structure and the subordinate list a.The topological property data array and the topology data array of electronic circuit among the corresponding subordinate list a of five modules in the circuit are carried out the circuit description, and the data array circuit that obtains circuit shown in Figure 6 is described as shown in table 4.
2). data array circuit describing method is applied to the embodiment of discharge circuit topology automatic Synthesis.
The step of utilizing data array circuit describing method generative circuit topological structure as shown in Figure 1.Controller generates the topological structure of whole discharge circuit according to the circuit topology create-rule by the editor to electronic circuit shown in the subordinate list a.Because each electronic circuit is described by topological property data array, topology data array and topological port data array, so controller is on the basis of analyzing electronic circuit port data array to the editor of electronic circuit, character in conjunction with each device of describing in the character data array, by modification to the structured data array, the realization entire circuit connects, at last the circuit that designs with the output of net sheet form.
According to the circuit create-rule of above introduction, two different discharge circuits of performance characteristics of target design, the characteristics of discharge circuit a are that gain requires height, the characteristics of discharge circuit b are bandwidth requirement height.The performance requirement that the user proposes is as shown in table 5.
With performance requirement substitution topology grade of fit computing formula (1) computing that the user proposes, obtain in the table 3 each topology design pointing needle to the grade of fit Fa={0 of discharge circuit a performance requirement; O; 0.8; 0.9; 0; 0; 1.9; 1; 1} is at the grade of fit Fb={1 of discharge circuit b performance requirement; 0; 0.9; 0.8; 1; 1; 1; 1.9; 1}.The table of comparisons 3, topological structure visible and that discharge circuit a grade of fit is the highest is encoded to 7 (ga-cf-ga types), and the topological structure the highest with discharge circuit b grade of fit is encoded to 8 (ga-ga-ga types).
The topology formation controller uses topological create-rule to generate discharge circuit, as shown in Figure 7 and Figure 8.In the table 5 Fig. 7 and discharge circuit shown in Figure 8 are carried out parameter configuration, and carry out performance simulation, adopt 0.35u technology, operating voltage 5v with spice.
Table 1 data array description grammer
| Type | | Type | Explanation | |||
| 1 | avdd | Need |
2 | avss | Need |
|
| 3 | in | |
4 | out | |
|
| 5 | acso | Need |
6 | dcso | Current source cso is provided | |
| 7 | acsi | Need |
8 | dcsi | Current sink csi is provided | |
| 9 | ang | The grid level that needs nmos | 10 | apg | The grid level that needs |
|
| 11 | anvb | Need nmos type power supply | 12 | dnvb | Nmos type power supply is provided | |
| 13 | apvb | Need pmos type power supply | 14 | dpvb | Pmos type power supply is provided | |
| 15 | dng | The grid level of nmos is provided | 16 | dpg | The grid level of pmos is provided |
Table 2 data array port type
| Numbering | Input stage | | Output stage | |
| 1 2 3 4 5 6 7 8 9 | GA GA GA GA GA GA GA GA GA | CF GA CF GA CF GA CF GA GA+GA | - - VF VF VF\GA VF\GA GA GA GA |
Table 3 amplifier topology design direction
The data array circuit of table 4 discharge circuit shown in Figure 6 is described
The parameter configuration of table 5 amplifier a and amplifier b and performance are relatively
Subordinate list a electronic circuit and data array topology thereof are described
Claims (1)
1. the data array circuit describing method of a mimic channel comprises: with the step of data array description mimic channel; This circuit is described the automatic generation step that the collaborative circuit create-rule of step can be realized the discharge circuit topological structure, can solve the connectivity problem of multiterminal device easily, and can be under the prerequisite that does not generate idle circuit, guarantee the whole design process closure, finally generate high-quality discharge circuit topological structure, and the circuit topological structure with net sheet form output design is characterized in that:
(1). the step of describing mimic channel is as follows:
1). with reference to 16 electronic circuits, mimic channel is divided into a plurality of circuit modules, each circuit module is identical with certain electronic circuit topological structure; Wherein each electronic circuit is described with topological property data array, topology data array and topological port data array respectively; The topological property data array is with the numbering of matrix form descriptor device that circuit comprises, type, its data array description grammer are that device number is the positive integer of inequality, type of device sign indicating number value is 0,1,2,3,4,5,6, respectively corresponding 0 → n channel transistor device, 1 → p channel transistor device, 2 → electric capacity, 3 → resistance, 4 → diode, 5 → independent voltage source, 6 → independent current; Topology data array descriptor circuit topology connects situation, the data array description grammer is that 1～15 electronic circuit all comprises transistor device, when describing circuit, transistor device can be handled as four-terminal device or three terminal device, be used 4 * 1 matrixes or 3 * 1 matrix representations respectively; In the design of discharge circuit automatic Synthesis, transistor device is handled as three terminal device, with 3 * 1 matrix representations; The 16th electronic circuit is the two terminal device electronic circuit, and the topology data array is with 2 * 1 matrix representations; When describing electric capacity or resistance, the every row element of matrix is represented a port of this device; When describing diode or independent current source, on behalf of forward voltage end or electric current, first row element of matrix flow into end, and second row element is represented negative voltage end or electric current outflow end; The port character of topology port data array descriptor circuit, 1～15 electronic circuit topology port character is to be described by 16 kinds of port types that provide, wherein in 16 kinds of port types: 1 be avdd, 2 for avss, 3 in, 4 for out, 5 for acso, 6 for dcso, 7 for acsi, 8 for dcsi, 9 for ang, 10 for apg, 11 for anvb, 12 for dnvb, 13 for apvb, 14 for dpvb, 15 for dng, 16 be dpg; The form of 1～15 electronic circuit topology port data array is according to from top to bottom, and order from left to right is each transistor device in the descriptor circuit successively, and the character of a port of every line description electronic circuit of topological port data array; Wherein p/n channel transistor active pull-up electronic circuit comprises two topological port data arrays respectively, port character when first topological port data array is described this electronic circuit as active pull-up, the port character when second topological port data array described this electronic circuit and other electronic circuit composition biasing circuit; The 16th electronic circuit is the two terminal device electronic circuit, does not have the port property description, and the topological port data array of port character is 0;
2). each circuit module is applied mechanically the topological property data array and the topology data array of corresponding electronic circuit, generates self topological property data array and topology data array;
(2). realize that the automatic step that generates of discharge circuit topological structure is as follows:
1). topology forms controller according to customer requirements, selects the discharge circuit design direction;
2). topology forms controller and utilizes topological formation rule and 16 electronic circuits, designs input stage, intergrade and the output stage of discharge circuit successively;
3). the design procedure of every grade of amplifier is at first to select suitable electronic circuit in optional scope, current source/the current sink that connects every grade of circuit again, and handle the input/output end port of every grade of circuit, then according to the topological port data array connexon circuit port of electronic circuit, and the port that will not connect is saved in corresponding pending port data matrix T XXX, the wait post-processed;
4). topology forms all unsettled ports in the controller treatment circuit generative process, makes the closing of circuit of generation.
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| CN102024066B (en) * | 2009-09-09 | 2013-02-06 | 中国科学院微电子研究所 | Automatic generation method of analog circuit schematic through analog circuit netlist |
| CN113552466B (en) * | 2021-06-11 | 2022-04-19 | 西安电子科技大学 | Collaborative circuit generation method based on user hardware resource distribution |
| CN113673195B (en) * | 2021-10-25 | 2022-02-22 | 南京集成电路设计服务产业创新中心有限公司 | Circuit gate size optimization method based on network topology sequence |
| CN114004048A (en) * | 2021-10-27 | 2022-02-01 | 中国南方电网有限责任公司超高压输电公司检修试验中心 | Converter transformer on-load tap-changer switching topological structure design method |
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| US6381563B1 (en) * | 1999-01-22 | 2002-04-30 | Cadence Design Systems, Inc. | System and method for simulating circuits using inline subcircuits |
| CN1272735C (en) * | 2001-06-15 | 2006-08-30 | 西诺谱西斯公司 | Method and system for design selection by interactive visualization |
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|---|---|---|---|---|
| US6381563B1 (en) * | 1999-01-22 | 2002-04-30 | Cadence Design Systems, Inc. | System and method for simulating circuits using inline subcircuits |
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