CN113552466B - Collaborative circuit generation method based on user hardware resource distribution - Google Patents

Collaborative circuit generation method based on user hardware resource distribution Download PDF

Info

Publication number
CN113552466B
CN113552466B CN202110650368.2A CN202110650368A CN113552466B CN 113552466 B CN113552466 B CN 113552466B CN 202110650368 A CN202110650368 A CN 202110650368A CN 113552466 B CN113552466 B CN 113552466B
Authority
CN
China
Prior art keywords
code
module
beta
radiation
user
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110650368.2A
Other languages
Chinese (zh)
Other versions
CN113552466A (en
Inventor
宫江雷
闫允一
郭宝龙
成永盛
程首豪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xidian University
Original Assignee
Xidian University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xidian University filed Critical Xidian University
Priority to CN202110650368.2A priority Critical patent/CN113552466B/en
Publication of CN113552466A publication Critical patent/CN113552466A/en
Application granted granted Critical
Publication of CN113552466B publication Critical patent/CN113552466B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2868—Complete testing stations; systems; procedures; software aspects
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2868—Complete testing stations; systems; procedures; software aspects
    • G01R31/287—Procedures; Software aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • Environmental & Geological Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The invention belongs to the technical field of FPGA (field programmable gate array) reliability, and particularly relates to a cooperative circuit generation method based on user hardware resource distribution. Comprises the following steps: the user code resource distribution is named, the user code is named as alpha, and the sub-module code of the user code is named as alphai(ii) a The number of each submodule FF is F alphai(ii) a The number of LUTs per submodule is L alphai(ii) a Step two: reducing the user code resource distribution in the step one according to a scale factor to obtain radiation sensitive code resource distribution; step three: generating a radiation code submodule beta according to the radiation code resource distribution obtained in the step twoi(ii) a Step four: all the sub-module codes beta generated in the third stepiFusing to form a radiation sensing code beta; step five: and fusing the user code alpha and the radiation sensing code beta generated in the step four into a code delta, and naming the code delta as a cooperative code. The method can estimate the error rate and the error position of the user circuit, and can greatly improve the detection efficiency.

Description

Collaborative circuit generation method based on user hardware resource distribution
Technical Field
The invention belongs to the technical field of FPGA (field programmable gate array) reliability, and particularly relates to a cooperative circuit generation method based on user hardware resource distribution.
Background
In the field of aerospace, an FPGA is widely used as a chip with flexible design, low power consumption and high performance in space equipment such as deep space exploration and scientific satellites. The FPGA is of an SRAM type at present, single event upset is easy to occur, and the FPGA develops towards the direction of low voltage and high integration level at present, so that the single event upset is easier to occur. When the FPGA is radiated by space, the equipment works abnormally if the FPGA is lightened, and the equipment is permanently disabled if the FPGA is seriously damaged. Therefore, the influence of space radiation can be prevented to the maximum extent only by better evaluating the single event upset condition.
The existing method for evaluating the reliability of the FPGA is error detection, and the error rate and the error position of the FPGA are obtained through the error detection of an FPGA circuit. And the FPGA circuit has large scale, long error detection time and very low reliability evaluation efficiency.
Disclosure of Invention
The invention aims to provide a method for generating a collaborative circuit based on user hardware resource distribution aiming at the defects of the prior art. By carrying out error detection on the generated cooperative circuit, the error rate and the error position of the user circuit are estimated, and the detection efficiency can be greatly improved.
The method comprises the following steps:
step 1: and distributing and naming the user code resources. The user code is named as alpha, and the sub-module code of the user code is named as alphai(ii) a The number of each submodule FF is F alphai(ii) a The number of LUTs per submodule is L alphai。
αiWhere N is the number of modules of the user code, i is 1,2,3 … N.
FαiI in (1), 2,3 … N, where N is the number of user code modules; f refers to the resource type FF in the user code.
LαiI in (1), 2,3 … N, where N is the number of user code modules; l refers to the resource type LUT in the user code.
Step 2: the user code resource distribution in the step 1 is distributed according to a scale factor lambda (lambda)<1) And after the reduction, obtaining the radiation sensitive code resource distribution. Where resource distribution refers to the number of LUTs and FFs occupied by each sub-module in the code. Number F beta of each submodule FF of the radiation sensitive codeiAnd the LUT number L betaiAnd λ satisfies the formula (0.1).
Figure BDA0003111396630000021
Where λ is 0.1. Naming the distribution of the radiation sensitive code resources, and connecting the spokesThe sensory code is named beta; naming the sub-module code of the radiation sensitive code as betai(ii) a The number of FF of each submodule is F betai(ii) a The number of LUTs per submodule is L betai。
βiWhere N is the number of modules of the radiation code, i is 1,2,3 … N.
FβiI in (1), 2,3 … N, where N is the number of spoke code modules; f refers to the resource type FF in the spoke code.
LβiI in (1), 2,3 … N, where N is the number of spoke code modules; l refers to the resource type LUT in the radiation sensitive code.
And step 3: generating a radiation code submodule beta according to the radiation code resource distribution obtained in the step 2i. Wherein beta isiI is 1,2,3 … N, N is the number of radiation sensing code sub-modules.
Step 3 a: and generating a radiation sensitive code submodule framework. The framework is a fixed modular structure in VHDL syntax. And requires defining an ENTITY name and an archtecture name. The name needs to satisfy the VHDL syntax rules.
And step 3 b: according to F beta calculated in the step 2iThe quantities generate a code that defines the signal. The code complies with the requirements defined in the VHDL syntax for a signal whose bit width is FbetaiThe value of (c). The signal name may satisfy the VHDL syntax rule.
And step 3 c: generating a PROCESS structure code according to the quantity obtained by calculation in the step 2, wherein the code realizes the function of adding two signals; and assigns the result of the addition to the signal generated in step 3 b.
And step 3 d: according to F beta calculated in the step 2iAnd L betaiAnd generating an input/output interface code. The code includes a clock signal, two input signals and an output signal. Wherein one input signal has a bit width of F betaiThe bit width of the other input signal and the output signal is L betai。
Step 3 e: combining the codes generated in steps 3a, 3b, 3c, 3d together to form a new sub-module code. Repeating steps 3a, 3b, 3c, 3d until all sub-module codes are generated.
And 4, step 4: all sub-module codes beta generated in the step 3iAnd fusing to form the radiation sensing code beta.
Step 4 a: and generating a radiation sensitive code top module framework. The framework follows VHDL language syntax provisions. An ENTITY name and an archtecture name need to be defined. The name needs to satisfy the VHDL syntax rules.
And 4 b: and generating an input/output interface of the radiation sensitive code top-layer module. The input and output interface comprises the input and output interface of each submodule. And combining the input and output interfaces of each submodule together, and removing redundant clock signals to only leave one clock signal. The input and output interface of the radiation sensing code top module is obtained.
And 4 c: a COMPONENT block is generated. The syntax structure of the COMPONENT block is:
COMPONENT submodule name N
PORT (input output interface of sub-module N);
END COMPONENT；
each submodule generates a corresponding COMPONENT block, and the code is placed in a top-level module of the radiation sensitive code;
and 4 d: and combining the module framework generated in the step 4a, the input and output interface generated in the step 4b and the COMPONENT block generated in the step 4c into a module code. The way of merging follows the VHDL syntax specification.
And 5: and fusing the user code alpha and the radiation sensing code beta generated in the step 4 into a code delta, and naming the code delta as a cooperative code. The code constitutes a new FPGA engineering. The collaborative code resource distribution is named. Naming the collaboration code as δ; naming each sub-module code of the collaboration code as δi(ii) a The number of FF of each submodule of the cooperative code is F deltai(ii) a The number of LUTs of each submodule of the cooperative code is L deltai。
Wherein deltaiWhere N is the number of modules of the cooperative code, i is 1,2,3 … N.
FδiI in (1), 2,3 … N, where N is the number of cooperating circuit modules; in F-finger cooperative circuitsThe resource type FF.
LδiI in (1), 2,3 … N, where N is the number of cooperating circuit modules; l refers to the resource type LUT in the cooperative circuit.
Step 5 a: and generating a collaborative code top module framework. The framework follows VHDL language syntax provisions. An ENTITY name and an archtecture name need to be defined. The name needs to satisfy the VHDL syntax rules.
And step 5 b: and the input and output interface generates the cooperative code. The interface combines the user code input and output interface and the radiation sensing code input and output interface and eliminates the repeated clock signals. This is the input/output interface of the cooperative code.
And step 5 c: a COMPONENT block is generated. The format of the block is the same as that of step 4 c.
And step 5 d: and combining the module framework generated in the step 5a, the input and output interface generated in the step 5b and the COMPONENT block generated in the step 5c into a code project.
Step 6: and adding constraint statements in the constraint file of the new project generated in the step 5. Where a constraint statement is a formulation of a place and route rule. Each sub-module alpha of the user code is encoded by adding a constraint statementi' and each submodule beta of the radiation sense codei' are interleaved together.
Wherein interleaving refers to the fact that each submodule of two codes fits into each other.
The interleaving statements are respectively a create _ pblock statement and a reset _ pblock statement. The two interleaved statements form a group of interleaved statements; the role of create pblock is to create an interleaving region. The resize _ pblock statement is to set the region scope. Each pair of sub-module interweaves and corresponds to a group of interweaving statements, pblock names of different groups of interweaving statements need to be different, and coordinates need to be different;
and 7: and the cooperative code is comprehensively realized to generate a cooperative circuit. After the cooperative code engineering is comprehensively realized on a vivado tool, codes are mapped onto an FPGA circuit, and the process is a general process in FPGA development.
Compared with the prior art, the invention has the beneficial effects that:
firstly, generating a circuit which is proportionally reduced with the resource distribution of a user circuit, namely a radiation circuit, and then interweaving the user circuit and the radiation circuit together, so that the error rate of the radiation circuit is equal to the error rate of the user circuit; the radiating circuit error location is equal to the subscriber circuit error location; the method for realizing the purpose is to generate the radiation sensing codes according to the resource distribution of the user codes, further fuse the user codes and the radiation sensing codes into the cooperative codes, and estimate the error rate and the error position of the user circuit by carrying out error detection on the generated cooperative circuit, thereby greatly improving the detection efficiency.
Drawings
Fig. 1 is a flow chart of a cooperative circuit generation method of the present invention.
FIG. 2 is a resource distribution diagram after the synthesis of the radiation sensing circuit in the present invention;
wherein, diagram (a) is the resource distribution of sub-module 1; fig. (b) is the resource distribution of sub-module 2; the diagram (c) shows the resource distribution of the submodule 3.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
As can be seen from fig. 1, the operation process of the method is to generate the spoke codes according to the resource overhead, and then fuse the user codes and the spoke codes to finally generate the cooperative codes. The code fusion is converted into circuit interleaving by adding constraint statements. Eventually generating a cooperative circuit that can be used for error detection. The concept of the present method is explained in detail below.
User code: user code refers to functional code running on an FPGA device of a spacecraft. And is also the code to be guarded by the method. Typically the user code is in VHDL language.
Resource amount: there are many different kinds of logic elements in an FPGA, such as LUTs, FFs, BRAMs, DSPs, etc. Different logic cells have different roles. These logic cells are all referred to as resources of the FPGA. The amount of resources is the number of these logical units. The resource amount of the method is particularly the number of LUTs and FFs.
Resource distribution: the same type of logic resources in the FPGA may be distributed to different regions, and resource distribution refers to the distribution of these resources in the FPGA circuitry.
Resource overhead: the resource overhead refers to the amount of resources occupied by a circuit and the distribution of the resources. It is a general term for resource amount and resource distribution.
The radiation sensitive code is as follows: radiation sensing is short for radiation sensing. Irradiation means that the FPGA is irradiated by various cosmic rays in space. The code plays a role in sensing the influence condition of radiation on the FPGA. This code is also constructed in VHDL language.
Fusing: fusion refers to combining two codes into one code. The fusion in the method is mainly used for generating the radiation-sensitive codes and the cooperative codes.
Interweaving: interleaving is the closeness of the place and route of two circuits. The interleaving in the method is the bonding of the layout and the wiring of the user circuit and the radiation sensing circuit.
The cooperation code is as follows: the cooperative code is a code obtained by fusing a user code and a radiation sensitive code into one piece.
A cooperative circuit: the cooperative circuit is a circuit which is comprehensively mapped on the FPGA by cooperative codes and is a circuit formed by interweaving a user circuit and a radiation circuit. And is the circuit that the method ultimately will produce.
The innovation point of the method is to generate a circuit capable of improving error detection efficiency, namely a cooperative circuit. The circuit is a circuit in which the spoke circuit and the subscriber circuit are interleaved. Because the radiation circuit and the user circuit are distributed in the same resource, the error detection results of the radiation circuit and the user circuit are the same, and the resource amount of the radiation circuit is far less than that of the user circuit, so that the error detection efficiency is greatly improved.
The implementation steps of the method are described in detail below with reference to examples, which were tested under the vivado2018.2 tool; the FPGA model is XC7A100T-2FGG 484L; the programming language is VHDL language.
Step 1: the user circuit resource distribution is named. Naming the user code as alpha; coding a userIs named as alphai(ii) a The number of each submodule FF is F alphai(ii) a The number of LUTs per submodule is L alphaiThese data are known conditions;
αiwhere N is the number of modules of the user code, i is 1,2,3 … N. N is 3.
FαiWherein i is 1,2,3 … N, where N is the number of subscriber circuit modules; f refers to the resource type FF in the user circuit. N is 3; resource distribution of F alpha1＝70；Fα2＝80；Fα3＝90。
LαiWherein i is 1,2,3 … N, where N is the number of subscriber circuit modules; l refers to the resource type LUT in the user circuit. N is 3; resource distribution of L alpha1＝60；Lα2＝80；Lα3＝50。
The user code has three sub-modules. The input and output of each submodule is a signal, and the bit width is 10. The resource distribution of the user code is as shown in table 1.
Table 1 subscriber circuit resource distribution
Module numbering Submodule 1(U1) Submodule 2(U2) Submodule 3(U3)
Number of FF 70 80 90
Number of LUTs 60 80 50
Step 2: the user circuit resource distribution is proportioned by a scale factor lambda (lambda)<1) After the reduction, the radiation sensing circuit resource distribution is obtained. Wherein the resource distribution refers to the number of LUTs and FFs occupied by each sub-module in the circuit; number F beta of each submodule FF of a radiation-sensitive circuitiAnd the LUT number L betaiAnd lambda satisfies the formula (0.1)
Figure BDA0003111396630000081
Wherein lambda is 0.1; naming the distribution of the radiation circuit resources, and naming the radiation codes as beta; naming the spoke circuit as beta'; naming the sub-module code of the radiation sensitive code as betai(ii) a The submodule circuit of the radiation sensitive circuit is named as betai'; the number of FF of each submodule is F betai(ii) a The number of LUTs per submodule is L betai。
βiWherein, i is 1,2,3 … N, where N is the number of modules of the spoke code, and N is 3; beta is aiIn' i is 1,2,3 … N, where N is the number of modules in the spoke circuit and N is 3.
FβiWherein i is 1,2,3 … N, where N is the number of the spoke circuit modules; f refers to resource type FF in the spoke circuit. N is 3; f beta is calculated according to the formula (0.1)1＝7；Fβ2＝8；Fβ3＝9；LβiWherein i is 1,2,3 … N, where N is the number of the spoke circuit modules; l refers to a resource type LUT in the radiation circuit, and N is 3; l beta is calculated according to the formula (0.1)1＝6；Lβ2＝8；Lβ3(ii) 5; the calculated radiation sensing circuit resource distribution at this time is shown in table 2:
TABLE 2
Module numbering Module 1 Module 2 Module 3
FF 7 8 9
LUT 6 8 5
And step 3: generating a radiation code submodule beta according to the radiation circuit resource distribution obtained in the step 2i(ii) a Wherein beta isiI is 1,2,3 … N, N is the number of radiation sensing code sub-modules, N is 3;
according to Fbeta1And L beta1The generated code of sub-module 1, the input/output interface of which is formed by a clock signal, 1 input signal of 6 bits wide and 1 input signal of 7 bits wide and 1 output signal of 7 bits wide. The signal definition of this block is a 7-bit wide signal. The PROCESS statement of the module is added by a 6-bit wide input signal and a 7-bit wide input signal, and then assigned to a 7-bit wide output signal.
According to Fbeta2And L beta2The generated code of submodule 2. The input/output interface of the module is composed of a clock signal, 1 input signal with 8 bit width and 1 output signal with 8 bit width. The signal definition of the module is an 8-bit wide signal. Is 8 bits wide in the PROCESS statement of the moduleThe input signal and the 8-bit wide input signal are summed and then assigned to the 8-bit wide output signal.
According to Fbeta3And L beta3The value of (c), the code of the generated submodule 3. The input/output interface of the module is composed of a clock signal, 1 input signal with 5 bit width, 1 input signal with 9 bit width and 1 output signal with 9 bit width. The signal definition of this block is 9 bits wide. The processing statement of the module is added by a 5-bit wide input signal and a 9-bit wide input signal, and then is assigned to a 9-bit wide output signal.
And 5: fusing the user code alpha in the step 1 and the radiation sensing code beta generated in the step 4 into a code delta, and naming the code delta as a cooperative code, wherein the code forms a new FPGA project and names the resource distribution of the cooperative code; naming the collaboration code as δ; naming the cooperative circuit as δ'; naming each sub-module code of the collaboration code as δi(ii) a The number of FF of each submodule of the cooperative code is F deltai(ii) a The number of LUTs of each submodule of the cooperative code is L deltai；
Wherein deltaiWherein, i is 1,2,3 … N, where N is the number of modules of the cooperative code, and N is 6;
Fδii in (1), 2,3 … N, where N is the number of cooperative code modules; f refers to resource type FF in cooperative circuit, N is 6;
Lδii in (1), 2,3 … N, where N is the number of cooperative code modules; l refers to the resource type LUT in the cooperative circuit, N is 6;
the input and output interface of the generated new code is formed by a user code and a radiation code, the cooperative code is formed by adding three sub-modules of the radiation code under the original three sub-modules of the user code, the code is expressed by component blocks, and the three component blocks of the radiation code are added on the basis of the user code;
step 6: adding a constraint statement in the constraint file of the new project generated in the step 5, and aiming at interweaving the user circuit alpha ' and the radiation circuit beta ' together to obtain delta '; wherein the constraint statement is a formulation of a place and route rule; each sub-circuit of the user circuit is divided by adding constraint statementsModule alphai' and each submodule beta of the radiation sensitive circuiti' are interleaved together.
Generating three interleaving areas by a create _ pblock statement, and respectively placing a sub-module 1 of a user code and a sub-module 1 of a radiation sensing code into a first interleaving area; respectively placing the sub-module 2 of the user code and the sub-module 2 of the radiation sensing code into a second interleaving area; and respectively placing the sub-module 3 of the user code and the sub-module 3 of the radiation sensitive code into a third interleaving area.
The inside of the three pblocks is a circuit formed by interweaving the user circuit sub-module and the radiation circuit sub-module, and the radiation circuit and the user circuit are crossed together by means of interweaving; estimating an error rate and an error position of a user circuit by performing error detection on a small-scale radiation circuit; the efficiency of error detection is greatly improved.
In the method, user circuit resource distribution is the result of user circuit after synthesis by a synthesis tool, so the method needs to verify that the aforementioned example codes are synthesized on the synthesis tool vivado2018.2 according to whether the result after synthesis of the radiation code generated by radiation circuit resource distribution is consistent before synthesis, and the synthesis result is shown in fig. 2, wherein, the diagram (a) is the resource distribution of the sub-module 1; fig. (b) is the resource distribution of sub-module 2; the diagram (c) shows the resource distribution of the submodule 3. Description of the drawings: LUT2 is shown as a LUT; FDRE is FF.
Comparing fig. 2 with table 2, it can be seen that the results are completely consistent, which indicates that the resource distribution of the generated spoke circuit is in accordance with our expectation.
Firstly, generating a circuit which is proportionally reduced with the resource distribution of a user circuit, namely a radiation circuit, and then interweaving the user circuit and the radiation circuit together, so that the error rate of the radiation circuit is equal to the error rate of the user circuit; the radiating circuit error location is equal to the subscriber circuit error location; the method for realizing the purpose is to generate the radiation sensing codes according to the resource distribution of the user codes, further fuse the user codes and the radiation sensing codes into the cooperative codes, finally add the constraint sentences, and generate the cooperative circuit after comprehensive realization.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (3)

1. The method for generating the collaborative circuit based on the user hardware resource distribution is characterized by comprising the following steps:
step 1: and (3) naming the user code resource distribution: the user code is named as alpha, and the sub-module code of the user code is named as alphai(ii) a The number of each submodule FF is F alphai(ii) a The number of LUTs per submodule is L alphai；
αiWherein, i is 1,2,3 … N, where N is the number of modules of the user code;
Fαii in (1), 2,3 … N, where N is the number of user code modules; f refers to a resource type FF in the user code;
Lαii in (1), 2,3 … N, where N is the number of user code modules; l refers to a resource type LUT in the user code;
step 2: reducing the user code resource distribution in the step 1 by a scale factor lambda (lambda <1) to obtain radiation sensing code resource distribution;
the radiation perception is short for radiation perception, the radiation means that the FPGA is radiated by various cosmic rays in the space, the code plays a role in perceiving the influence condition of the radiation on the FPGA, and the code is also formed by VHDL language;
wherein, the resource distribution refers to the number of LUTs and FFs occupied by each sub-module in the code; number F beta of each submodule FF of the radiation sensitive codeiAnd the LUT number L betaiAnd λ satisfies the formula (0.1);
Figure FDA0003508660020000011
wherein, lambda is 0.1;
naming the distribution of the radiation sensitive code resources: naming the spoke code as beta; naming the sub-module code of the radiation sensitive code as betai(ii) a The number of FF of each submodule is F betai(ii) a The number of LUTs per submodule is L betai；
βiI in (1), 2,3 … N, where N is the number of modules of the spoke code;
Fβii in (1), 2,3 … N, where N is the number of spoke code modules; f refers to a resource type FF in the radiation sensitive code;
Lβii in (1), 2,3 … N, where N is the number of spoke code modules; l refers to a resource type LUT in the radiation sensing code;
and step 3: generating a radiation code submodule beta according to the radiation code resource distribution obtained in the step 2i；
Wherein, betaiWherein i is 1,2,3 … N, N is the number of radiation sensing code sub-modules;
step 3 a: generating a radiation code submodule framework, and defining an ENTITY name and an ARCHITECTURE name;
and step 3 b: according to F beta calculated in the step 2iThe number generates a code defining the signal, which follows the requirements defined for the signal in the VHDL syntax, the bit width of the signal being F βiA signal name satisfies a VHDL syntax rule;
and step 3 c: according to the calculated L beta in the step 2iGenerating a PROCESS structure code in quantity, wherein the code realizes the function of adding two signals; and assigning the result of the addition to the signal generated in step 3 b;
and step 3 d: according to F beta calculated in the step 2iAnd L betaiGenerating an input/output interface code; the code includes a clock signal, two input signals and an output signal; wherein one input signal has a bit width of F betaiThe bit width of the other input signal and the output signal is L betai；
Step 3 e: combining the codes generated in the steps 3a, 3b, 3c and 3d together to form a new sub-module code;
repeating the steps 3a, 3b, 3c and 3d until all the sub-module codes are generated;
and 4, step 4: all sub-module codes beta generated in the step 3iFusing to form a radiation sensing code beta;
and 5: fusing the user code alpha and the radiation sensing code beta generated in the step 4 into a code delta, and naming the code delta as a cooperative code, wherein the code forms a new FPGA project, names the cooperative code resource distribution, and names the cooperative code delta; naming each sub-module code of the collaboration code as δi(ii) a The number of FF of each submodule of the cooperative code is F deltai(ii) a The number of LUTs of each submodule of the cooperative code is L deltai；
Wherein, deltaiI in (1), 2,3 … N, where N is the number of modules of the cooperative code;
Fδii in (1), 2,3 … N, where N is the number of cooperating circuit modules; f refers to a resource type FF in the cooperative circuit;
Lδii in (1), 2,3 … N, where N is the number of cooperating circuit modules; l refers to a resource type LUT in the cooperative circuit;
step 6: adding constraint statements in the constraint file of the new project generated in the step 5, wherein the constraint statements are the preparation of the layout and wiring rules, and each sub-module alpha 'of the user code is added by the constraint statements'iAnd each sub-module beta of the radiation sensitive codei' interweave together;
the interleaving means that each sub-module of the two codes are mutually attached;
wherein, the interleaving statements are respectively create _ pblock statement and resize _ pblock statement; the two interleaved statements form a group of interleaved statements; the function of create _ pblock is to create an interleaving region; resize _ pblock statements are used for setting the region range, each pair of sub-module interweaves and corresponds to one group of interweaving statements, the pblock names of different groups of interweaving statements need to be different, and the coordinates need to be different;
and 7: and comprehensively realizing the cooperative codes to generate a cooperative circuit, and mapping the codes onto the FPGA circuit after comprehensively realizing the cooperative code engineering on the vivado tool.
2. The method for generating cooperative circuits based on user hardware resource distribution according to claim 1, wherein the specific process of step 4 is:
step 4 a: generating a radiation sensitive code top module frame; the framework follows VHDL language syntax provisions; defining an ENTITY name and an ARCHITECTURE name; the name needs to satisfy VHDL syntax rules;
and 4 b: generating an input/output interface of a top module of the radiation sensing code; the input and output interface comprises the input and output interfaces of each submodule; combining the input and output interfaces of each submodule together, removing redundant clock signals and only leaving one clock signal; the input and output interface of the radiation sensing code top module is obtained;
and 4 c: generating a COMPONENT block, wherein the syntactic structure of the COMPONENT block is as follows:
COMPONENT submodule name N
PORT (input output interface of sub-module N);
END COMPONENT；
the COMPONENT blocks are used for representing the sub-modules, the main parameter of each COMPONENT block is the input/output interface of the sub-module, the input/output interface of each COMPONENT block needs to be the same as the input/output interface in the sub-module file, different COMPONENT blocks need different sub-module names, and the generated COMPONENT block codes are placed in a top-layer module of the radiation sensing codes;
and 4 d: and (4) merging the module framework generated in the step (4 a), the input and output interface generated in the step (4 b) and the COMPONENT block generated in the step (4 c) into a module code, wherein the merging mode conforms to the VHDL syntax specification.
3. The method of claim 2, wherein the collaborative circuit generation based on user hardware resource distribution,
the specific process of fusing the user code alpha and the radiation code beta in the step 5 is as follows:
step 5 a: generating a collaborative code top module framework, wherein the framework follows VHDL language syntax rules, and needs to define an ENTITY name and an ARCHITECTURE name, and the names need to meet the VHDL syntax rules;
and step 5 b: generating an input/output interface of the cooperative code, wherein the interface is an input/output interface of the cooperative code, and is formed by combining a user code input/output interface and a radiation sensing code input/output interface and removing a repeated clock signal;
and step 5 c: generating a COMPONENT block, the format of which is the same as that of step 4 c;
and step 5 d: and combining the module framework generated in the step 5a, the input and output interface generated in the step 5b and the COMPONENT block generated in the step 5c into a code project.
CN202110650368.2A 2021-06-11 2021-06-11 Collaborative circuit generation method based on user hardware resource distribution Active CN113552466B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110650368.2A CN113552466B (en) 2021-06-11 2021-06-11 Collaborative circuit generation method based on user hardware resource distribution

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110650368.2A CN113552466B (en) 2021-06-11 2021-06-11 Collaborative circuit generation method based on user hardware resource distribution

Publications (2)

Publication Number Publication Date
CN113552466A CN113552466A (en) 2021-10-26
CN113552466B true CN113552466B (en) 2022-04-19

Family

ID=78130526

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110650368.2A Active CN113552466B (en) 2021-06-11 2021-06-11 Collaborative circuit generation method based on user hardware resource distribution

Country Status (1)

Country Link
CN (1) CN113552466B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1741026A (en) * 2005-09-16 2006-03-01 北京中星微电子有限公司 Method for fast generating logical circuit
CN1845106A (en) * 2005-04-08 2006-10-11 中国科学院半导体研究所 Analog circuit data array description method
US8042093B1 (en) * 2001-11-15 2011-10-18 Cypress Semiconductor Corporation System providing automatic source code generation for personalization and parameterization of user modules
CN103226488A (en) * 2013-05-06 2013-07-31 中国农业银行股份有限公司 Method and device for efficiency control in formalized code generation
CN107895087A (en) * 2017-11-29 2018-04-10 中科亿海微电子科技（苏州）有限公司 The method and system that the emulation of PLD module level automatically generates with code
CN112100949A (en) * 2020-09-15 2020-12-18 北京士昌鼎科技有限公司 Automatic development method and device of integrated circuit chip and electronic equipment

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8042093B1 (en) * 2001-11-15 2011-10-18 Cypress Semiconductor Corporation System providing automatic source code generation for personalization and parameterization of user modules
CN1845106A (en) * 2005-04-08 2006-10-11 中国科学院半导体研究所 Analog circuit data array description method
CN1741026A (en) * 2005-09-16 2006-03-01 北京中星微电子有限公司 Method for fast generating logical circuit
CN103226488A (en) * 2013-05-06 2013-07-31 中国农业银行股份有限公司 Method and device for efficiency control in formalized code generation
CN107895087A (en) * 2017-11-29 2018-04-10 中科亿海微电子科技（苏州）有限公司 The method and system that the emulation of PLD module level automatically generates with code
CN112100949A (en) * 2020-09-15 2020-12-18 北京士昌鼎科技有限公司 Automatic development method and device of integrated circuit chip and electronic equipment

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
A Method to Search Fallible Branch in FPGA Programs;Haixu Li;《2015 International Conference on Intelligent Information Hiding and Multimedia Signal Processing》;20151231;第266-270页 *
卷积神经网络的软硬件协同加速技术;李欣瑶;《航空兵器》;20210530;第99-104页 *
采用软硬件协同设计的 SoftMax 函数的 FPGA 实现;周维康;《信 息 通 信》;20191231;第59-60页 *

Also Published As

Publication number Publication date
CN113552466A (en) 2021-10-26

Similar Documents

Publication Publication Date Title
De et al. RSYN: A system for automated synthesis of reliable multilevel circuits
Osada et al. SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect
US8627245B1 (en) Density balancing in multiple patterning lithography using integrated circuit layout fill
Xu et al. Clustered fault tolerance TSV planning for 3-D integrated circuits
CN109427741B (en) Semiconductor device including PG alignment cells and method of generating layout thereof
CN113552466B (en) Collaborative circuit generation method based on user hardware resource distribution
Evans et al. Riif-reliability information interchange format
Tiktopoulos et al. Validity of the relativistic eikonal approximation
US20060236158A1 (en) Memory element for mitigating soft errors in logic
US20150186199A1 (en) Method of analyzing error rate in system-on-chip
Urbatsch et al. Estimation and Interpretation of keff Confidence Intervals in MCNP
KR20190051673A (en) System and method for consequence analysis and risk assessment of multi-unit nuclear power plant
Neelima et al. Half diagonal matrix codes for reliable embedded memories
CN112597728B (en) Triple modular redundancy method based on molecular-level netlist
Ayache et al. A reliability model for error correcting memory systems
Freitas et al. LPC: An error correction code for mitigating faults in 3D memories
Jung et al. Decoupled planar MOC solution for dynamic group constant generation in direct three-dimensional core calculations
Lo et al. Reliable logic circuits with byte error control codes-a feasibility study
Ravi et al. Fault-diagnosis-based technique for establishing RTL and gate-level correspondences
Kourfali et al. Superimposed in-circuit fault mitigation for dynamically reconfigurable fpgas
CN102163250A (en) Redundant-residue-number-system-based irradiation-resisting reinforcing method and device
Drumm et al. Forward and adjoint methods and applications for deterministic electron-photon transport
Ying et al. Analysis of FPGA Mitigation Improvement to Energetic Protons
Krishna et al. Performance Analysis of Different Reduced Precision Redundancy based Full Adders
Stempkovsky et al. Improving Reliability-driven Resynthesis with Better Initial Structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant