CN100403527C - Micron scale chip size packaging radiation structure - Google Patents
Micron scale chip size packaging radiation structure Download PDFInfo
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- CN100403527C CN100403527C CNB2005100953499A CN200510095349A CN100403527C CN 100403527 C CN100403527 C CN 100403527C CN B2005100953499 A CNB2005100953499 A CN B2005100953499A CN 200510095349 A CN200510095349 A CN 200510095349A CN 100403527 C CN100403527 C CN 100403527C
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- chip
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- micron scale
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
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Abstract
The present invention relates to a micron scale chip size packaging radiation structure which is applied to the technical field of integrated circuit chips, or power discrete device chips, or wafer scale chip size packaging technique. The present invention comprises a chip body (1) and circuit welding pads (2), wherein the circuit welding pads (2) are arranged at the front surface of silicon basis materials of the chip body (1); metallic convex points (3) are implanted at the top surface of the circuit welding pads. The present invention is characterized in that a metallic layer (4) is implanted on the back surface of the silicon basis materials of the chip body (1); metallic lugs (5) are made on the metallic layer (4) which is arranged at the back surface of the silicon basis materials. The present invention has the characteristics that the traditional packaging mode in which base islands are exposed is changed; bare chips directly radiate heat by the chip through a flip chip packaging technology, so the present invention has favorable functions of heat radiation or heat conduction.
Description
Technical field:
The present invention relates to a kind of micron scale chip size packaging radiation structure, is to be applied in integrated circuit (IC) chip or power discrete device chip, or disc grade chip size encapsulation technology field.
Background technology:
In recent years, integrated circuit or discrete device consumer products demand heighten, the also corresponding increase of its kind.The metal wire of disk factory reduces, and the Chip Packaging product moves towards semicon industry development of technology such as miniaturization under the prerequisite of the Performance And Reliability that does not influence product, be the mainstay that satisfies this type of demand.
For many years, the naked brilliant encapsulation of chip is widely used, and this is present profile minimum, does not almost have a kind of packing forms of packing or protective materials.The area of this encapsulation is the same with chip area big.
Before the present invention makes, traditional Chip Packaging, its encapsulated radiating structure is to install metal fin additional at the silicon substrate of chip body or the Ji Dao back side, chip package inside, the heat that chip produced dispels the heat indirectly by exposing Ji Dao.Therefore its heat sinking function or heat conduction function are relatively poor.
Summary of the invention:
The objective of the invention is to overcome above-mentioned deficiency, a kind of micron scale chip size packaging radiation structure with preferable heat sinking function or heat conduction function is provided.
The object of the present invention is achieved like this: a kind of micron scale chip size packaging radiation structure, comprise the chip body, be arranged at the circuit welding pad in chip bulk silicon base material front, plant the metal salient point that places the circuit welding pad end face, it is characterized in that: plant metal level in chip bulk silicon substrate backside; On the silicon substrate metal layer on back, make metal coupling, form heat exchange area, produce heat sinking function with air at chip back.
Micron scale chip size packaging radiation structure of the present invention, described chip bulk silicon substrate backside metal level has single or multiple lift.
Micron scale chip size packaging radiation structure of the present invention, metal coupling has single or multiple lift on the described chip bulk silicon substrate backside metal level.
Characteristics of the present invention are to change the packaged type that tradition exposes Ji Dao, with flip-chip packaged technology, bare chip are directly dispelled the heat chip.Therefore have preferable heat sinking function or heat conduction function.
Description of drawings:
Fig. 1 plants for micron scale chip size packaging radiation structure chip bulk silicon substrate backside of the present invention and puts schematic diagram behind the metal level.
Fig. 1 is back schematic diagram for micron scale chip size packaging radiation structure of the present invention completes.
Embodiment:
Referring to Fig. 1, a kind of micron scale chip size packaging radiation structure of the present invention, mainly by chip body 1, be arranged at the circuit welding pad 2 in chip body 1 silicon substrate front, plant the metal salient point 3 that places the circuit welding pad end face, plant the single or multiple lift metal level 4 that places the chip body 1 silicon substrate back side; The single or multiple lift metal coupling 5 that is made on the silicon substrate metal layer on back 4 is formed.
Described chip bulk silicon substrate backside metal level 4 materials are a kind of among Ti or Cu, Ni, Au, the Tiw or several;
Described circuit welding pad end face metal salient point 3 materials are a kind of among Au or Ag, Cu, Sn, Ni, the Pd or several.
Concrete manufacture method:
In the bare chip packaging technology, on the silicon substrate of the chip body back side, adopt sputter, evaporation or plating or chemical plating process, the single or multiple lift metal is implanted, as Fig. 1; On the silicon substrate metal layer on back, adopt sputter, photoetching, etching, evaporation or plating or chemical plating process again, make the single or multiple lift metal salient point, as Fig. 2.
Claims (5)
1. micron scale chip size packaging radiation structure, comprise chip body (1), be arranged at the circuit welding pad (2) in chip body (1) silicon substrate front, plant the metal salient point (3) that places the circuit welding pad end face, it is characterized in that: plant metal level (4) in chip body (1) the silicon substrate back side; Go up making metal coupling (5) in silicon substrate metal layer on back (4), metal coupling (5) has multilayer on the described chip bulk silicon substrate backside metal level.
2. a kind of micron scale chip size packaging radiation structure according to claim 1 is characterized in that: described chip bulk silicon substrate backside metal level (4) has single or multiple lift.
3. a kind of micron scale chip size packaging radiation structure according to claim 2 is characterized in that: described chip bulk silicon substrate backside metal level (4) material is a kind of among Ti or Cu, Ni, Au, the Tiw or several.
4. a kind of micron scale chip size packaging radiation structure according to claim 1 is characterized in that: metal coupling (5) material is a kind of among Cu or Sn, Ni, Ag, Au, the Tiw or several on the described chip bulk silicon substrate backside metal level.
5. a kind of micron scale chip size packaging radiation structure according to claim 1 and 2 is characterized in that: described circuit welding pad end face metal salient point (3) material is a kind of among Au or Ag, Cu, Sn, Ni, the Pd or several.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100953499A CN100403527C (en) | 2005-11-09 | 2005-11-09 | Micron scale chip size packaging radiation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100953499A CN100403527C (en) | 2005-11-09 | 2005-11-09 | Micron scale chip size packaging radiation structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1794445A CN1794445A (en) | 2006-06-28 |
| CN100403527C true CN100403527C (en) | 2008-07-16 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100953499A Active CN100403527C (en) | 2005-11-09 | 2005-11-09 | Micron scale chip size packaging radiation structure |
Country Status (1)
| Country | Link |
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| CN (1) | CN100403527C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102142408A (en) * | 2010-01-28 | 2011-08-03 | 江苏长电科技股份有限公司 | Packaging structure of inversed T-shaped locking hole heat-dissipation block of inner pin embedded chip |
| CN102856273A (en) * | 2012-09-06 | 2013-01-02 | 日月光半导体制造股份有限公司 | Semiconductor assembly structure with radiating fin and assembling method thereof |
| WO2020103145A1 (en) * | 2018-11-23 | 2020-05-28 | 北京比特大陆科技有限公司 | Chip heat radiating structure, chip structure, circuit board, and supercomputing device |
| CN112164683A (en) * | 2020-08-24 | 2021-01-01 | 杰群电子科技（东莞）有限公司 | Bare chip packaging structure with metal layer on back surface |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08222885A (en) * | 1995-02-16 | 1996-08-30 | Sumise Device:Kk | Electromagnetic shielding film for package and its formation |
| US20010018800A1 (en) * | 1999-09-17 | 2001-09-06 | George Tzanavaras | Method for forming interconnects |
| CN1332475A (en) * | 2000-06-26 | 2002-01-23 | 智翎股份有限公司 | Heat sink and its manufacture |
| JP2002246508A (en) * | 2001-02-21 | 2002-08-30 | Hitachi Metals Ltd | Package for semiconductor |
| CN1599062A (en) * | 2004-08-20 | 2005-03-23 | 清华大学 | Large-area heat sink structure for large power semiconductor device |
| CN1635634A (en) * | 2003-12-30 | 2005-07-06 | 中芯国际集成电路制造(上海)有限公司 | Method and apparatus for producing welding pad for chip level packaging |
-
2005
- 2005-11-09 CN CNB2005100953499A patent/CN100403527C/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08222885A (en) * | 1995-02-16 | 1996-08-30 | Sumise Device:Kk | Electromagnetic shielding film for package and its formation |
| US20010018800A1 (en) * | 1999-09-17 | 2001-09-06 | George Tzanavaras | Method for forming interconnects |
| CN1332475A (en) * | 2000-06-26 | 2002-01-23 | 智翎股份有限公司 | Heat sink and its manufacture |
| JP2002246508A (en) * | 2001-02-21 | 2002-08-30 | Hitachi Metals Ltd | Package for semiconductor |
| CN1635634A (en) * | 2003-12-30 | 2005-07-06 | 中芯国际集成电路制造(上海)有限公司 | Method and apparatus for producing welding pad for chip level packaging |
| CN1599062A (en) * | 2004-08-20 | 2005-03-23 | 清华大学 | Large-area heat sink structure for large power semiconductor device |
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| Publication number | Publication date |
|---|---|
| CN1794445A (en) | 2006-06-28 |
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