CN1794446A - Micron scale chip size packaging radiation structure - Google Patents
Micron scale chip size packaging radiation structure Download PDFInfo
- Publication number
- CN1794446A CN1794446A CN 200510095350 CN200510095350A CN1794446A CN 1794446 A CN1794446 A CN 1794446A CN 200510095350 CN200510095350 CN 200510095350 CN 200510095350 A CN200510095350 A CN 200510095350A CN 1794446 A CN1794446 A CN 1794446A
- Authority
- CN
- China
- Prior art keywords
- chip
- pit
- silicon substrate
- micron scale
- radiation structure
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
This invention relates to a package radiation structure of a new type mum chip, including a chip, a circuit weld pad set at the positive of a silicon backing of the chip and a metallic convex point implanted on the top of the weld pad characterizing in processing a pit on the back of the silicon backing to form an array or a non-array and implanting a metallic layer on the back of backing of the chip on the pit surface or out of it.
Description
Technical field:
The present invention relates to a kind of novel micron scale chip size packaging radiation structure, is to be applied in integrated circuit (IC) chip or power discrete device chip, or disc grade chip size encapsulation technology field.
Background technology:
In recent years, integrated circuit or discrete device consumer products demand heighten, the also corresponding increase of its kind.The metal wire of disk factory reduces, and the Chip Packaging product moves towards semicon industry development of technology such as miniaturization under the prerequisite of the Performance And Reliability that does not influence product, be the mainstay that satisfies this type of demand.
For many years, the naked brilliant encapsulation of chip is widely used, and this is present profile minimum, does not almost have a kind of packing forms of packing or protective materials.The area of this encapsulation is the same with chip area big.
Before the present invention makes, traditional Chip Packaging, its encapsulated radiating structure is to install metal fin additional at the silicon substrate of chip body or the Ji Dao back side, chip package inside, the heat that chip produced dispels the heat indirectly by exposing Ji Dao.Therefore its heat sinking function or heat conduction function are relatively poor.
Summary of the invention:
The objective of the invention is to overcome above-mentioned deficiency, a kind of novel micron scale chip size packaging radiation structure with preferable heat sinking function or heat conduction function is provided.
The object of the present invention is achieved like this: a kind of novel micron scale chip size packaging radiation structure, comprise the chip body, be arranged at the circuit welding pad in chip bulk silicon base material front, plant the metal salient point that places the circuit welding pad end face, it is characterized in that: make pit in chip bulk silicon substrate backside, form array or non-array; Chip bulk silicon substrate backside outside pit surface and pit is planted metal level.Form heat exchange zone at chip back, produce heat sinking function with air.
Micron scale chip size packaging radiation structure of the present invention, the outer chip bulk silicon substrate backside metal level of described chip bulk silicon substrate backside pit surface and pit has single or multiple lift.
Characteristics of the present invention are to change the packaged type that tradition exposes Ji Dao, with flip-chip packaged technology, bare chip are directly dispelled the heat chip.Therefore have preferable heat sinking function or heat conduction function.
Description of drawings:
Fig. 1 is a schematic diagram behind the novel micron scale chip size packaging radiation structure chip of the present invention bulk silicon substrate backside making pit.
Fig. 1 is a schematic diagram after the novel micron scale chip size packaging radiation structure of the present invention completes.
Embodiment:
Referring to Fig. 1, a kind of novel micron scale chip size packaging radiation structure of the present invention, mainly by chip body 1, be arranged at the circuit welding pad 2 in chip bulk silicon base material front, plant the metal salient point 3 that places the circuit welding pad end face, be made in the pit 4 of chip bulk silicon substrate backside and plant single or multiple lift metal level 5 compositions that place the chip bulk silicon substrate backside outside pit 4 surfaces and the pit.
Outer chip bulk silicon substrate backside metal level 5 materials of described pit surface and pit are a kind of among Ti or Cu, Ni, Au, the Tiw or several.
Described circuit welding pad end face metal salient point 3 materials are a kind of among Au or Ag, Cu, Sn, Ni, the Pd or several.
Concrete manufacture method:
In the bare chip packaging technology, make pit in the etching of chip bulk silicon substrate backside, form array or non-array, as Fig. 1; On the basis that makes pit, adopt sputter, photoetching, etching, evaporation or plating or chemical plating process again, the single or multiple lift metal is implanted pit surface and the outer chip bulk silicon substrate backside of pit, as Fig. 2.
Claims (4)
1, a kind of novel micron scale chip size packaging radiation structure, comprise chip body (1), be arranged at the circuit welding pad (2) in chip body (1) silicon substrate front, plant the metal salient point (3) that places the circuit welding pad end face, it is characterized in that: make pit (4) in chip body (1) the silicon substrate back side, form array or non-array; Chip bulk silicon substrate backside outside pit (4) surface and pit is planted metal level (5).
2, a kind of novel micron scale chip size packaging radiation structure according to claim 1 is characterized in that: the outer chip bulk silicon substrate backside metal level (5) of described pit surface and pit has single or multiple lift.
3, a kind of novel micron scale chip size packaging radiation structure according to claim 2 is characterized in that: outer chip bulk silicon substrate backside metal level (5) material of described pit surface and pit is a kind of among Ti or Cu, Ni, Au, the Tiw or several.
4, according to claim 1 or 2,3 described a kind of novel micron scale chip size packaging radiation structures, it is characterized in that: described circuit welding pad end face metal salient point (3) material is a kind of among Au or Ag, Cu, Sn, Ni, the Pd or several.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510095350 CN1794446A (en) | 2005-11-09 | 2005-11-09 | Micron scale chip size packaging radiation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510095350 CN1794446A (en) | 2005-11-09 | 2005-11-09 | Micron scale chip size packaging radiation structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1794446A true CN1794446A (en) | 2006-06-28 |
Family
ID=36805804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510095350 Pending CN1794446A (en) | 2005-11-09 | 2005-11-09 | Micron scale chip size packaging radiation structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1794446A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105023888A (en) * | 2015-07-08 | 2015-11-04 | 华进半导体封装先导技术研发中心有限公司 | Board-level fan-out chip packaging device and preparation method therefor |
-
2005
- 2005-11-09 CN CN 200510095350 patent/CN1794446A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105023888A (en) * | 2015-07-08 | 2015-11-04 | 华进半导体封装先导技术研发中心有限公司 | Board-level fan-out chip packaging device and preparation method therefor |
| CN105023888B (en) * | 2015-07-08 | 2018-01-16 | 华进半导体封装先导技术研发中心有限公司 | Plate level fan-out-type chip package device and preparation method thereof |
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| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |