CN100399507C - Method for producing polycrystalline silicon - Google Patents
Method for producing polycrystalline silicon Download PDFInfo
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- CN100399507C CN100399507C CNB2005100801602A CN200510080160A CN100399507C CN 100399507 C CN100399507 C CN 100399507C CN B2005100801602 A CNB2005100801602 A CN B2005100801602A CN 200510080160 A CN200510080160 A CN 200510080160A CN 100399507 C CN100399507 C CN 100399507C
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Abstract
The invention relates to a manufacture method of polysilicon. First, supply a base and form a non-silicon layer on the base. Then, form a cushion layer on the non-silicon layer and coat the metal catalyzing solution on the cushion layer. The metal catalyzing solution includes the metal-salt and the solvent. Roast to remove the solvent of the metal catalyzing solution so that the metal-salt can adhere to the cushion layer surface. Annealing to make the metal ion of the metal-salt go into the non-silicon layer through the cushion layer and induce the non-silicon layer crystallization to form the polysilicon layer. Remove the cushion layer and the metal-salt left on it. The method prevents the polysilicon layer leaving too much metal silicide and metal atom to improve the electric capability of the polsilicon layer.
Description
Technical field
The present invention relates to a kind of manufacture method of polysilicon, relate in particular to a kind of applied metal and bring out the method that side crystallization technique is made polysilicon.
Background technology
Along with high-tech development, video product, particularly digitlization video signal or device for image become in the general daily life common product.In these digitlization video signals or device for image, display is a critical elements, to show relevant information.The user can read information by display, or and then the running of control device.
Because thin-film transistor (TFT) can be applicable to LCD (liquid crystaldisplay, abbreviation LCD) driving element, make this product become a main flow of last straight formula type flat-panel screens, become following dominance product in markets such as personal computer, Game device, monitors.At present, because of amorphous silicon (amorphous silicon claims a-Si again) thin-film transistor can generate in 200-300 degree centigrade low temperature, therefore be widely used.Because the electron mobility (electronmobility) of amorphous silicon is low, be no more than 1cm2/V.s, make amorphous silicon film transistor not apply present high speed element demands of applications, and polysilicon (polycrystalline silicon, claim ploy-Si again) thin-film transistor is compared with amorphous silicon film transistor higher mobility is arranged (approximately than the high 2-3 of an amorphous silicon order of magnitude) and low-temperature sensitive (low temperature sensitivity), make it more be applicable to high speed element.Yet when the amorphous silicon of annealing in a conventional manner formed polysilicon, its formation temperature needed more than 600 degrees centigrade, so the general quartz (quartz) that uses is as substrate.Because the quartz base plate cost is expensive more a lot of than glass substrate, and under the restriction of substrate size, panel approximately only has 2 to 3 inches, therefore can only develop small panel in the past.
Must use glass substrate in order to reduce cost at present, so the formation temperature of polysilicon is reduced to below 500 degrees centigrade.Therefore, many low temperature polycrystalline silicon formation methods are used one after another, wherein attract attention with quasi-molecule laser annealing technology (excimer laser annealing is called for short ELA) and metal inducement side crystallization technology (metali nduced lateral crystallization is called for short MILC).Wherein, the crystallization mode of metal inducement side crystallization technology is based on lateral growth (lateralgrowth), it is after amorphous silicon layer forms, form catalyzing metal layer (catalysismetallayer), in order to promote the crystallization of amorphous silicon layer, and after metal level forms, carry out low temperature annealing process (low temperature annealing process), to form polysilicon layer.
Employed catalyzing metal layer in the metal inducement side crystallization technology can diffuse in the amorphous silicon layer when process annealing, and forms metal silicide (metal silicide), to induce recrystallized amorphous silicon by this metal silicide.Yet,, therefore may form too much metal silicide or metallic atom on the amorphous silicon layer surface because known metal inducement side crystallization technology is directly catalytic metal to be deposited upon the amorphous silicon layer surface.Thus, too much metal silicide or metallic atom content may cause the phenomenon of leakage current (current leakage) increase of polysilicon layer, and influence the electrical property performance of polysilicon layer.In addition, if desire metal silicide that this is too much or metallic atom by separating out in the polysilicon layer, then need carry out complicated technology, increased manufacturing cost relatively.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of manufacture method of polysilicon, it can avoid residual too much metal silicide or metallic atom in polysilicon layer effectively, and then promotes the electrical property of polysilicon layer.
Another object of the present invention is to provide a kind of manufacture method of polysilicon, it need not use vacuum coating equipment to form catalyzing metal layer, therefore can reduce the technology cost.
Another purpose of the present invention is to provide a kind of manufacture method of polysilicon, and it can adjust the concentration of catalytic metal, to form the polysilicon layer of better quality.
Based on above-mentioned or other purpose, the present invention proposes a kind of manufacture method of polysilicon.At first, provide substrate, and on this substrate, form amorphous silicon layer.Then, on amorphous silicon layer, form first resilient coating, and on first resilient coating coating metal catalytic solution, wherein this metal catalytic solution comprises metallic salt (metal salt) and solvent (solvent).Then, the baking substrate to remove the solvent in the metal catalytic solution, makes metallic salt be attached to first buffer-layer surface.Then, carry out annealing in process,, in above-mentioned amorphous silicon layer, generating metal silicide, and induce the amorphous silicon layer crystallization to become polysilicon layer by this metal silicide so that the metal ion of metallic salt enters in the amorphous silicon layer by first resilient coating.Afterwards, remove first resilient coating and on institute's metal remained salt.
In one of the present invention preferred embodiment, the thickness of above-mentioned first resilient coating for example is between 100 dust to 1000 dusts.In addition, the material of this first resilient coating for example is silica (SiOx) or silicon nitride (SiNx).
In one of the present invention preferred embodiment, above-mentioned metallic salt comprises nickel nitrate (nickelnitrate), aluminum nitrate (aluminum nitrate) or copper nitrate (copper nitrate).
In one of the present invention preferred embodiment, the method for coating metal catalytic solution comprises method of spin coating (spin coating) or ink-jet method (inkjet printing) on first resilient coating.
In one of the present invention preferred embodiment, aforesaid substrate for example is a glass substrate.
In one of the present invention preferred embodiment, before forming amorphous silicon layer, also be included in and form second resilient coating on the substrate.In addition, the material of this second resilient coating comprises silica or silicon nitride, and the method that forms second resilient coating for example is chemical vapour deposition technique (chemical vapor deposition) or sputtering method (sputtering).
In one of the present invention preferred embodiment, the method that forms the amorphous silicon layer and first resilient coating on substrate for example is chemical vapour deposition technique or sputtering method.In addition, the method that removes first resilient coating for example is dry ecthing (dry etching) or wet etching (wet etching).
Based on above-mentioned, the present invention forms resilient coating on amorphous silicon layer, again with the metal catalytic solution coat in buffer-layer surface, therefore can avoid catalytic metal directly to contact with amorphous silicon.Thus, can reduce metal silicide or metallic atom content in the formed polysilicon layer effectively, and then improve the electrical property of polysilicon layer.In addition, because catalytic metal is the solution kenel, therefore can adjust the concentration of catalytic metal easily, in the hope of obtaining best reaction effect.
State with other purpose, feature and advantage and can become apparent on the present invention for allowing, preferred embodiment cited below particularly, and cooperate appended accompanying drawing, be described in detail below.
Description of drawings
Figure 1A～1G is followed successively by the schematic diagram of a kind of polysilicon process of the present invention.
Fig. 2 A～2H is followed successively by the schematic diagram of making low-temperature polysilicon film transistor in the viewing area of thin-film transistor array base-plate and periphery circuit region simultaneously.
The main element description of symbols
100: substrate
110: resilient coating
120: amorphous silicon layer
120a: polysilicon layer
130: resilient coating
140: metal catalytic solution
142: metallic salt
200: substrate
200a, 200b: island polysilicon layer
202: resilient coating
204a, 204b: channel region
206,214,220: the patterning photoresist layer
210: source electrode
212: gate insulator
218,224: shallow doped-drain zone
226a and 226b: grid
228: interlayer dielectric layer
230,236: opening
232: the source/drain contacting metal
234: protective layer
238: pixel electrode
Embodiment
Please refer to Figure 1A～1G, it is followed successively by the schematic diagram of a kind of polysilicon process of the present invention.
At first, shown in Figure 1A, provide substrate 100, it for example is glass substrate or other substrate that is suitable for, as silicon wafer or plastic base etc.In addition, in one embodiment, for example can pass through chemical vapour deposition technique (chemical vapor deposition, CVD) or sputtering method modes such as (sputtering) on substrate 100, form resilient coating 110, it for example is the stack layer that silicon nitride layer and silicon oxide layer are formed.The main effect of this resilient coating 110 is to promote the tack of substrate 100 and the polysilicon layer of follow-up formation, and when metal ion such as sodium is arranged in the substrate 100, can prevent the metal ion pollution polysilicon layer in the substrate 100.
Then, shown in Figure 1B, form amorphous silicon layer 120 on substrate 100, the method that wherein forms this amorphous silicon layer 120 for example is chemical vapour deposition technique or sputtering method.
Then, shown in Fig. 1 C, form another resilient coating 130 on amorphous silicon layer 120, its material for example is silicon nitride or silica, and thickness for example is between 100 dust to 1000 dusts.Wherein, the thickness of the resilient coating 130 of the required formation of foundation can be selected suitable manufacture, for example chemical vapour deposition technique or sputtering method.The purpose that forms this resilient coating 130 is to diffuse in the amorphous silicon layer 120 to avoid excessive catalytic metal the effect of buffering is provided between the catalytic metal of follow-up formation and the amorphous silicon layer 120.Thickness that it should be noted that the resilient coating 130 that present embodiment proposes is a preferred range, wherein if the thickness of resilient coating 130 less than 100 dusts, then Huan Chong effect is limited.In addition, if the thickness of resilient coating 130 then will increase catalytic metal diffuses into amorphous silicon layer 120 by resilient coating 130 time greater than 1000 dusts.Certainly, in practical application, the concentration that should look catalytic metal decides the thickness of resilient coating 130.
Then, shown in Fig. 1 D-1 and 1D-2, coating metal catalytic solution 140 on resilient coating 130.In the present invention, the method that forms metal catalytic solution 140 for example is method of spin coating or ink-jet method etc., wherein Fig. 1 D-1 is the schematic diagram that forms metal catalytic solution by method of spin coating, and Fig. 1 D-2 is the schematic diagram that forms metal catalytic solution by ink-jet method.Wherein, if adopt method of spin coating, be metal catalytic solution 140 to be coated on the resilient coating 130 comprehensively.In addition, if adopt ink-jet method, then, so can simplify technology, and can reduce the use amount of metal catalytic solution 140, to reduce cost optionally at the specific region sprinkling metal catalytic solution 140 that need change polysilicon into by amorphous silicon.
In addition, above-mentioned metal catalytic solution 140 for example is solution such as nickel nitrate, aluminum nitrate or copper nitrate, and its concentration of metal ions can adjust according to technology is required (for example be thousands of to tens thousand of ppm).Because the present invention reacts by metal catalytic solution 140, therefore can adjust the concentration of the metallic salt (as nickel nitrate, aluminum nitrate or copper nitrate etc.) in the metal catalytic solution 140 easily, and do not have knownly because of uncontrollable catalytic metal concentration, cause excessive catalytic metal to diffuse into the problem of amorphous silicon layer 120.
Then, shown in Fig. 1 E, the step of toasting to remove the solvent part in the metal catalytic solution 140, makes metallic salt 142 (as nickel nitrate, aluminum nitrate or copper nitrate etc.) be attached to resilient coating 130 surfaces.
Then, shown in Fig. 1 F, carry out annealing in process, so that the metal ion in the metallic salts such as nickel nitrate, aluminum nitrate or copper nitrate 142 enters in the amorphous silicon layer 120 by resilient coating 130, in amorphous silicon layer 120, generating metal silicide, and induce amorphous silicon layer 120 crystallizations becoming polysilicon layer 120a by metal silicide.
Afterwards, shown in Fig. 1 G, remove resilient coating 130 and on institute's metal remained salt 142, the method that wherein removes resilient coating 130 comprises modes such as dry ecthing or wet etching.
After the manufacturing of finishing above-mentioned polysilicon layer, for example can carry out follow-up film-forming process again, to form for example semiconductor element such as thin-film transistor.Hereinafter will be with in the thin-film transistor array base-plate, the technology of low-temperature polysilicon film transistor is that example describes.
Please refer to Fig. 2 A～2H, it is followed successively by the schematic diagram of making low-temperature polysilicon film transistor in the viewing area of thin-film transistor array base-plate and periphery circuit region simultaneously.
At first, shown in Fig. 2 A, on the substrate 200 the manufacture method by above-mentioned polysilicon be formed with a plurality of island polysilicon layer 200a, 200b, wherein island polysilicon layer 200a for example is the some of the predetermined P of formation type thin-film transistor, and island polysilicon layer 200b for example is the some of the predetermined N of formation type thin-film transistor, and in after description form the technology of P type and N type thin-film transistor simultaneously.But the present invention is not limited to make simultaneously the manufacturing process of P type and N type thin-film transistor, and only is when an example that explains feature of the present invention with present embodiment.
Afterwards, shown in Fig. 2 B, carry out channel doping technology (channel doping), in each island polysilicon layer 200a, 200b, to form doped region.
Then, shown in Fig. 2 C, on substrate 200, form patterning photoresist layer 206,, and expose island polysilicon layer 200b both sides upper surface with covering island polysilicon layer 200a and part island polysilicon layer 200b.Afterwards, carry out n
+Doping process is to form the source electrode 210 of N type thin-film transistor in island polysilicon layer 200b both sides.
Then, shown in Fig. 2 D, remove patterning photoresist layer 206, again cover gate insulating barrier 212 on island polysilicon layer 200a, 200b and resilient coating 202.Then, on gate insulator 212, form another patterning photoresist layer 214,, and expose the position that is close to source electrode 210 among the island polysilicon layer 200b with covering island polysilicon layer 200a and part island polysilicon layer 200b.Subsequently, carry out n
-Doping process to form the shallow doped-drain zone 218 of N type thin-film transistor, defines the channel region 204b between shallow doped-drain zone 218 simultaneously.
Then, shown in Fig. 2 E, remove patterning photoresist layer 214, on gate insulator 212, form another patterning photoresist layer 220 again, covering island polysilicon layer 200b and part island polysilicon layer 200a, and expose the position of island polysilicon layer 200b both sides upper surface.Subsequently, carry out p
+Doping process to form the source electrode 224 of P type thin-film transistor, defines the channel region 204a between source electrode 224 simultaneously.
Afterwards, shown in Fig. 2 F, remove patterning photoresist layer 220, go up formation grid 226a and 226b in channel region 204a and 204b again.Then, on substrate 100, form interlayer dielectric layer (inter-layer dielectric is called for short ILD) 228, to cover island polysilicon layer 200a, 200b and grid 226a, 226b.
Then, shown in Fig. 2 G, in interlayer dielectric layer 228 and gate insulator 212, form a plurality of openings 230, to expose source electrode 210 and 224, form a plurality of source/drain contacting metals 232 again, source/drain contacting metal 232 is to electrically connect with source electrode 210 and 224 by opening 230.
Afterwards, shown in Fig. 2 H, form protective layer 234 on substrate 200, form another opening 236 again in protective layer 234, to expose part source/drain contacting metal 232, wherein protective layer 234 for example is a silicon nitride layer.At last, form pixel electrode 238, pixel electrode 238 is electrical connected with part source/drain contacting metal 232 by opening 236, and wherein the material of pixel electrode 238 for example is indium tin oxide (ITO).
In sum, the manufacture method of crystal silicon has following feature and advantage at least more than the present invention:
1. on amorphous silicon layer, form resilient coating, reducing metal silicide or the metallic atom content in the formed polysilicon layer, and then improve the electrical property of polysilicon layer and formed semiconductor element.
2. use metal catalytic solution, therefore can adjust the concentration of catalytic metal easily, in the hope of obtaining best reaction effect.
3. need not use vacuum coating equipment to form catalyzing metal layer, therefore help to reduce the technology cost.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any described those skilled in the art; without departing from the spirit and scope of the invention; when can doing a little change and improvement, so the present invention's protection range attached claim person of defining after looking is as the criterion.
Claims (12)
1. the manufacture method of a polysilicon is characterized in that comprising:
Substrate is provided;
On aforesaid substrate, form amorphous silicon layer;
On above-mentioned amorphous silicon layer, form first resilient coating;
Coating metal catalytic solution on above-mentioned first resilient coating, this metal catalytic solution comprises metallic salt and solvent;
The baking aforesaid substrate to remove the above-mentioned solvent in the above-mentioned metal catalytic solution, makes above-mentioned metallic salt be attached to above-mentioned first buffer-layer surface;
Carry out annealing in process, so that the metal ion in the above-mentioned metallic salt enters in the above-mentioned amorphous silicon layer by above-mentioned first resilient coating, in above-mentioned amorphous silicon layer, generating metal silicide, and induce this amorphous silicon layer crystallization to become polysilicon layer by this metal silicide; And
Remove above-mentioned first resilient coating and on residual above-mentioned metallic salt.
2. the manufacture method of polysilicon according to claim 1, the thickness that it is characterized in that above-mentioned first resilient coating is between 100 dust to 1000 dusts.
3. the manufacture method of polysilicon according to claim 1 is characterized in that the material of above-mentioned first resilient coating comprises silica or silicon nitride.
4. the manufacture method of polysilicon according to claim 1 is characterized in that above-mentioned metallic salt comprises nickel nitrate, aluminum nitrate or copper nitrate.
5. the manufacture method of polysilicon according to claim 1 is characterized in that the method for the above-mentioned metal catalytic solution of coating on above-mentioned first resilient coating comprises method of spin coating or ink-jet method.
6. the manufacture method of polysilicon according to claim 1 is characterized in that aforesaid substrate is a glass substrate.
7. the manufacture method of polysilicon according to claim 1 is characterized in that before forming above-mentioned amorphous silicon layer, also was included in and formed second resilient coating on the aforesaid substrate.
8. the manufacture method of polysilicon according to claim 7 is characterized in that the material of above-mentioned second resilient coating comprises silica or silicon nitride.
9. the manufacture method of polysilicon according to claim 7 is characterized in that the method that forms above-mentioned second resilient coating on aforesaid substrate comprises chemical vapour deposition technique or sputtering method.
10. the manufacture method of polysilicon according to claim 1 is characterized in that the method that forms above-mentioned amorphous silicon layer on aforesaid substrate comprises chemical vapour deposition technique or sputtering method.
11. the manufacture method of polysilicon according to claim 1 is characterized in that the method that forms above-mentioned first resilient coating on above-mentioned amorphous silicon layer comprises chemical vapour deposition technique or sputtering method.
12. the manufacture method of polysilicon according to claim 1 is characterized in that the method that removes above-mentioned first resilient coating comprises dry ecthing or wet etching.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005100801602A CN100399507C (en) | 2005-06-30 | 2005-06-30 | Method for producing polycrystalline silicon |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005100801602A CN100399507C (en) | 2005-06-30 | 2005-06-30 | Method for producing polycrystalline silicon |
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| CN1889232A CN1889232A (en) | 2007-01-03 |
| CN100399507C true CN100399507C (en) | 2008-07-02 |
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| CNB2005100801602A Expired - Fee Related CN100399507C (en) | 2005-06-30 | 2005-06-30 | Method for producing polycrystalline silicon |
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| CN104538350A (en) * | 2014-12-30 | 2015-04-22 | 深圳市华星光电技术有限公司 | Polycrystalline silicon substrate and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040166655A1 (en) * | 2003-02-24 | 2004-08-26 | Man Wong | Methods for forming laterally crystallized polysilicon and devices fabricated therefrom |
| US6830965B1 (en) * | 2000-10-25 | 2004-12-14 | Sharp Laboratories Of America, Inc. | Semiconductor device and a method of creating the same utilizing metal induced crystallization while suppressing partial solid phase crystallization |
| CN1595613A (en) * | 2004-06-30 | 2005-03-16 | 吉林大学 | A method for making metal induced polysilicon film having diffuse layer above metal |
| US20050116292A1 (en) * | 2003-11-27 | 2005-06-02 | Jae-Bon Koo | Thin film transistor using a metal induced crystallization process and method for fabricating the same and active matrix flat panel display using the thin film transistor |
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2005
- 2005-06-30 CN CNB2005100801602A patent/CN100399507C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6830965B1 (en) * | 2000-10-25 | 2004-12-14 | Sharp Laboratories Of America, Inc. | Semiconductor device and a method of creating the same utilizing metal induced crystallization while suppressing partial solid phase crystallization |
| US20040166655A1 (en) * | 2003-02-24 | 2004-08-26 | Man Wong | Methods for forming laterally crystallized polysilicon and devices fabricated therefrom |
| US20050116292A1 (en) * | 2003-11-27 | 2005-06-02 | Jae-Bon Koo | Thin film transistor using a metal induced crystallization process and method for fabricating the same and active matrix flat panel display using the thin film transistor |
| CN1595613A (en) * | 2004-06-30 | 2005-03-16 | 吉林大学 | A method for making metal induced polysilicon film having diffuse layer above metal |
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| CN1889232A (en) | 2007-01-03 |
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