CN105321825A - Low temperature polycrystalline silicon thin film transistor and manufacturing method therefor - Google Patents
Low temperature polycrystalline silicon thin film transistor and manufacturing method therefor Download PDFInfo
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- CN105321825A CN105321825A CN201510799096.7A CN201510799096A CN105321825A CN 105321825 A CN105321825 A CN 105321825A CN 201510799096 A CN201510799096 A CN 201510799096A CN 105321825 A CN105321825 A CN 105321825A
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- buffer pad
- conductie buffer
- drain region
- conductie
- film transistor
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000010409 thin film Substances 0.000 title abstract description 5
- 239000010410 layer Substances 0.000 claims description 117
- 229920005591 polysilicon Polymers 0.000 claims description 52
- 239000011248 coating agent Substances 0.000 claims description 32
- 238000000576 coating method Methods 0.000 claims description 32
- 239000012212 insulator Substances 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 25
- 239000011229 interlayer Substances 0.000 claims description 23
- 238000000059 patterning Methods 0.000 claims description 22
- 239000004020 conductor Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 16
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 12
- 239000007769 metal material Substances 0.000 claims description 9
- 238000001459 lithography Methods 0.000 claims description 8
- 239000000428 dust Substances 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 3
- 239000010408 film Substances 0.000 description 34
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 239000012528 membrane Substances 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- -1 boron ion Chemical class 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000004035 construction material Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a low temperature polycrystalline silicon thin film transistor and a manufacturing method therefor. A conductive buffer cushion is arranged in a source electrode region and a drain electrode region for preventing the polycrystalline silicon in a contact hole from being etched; and the electrical conductivity among the polycrystalline silicon layer, the source electrode and the drain electrode is improved so as to reduce contact resistance and improve the assembly performance of the polycrystalline silicon thin film transistor.
Description
[technical field]
The present invention relates to a kind of manufacture method of thin-film transistor, and particularly relate to a kind of low-temperature polysilicon film transistor and preparation method thereof.
[background technology]
Along with the development of semiconductor technology, video product, particularly digitized video or device for image have become product common in general daily life.In these digitized videos or device for image, display is a significant components, to show relevant information.And low-temperature polysilicon film transistor (LTPSTFT) can be applicable to the driven unit of liquid crystal display, make this product become the main flow of display, become following dominance product in markets such as personal calculator, game machine, monitors.
In the process structure of low-temperature polysilicon film transistor (LTPSTFT) display panels, at interlayer dielectric layer (inter-layerdielectric, ILD) in manufacturing process, impact because of making technology causes the film loss amount property of there are differences of polysilicon layer in via hole, cause the in uneven thickness of the film loss amount of polysilicon in interlayer dielectric layer via hole, thus cause the contact impedance between polysilicon layer and source electrode/drain electrode unequal and excessive, even contact area is too little, cause the electrical property difference of thin-film transistor clearly, thus affect the assembly property of low-temperature polysilicon film transistor.
As shown in Figure 1, in the prior art, in traditional low-temperature polysilicon film transistor fabrication processing, first buffer layer 102, active layer 104, gate insulator 106, gate electrode 108 over the glass substrate 100, then make interlayer dielectric layer (ILD) 110 and carry out being etched to the polysilicon membrane of active layer 104, then source electrode/drain electrode 112 is formed, to form polycrystal silicon film transistor (TFT).The etch process of interlayer dielectric layer 110 directly can be etched to polycrystalline silicon membrane, causes the loss of polysilicon membrane; Simultaneously via hole 114 bottom area of interlayer dielectric layer 110 and polysilicon membrane and source electrode/drain electrode 112 metal contact area less, the Metal Contact impedance of polysilicon membrane and source electrode/drain electrode 112 is larger.
Therefore the manufacture method developing a kind of new-type low-temperature polysilicon film transistor is needed, too little with the contact area solved between above-mentioned polysilicon layer and source electrode/drain electrode, cause the problem that contact impedance is excessive.
[summary of the invention]
Supervise in this; the object of the present invention is to provide a kind of low-temperature polysilicon film transistor and preparation method thereof; by the conductie buffer pad on source area and drain region; do not etched to protect the polysilicon layer in contact hole; and increase conductivity between polysilicon layer and source electrode and drain electrode; to reduce contact impedance, improve the assembly property of low-temperature polysilicon film transistor.
To achieve the above object of the invention, a kind of low-temperature polysilicon film transistor and preparation method thereof is provided in first embodiment of the invention, it is characterized in that, comprise the following steps:
One substrate is provided;
Form a resilient coating on the substrate;
Described resilient coating is formed an amorphous silicon layer;
Anneal to form a polysilicon layer to described amorphous silicon layer by an annealing process, and polysilicon layer described in patterning, to form an active layer on described resilient coating, wherein said active layer comprises source area, drain region and channel region, and described channel region is arranged between described source area and described drain region;
A conductive material layer is formed on described active layer and on the resilient coating exposed to the open air;
Conductive material layer described in patterning and the described conductive material layer of etch patterning, to form one first conductie buffer pad and one second conductie buffer pad on the described source area of described active layer and on described drain region respectively, described source area and described drain region is made to be formed in electrical contact with described first conductie buffer pad and described second conductie buffer pad respectively;
A gate insulator is formed on described resilient coating, on described source area, on described drain region and on described channel region;
Described gate insulator is formed a grid material layers, and grid material layers described in patterning, with the grid material layers of lithography patterning, to form a gate electrode;
Interbedded insulating layer is formed on described gate electrode and on the gate insulator exposed to the open air;
Interlayer insulating film described in patterning, and the interlayer insulating film of lithography patterning and described gate insulator, to form contact hole in described interlayer insulating film and described gate insulator, and in described contact hole, expose described first conductie buffer pad and described second conductie buffer pad to the open air;
In described contact hole, form one source pole electrode and a drain electrode, make described source electrode and described drain electrode be electrically connected described first conductie buffer pad and described second conductie buffer pad respectively.
In one embodiment, the width of described first conductie buffer pad equals or is less than the width of source area, and the width of described second conductie buffer pad equals or is less than the width of drain region.
In one embodiment, the contact area of described first conductie buffer pad and described source area is greater than the contact area of described source electrode and described first conductie buffer pad, and the contact area of described second conductie buffer pad and described drain region is greater than the contact area of described drain electrode and described second conductie buffer pad.
In one embodiment, the thickness of described first conductie buffer pad and described second conductie buffer pad is between 2 dust to 800 dusts.
In one embodiment, the material of described conductive material layer is the metal material with conductivity.
In one embodiment, formed in the step of described active layer on described resilient coating, be included on described active layer and on described resilient coating and form a material layers as cover curtain, to carry out dopping process to described active layer, to form described source area and described drain region.
In another embodiment of the present invention, a kind of low-temperature polysilicon film transistor, comprises for display panels: a resilient coating, is arranged on a substrate; One active layer, being formed on described resilient coating and being made up of polysilicon material, described active layer comprises source area, drain region and channel region, and described channel region is arranged between described source area and described drain region; One conductive material layer, comprise one first conductie buffer pad and one second conductie buffer pad, described first conductie buffer pad is arranged on the described source area of described active layer, to be electrically connected described source area, described second conductie buffer pad is arranged on the described drain region of described active layer, to be electrically connected described drain region; One gate insulator, is formed on described resilient coating, on described source area, on described drain region and on described channel region; Interbedded insulating layer, is formed on described gate electrode and on the gate insulator exposed to the open air; Some contact holes, are formed in described interlayer insulating film and described gate insulator, and in described contact hole, expose described first conductie buffer pad and described second conductie buffer pad to the open air; Some electrodes, comprise a gate electrode, one source pole electrode and a drain electrode, described gate electrode is formed on described gate insulator, described source electrode is formed in described contact hole, described source electrode is electrically connected described first conductie buffer pad, described drain electrode is formed in described contact hole, and described drain electrode is electrically connected described second conductie buffer pad.
In one embodiment, the width of described first conductie buffer pad equals or is less than the width of source area, and the width of described second conductie buffer pad equals or is greater than the width of drain region.
In one embodiment, the contact area of described first conductie buffer pad and described source area is greater than the contact area of described source electrode and described first conductie buffer pad, and the contact area of described second conductie buffer pad and described drain region is greater than the contact area of described drain electrode and described second conductie buffer pad.
In one embodiment, the thickness of described first conductie buffer pad and described second conductie buffer pad is between 2 dust to 800 dusts, and the material of wherein said first conductie buffer pad and described second conductie buffer pad is metal material or the non-metallic material with conductivity.
[accompanying drawing explanation]
Fig. 1: be the part-structure schematic diagram of low-temperature polysilicon film transistor of the prior art.
Fig. 2-8: be the generalized section of the Making programme step according to low-temperature polysilicon film transistor in the embodiment of the present invention.
[embodiment]
Specification of the present invention provides different embodiment so that the technical characteristic of the different execution mode of the present invention to be described.The configuration of each assembly in embodiment is the content disclosed to clearly demonstrate the present invention, and is not used to limit the present invention.Different graphic in, identical element numbers represents same or analogous assembly.
With reference to the generalized section that figure 2-8, Fig. 2-8 is the Making programme step according to low-temperature polysilicon film transistor in the embodiment of the present invention.As shown in Figure 2, a substrate 200 is provided.In one embodiment, substrate 200 is such as glass substrate, quartz base plate, stainless steel substrate or plastic base.
As shown in Figure 2, described substrate 200 forms a resilient coating 202.In one embodiment, comprise with physical vaporous deposition (physicalvapordeposition, PVD), chemical vapour deposition technique (chemicalvapordeposition, or PECVD (plasmaenhancedchemicalvapordeposition, PECVD) forms described resilient coating 202 CVD).Described resilient coating 202 optionally can be arranged on substrate 200 according to actual demand, diffuse in the material layers of follow-up formation in manufacturing process to avoid the impurity in substrate 200, resilient coating 202 is such as the individual layer that forms of silicon oxide layer, silicon nitride layer and silicon oxynitride layer or sandwich construction material layers structure, is not construed as limiting in the present invention.
As shown in Figure 2, formed an amorphous silicon layer (amorphoussilicon) (not shown) at described resilient coating 202.Described amorphous silicon layer can be grown up at low temperature 200 to 300 degree low temperature Celsius.In one embodiment, described amorphous silicon layer is formed with chemical vapour deposition technique (CVD).
As shown in Figure 2, anneal to form a polysilicon layer (not shown) to described amorphous silicon layer by an annealing process, and polysilicon layer described in patterning, to form an active layer 206 on described resilient coating 202, wherein said active layer 206 comprises source area 206a, drain region 206b and channel region 206c, and described channel region 206c is arranged between described source area 206a and described drain region 206b.In one embodiment, excimer laser annealing (excimerlaserannealing, ELA) processing procedure anneals to form described polysilicon layer to described amorphous silicon layer, described amorphous silicon layer melting to be made the silicon molecule recrystallization in described amorphous silicon layer, to form described polysilicon layer, using the material layers as active layer 206.In one embodiment, active layer 206 also comprises lightly-doped source polar region 206a1 between source area 206a and channel region 206c, and comprises lightly mixed drain area 206b1 between drain region 206b and channel region 206c.A material layers is formed as cover curtain, to carry out dopping process to described active layer 206, to form described source area 206a and described drain region 206b on described active layer 206 and on described resilient coating 202.In one embodiment, such as plant (ionimplant) processing procedure with ion cloth to plant active layer 216 cloth, that is passage doping (channeldoping), the ion implanted can be P type or N-type dopant, P type alloy is such as boron ion, and N-type dopant is such as phosphonium ion.
As shown in Figure 3, on described active layer 206 and on the resilient coating 202 exposed to the open air, a conductive material layer 208 is formed.
As shown in Figure 3 and 4, conductive material layer 208 described in patterning and the described conductive material layer 208 of etch patterning, such as using photoresist layer 209 as etch mask, to form one first conductie buffer pad 208a and one second conductie buffer pad 208b on the described source area 206a of described active layer 206 and on described drain region 206b respectively, described source area 206a and described drain region 206b is made to be formed in electrical contact with described first conductie buffer pad 208a and described second conductie buffer pad 208b respectively.In one embodiment, the width of described first conductie buffer pad 208a equals or is less than the width of source area 206a, and the width of described second conductie buffer pad 208b equals, is less than or is greater than the width of drain region 206b.The thickness of described first conductie buffer pad 208a and described second conductie buffer pad 208b is between 2 dust to 800 dusts.The material of described conductive material layer 208 is the metal material with conductivity, is better with the conductive material of high conductivity.
As shown in Figure 5, on described resilient coating 202, on described source area 206a, on described drain region 206b and on described channel region 206c, a gate insulator 210 is formed.In one embodiment, described gate insulator 210 is formed with physical vaporous deposition (PVD) or chemical vapour deposition technique (CVD).Described gate insulator 210 is formed a grid material layers (non-icon), and grid material layers described in patterning, with the grid material layers of lithography patterning, to form a gate electrode 212.In one embodiment, comprise and form a grid material layers with sputter process, physical vaporous deposition or chemical vapour deposition technique, and lithography step is carried out to described grid material layers, to form described gate electrode 212.
As shown in Figure 6, on described gate electrode and on the gate insulator exposed to the open air, interbedded insulating layer 213 is formed.
As shown in Figure 6, interlayer insulating film 213 described in patterning, and the interlayer insulating film 213 of lithography patterning and described gate insulator 210, to form contact hole 214 in described interlayer insulating film 213 and described gate insulator 210, and in described contact hole 214, expose described first conductie buffer pad 208a and described second conductie buffer pad 208b to the open air.
Described interlayer insulating film 213 is such as interlayer insulating film (inter-layer).In one embodiment, interlayer insulating film 213 described in interlayer insulating film 213 described in patterning and lithography, to expose source area 206a and drain region 206b.The material of described interlayer insulating film 213 is such as silica, silicon nitride and silicon oxynitride, or other isolation material.
As shown in Figure 7, in described contact hole 214, form an one source pole electrode 216a and drain electrode 216b, make described source electrode 216a and described drain electrode 216b be electrically connected described first conductie buffer pad 208a and described second conductie buffer pad 208b respectively.
As shown in Figure 7, in a preferred embodiment, the width of the first conductie buffer pad 208a and the second conductie buffer pad 208b is greater than the width bottom source electrode 216a and drain electrode 216b.In a preferred embodiment, the contact area of described first conductie buffer pad 208a and described source area 206a is greater than the contact area of described source electrode and described first conductie buffer pad 208a, and the contact area of described second conductie buffer pad 208b and described drain region 206b is greater than the contact area of described drain electrode 216b and described second conductie buffer pad 208b.The low-temperature polysilicon film transistor of the present invention and manufacture method can avoid source area 206a, drain region 206b etched, reduce source area 206a and source electrode 216a, contact impedance between drain region 206b and drain electrode 216b simultaneously.
As shown in Figure 8, sequentially flatness layer 218, first indium tin oxide layer 220, dielectric protection layer 222 and the second indium tin oxide layer 224 (such as pixel indium tin oxide layer) is formed, to complete the processing procedure of the multiple substrate of display panels.
Continue with reference to figure 8, the low-temperature polysilicon film transistor of the present invention, for display panels, comprising: resilient coating 202 is arranged on a substrate 200; Active layer 206 to be formed on described resilient coating 202 and to be made up of polysilicon material, described active layer 206 comprises source area 206a, drain region 206b and channel region 206c, and described channel region 206c is arranged between described source area 206a and described drain region 206b; One conductive material layer 208 comprises one first conductie buffer pad 208a and one second conductie buffer pad 208b, described first conductie buffer pad 208a is arranged on the described source area 206 of described active layer, to be electrically connected described source area 206a, described second conductie buffer pad 208b is arranged on the described drain region 206b of described active layer 206, to be electrically connected described drain region 206b; One gate insulator 210 is formed on described resilient coating 202, on described source area 206a, on described drain region 206b and on described channel region 206c; Interbedded insulating layer 213 is formed on described gate electrode 212 and on the gate insulator 210 exposed to the open air; Some contact holes 214 are formed in described interlayer insulating film 213 and described gate insulator 210, and in described contact hole 214, expose described first conductie buffer pad 208a and described second conductie buffer pad 208b to the open air; Some electrodes 216, comprise source electrode 216a, drain electrode 216b and gate electrode 212, described gate electrode 212 is formed on described gate insulator 210, described source electrode 216a is formed in described contact hole 214, described source electrode 216a is electrically connected described first conductie buffer pad 208a, described drain electrode 216b is formed in described contact hole 214, and described drain electrode 216b is electrically connected described second conductie buffer pad 208b.
In one example, the width of described first conductie buffer pad 208a equals or is less than the width of source area 206a, and the width of described second conductie buffer pad 208b equals or is greater than the width of drain region 206b.
In one example, the contact area of described first conductie buffer pad 208a and described source area 206a is greater than the contact area of described source electrode 216a and described first conductie buffer pad 208a, and the contact area of described second conductie buffer pad 208b and described drain region 206b is greater than the contact area of described drain electrode 216b and described second conductie buffer pad 208b.
In one example, the thickness of described first conductie buffer pad 208a and described second conductie buffer pad 208b is between 2 dust to 800 dusts, and the material of wherein said first conductie buffer pad 208a and described second conductie buffer pad 208b is metal material or the non-metallic material with conductivity.
Low-temperature polysilicon film transistor of the present invention and preparation method thereof; by the conductie buffer pad on source area and drain region; do not etched to protect the polysilicon layer in contact hole; and increase conductivity between polysilicon layer and source electrode and drain electrode; to reduce contact impedance, improve the assembly property of low-temperature polysilicon film transistor.
Although the present invention discloses as above with preferred embodiment; so its Bing is not used to limit the present invention; persond having ordinary knowledge in the technical field of the present invention; without departing from the spirit and scope of the present invention; when being used for a variety of modifications and variations, therefore protection scope of the present invention is when being as the criterion depending on the accompanying right person of defining.
Claims (10)
1. a manufacture method for low-temperature polysilicon film transistor, for display panels, is characterized in that, comprises the following steps:
One substrate is provided;
Form a resilient coating on the substrate;
Described resilient coating is formed an amorphous silicon layer;
Anneal to form a polysilicon layer to described amorphous silicon layer by an annealing process, and polysilicon layer described in patterning, to form an active layer on described resilient coating, wherein said active layer comprises source area, drain region and channel region, and described channel region is arranged between described source area and described drain region;
A conductive material layer is formed on described active layer and on the resilient coating exposed to the open air;
Conductive material layer described in patterning and the described conductive material layer of etch patterning, to form one first conductie buffer pad and one second conductie buffer pad on the described source area of described active layer and on described drain region respectively, described source area and described drain region is made to be formed in electrical contact with described first conductie buffer pad and described second conductie buffer pad respectively;
A gate insulator is formed on described resilient coating, on described source area, on described drain region and on described channel region;
Described gate insulator is formed a grid material layers, and grid material layers described in patterning, with the grid material layers of lithography patterning, to form a gate electrode;
Interbedded insulating layer is formed on described gate electrode and on the gate insulator exposed to the open air;
Interlayer insulating film described in patterning, and the interlayer insulating film of lithography patterning and described gate insulator, to form contact hole in described interlayer insulating film and described gate insulator, and in described contact hole, expose described first conductie buffer pad and described second conductie buffer pad to the open air;
In described contact hole, form one source pole electrode and a drain electrode, make described source electrode and described drain electrode be electrically connected described first conductie buffer pad and described second conductie buffer pad respectively.
2. the manufacture method of low-temperature polysilicon film transistor according to claim 1, it is characterized in that, the width of described first conductie buffer pad equals or is less than the width of source area, and the width of described second conductie buffer pad equals or is less than the width of drain region.
3. the manufacture method of low-temperature polysilicon film transistor according to claim 1, it is characterized in that, the contact area of described first conductie buffer pad and described source area is greater than the contact area of described source electrode and described first conductie buffer pad, and the contact area of described second conductie buffer pad and described drain region is greater than the contact area of described drain electrode and described second conductie buffer pad.
4. the manufacture method of low-temperature polysilicon film transistor according to claim 1, it is characterized in that, the thickness of described first conductie buffer pad and described second conductie buffer pad is between 2 dust to 800 dusts.
5. the manufacture method of low-temperature polysilicon film transistor according to claim 1, it is characterized in that, the material of described conductive material layer is the metal material with conductivity.
6. the manufacture method of low-temperature polysilicon film transistor according to claim 1, it is characterized in that, formed in the step of described active layer on described resilient coating, be included on described active layer and on described resilient coating and form a material layers as cover curtain, to carry out dopping process to described active layer, to form described source area and described drain region.
7. a low-temperature polysilicon film transistor, for display panels, is characterized in that, described low-temperature polysilicon film transistor comprises:
One resilient coating, is arranged on a substrate;
One active layer, being formed on described resilient coating and being made up of polysilicon material, described active layer comprises source area, drain region and channel region, and described channel region is arranged between described source area and described drain region;
One conductive material layer, comprise one first conductie buffer pad and one second conductie buffer pad, described first conductie buffer pad is arranged on the described source area of described active layer, to be electrically connected described source area, described second conductie buffer pad is arranged on the described drain region of described active layer, to be electrically connected described drain region;
One gate insulator, is formed on described resilient coating, on described source area, on described drain region and on described channel region;
Interbedded insulating layer, is formed on described gate electrode and on the gate insulator exposed to the open air;
Some contact holes, are formed in described interlayer insulating film and described gate insulator, and in described contact hole, expose described first conductie buffer pad and described second conductie buffer pad to the open air;
Some electrodes, comprise a gate electrode, one source pole electrode and a drain electrode, described gate electrode is formed on described gate insulator, described source electrode is formed in described contact hole, described source electrode is electrically connected described first conductie buffer pad, described drain electrode is formed in described contact hole, and described drain electrode is electrically connected described second conductie buffer pad.
8. low-temperature polysilicon film transistor according to claim 7, it is characterized in that, the width of described first conductie buffer pad equals or is less than the width of source area, and the width of described second conductie buffer pad equals or is greater than the width of drain region.
9. low-temperature polysilicon film transistor according to claim 7, it is characterized in that, the contact area of described first conductie buffer pad and described source area is greater than the contact area of described source electrode and described first conductie buffer pad, and the contact area of described second conductie buffer pad and described drain region is greater than the contact area of described drain electrode and described second conductie buffer pad.
10. low-temperature polysilicon film transistor according to claim 7, it is characterized in that, the thickness of described first conductie buffer pad and described second conductie buffer pad is between 2 dust to 800 dusts, and the material of wherein said first conductie buffer pad and described second conductie buffer pad is metal material or the non-metallic material with conductivity.
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| CN201510799096.7A CN105321825A (en) | 2015-11-18 | 2015-11-18 | Low temperature polycrystalline silicon thin film transistor and manufacturing method therefor |
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| CN201510799096.7A CN105321825A (en) | 2015-11-18 | 2015-11-18 | Low temperature polycrystalline silicon thin film transistor and manufacturing method therefor |
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| CN106229347A (en) * | 2016-08-24 | 2016-12-14 | 武汉华星光电技术有限公司 | A kind of low-temperature polysilicon film transistor and manufacture method thereof |
| CN108183111A (en) * | 2017-12-08 | 2018-06-19 | 友达光电股份有限公司 | Pixel array substrate |
| CN110993698A (en) * | 2019-12-18 | 2020-04-10 | 京东方科技集团股份有限公司 | Thin film transistor, preparation method thereof, array substrate and display device |
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| CN101196668A (en) * | 2006-12-07 | 2008-06-11 | 三菱电机株式会社 | Display device and method of producing the same |
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| CN106229347A (en) * | 2016-08-24 | 2016-12-14 | 武汉华星光电技术有限公司 | A kind of low-temperature polysilicon film transistor and manufacture method thereof |
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| CN110993698A (en) * | 2019-12-18 | 2020-04-10 | 京东方科技集团股份有限公司 | Thin film transistor, preparation method thereof, array substrate and display device |
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