CN100390910C - Method for increasing unit area capacitance density of metal-insulator-metal capacitor - Google Patents
Method for increasing unit area capacitance density of metal-insulator-metal capacitor Download PDFInfo
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- CN100390910C CN100390910C CNB200310122877XA CN200310122877A CN100390910C CN 100390910 C CN100390910 C CN 100390910C CN B200310122877X A CNB200310122877X A CN B200310122877XA CN 200310122877 A CN200310122877 A CN 200310122877A CN 100390910 C CN100390910 C CN 100390910C
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Abstract
The present invention discloses a manufacturing method for a stacked metal-insulator-metal capacitor, which comprises the steps: a) a bottom metal layer and a capacitor dielectric layer are orderly deposited on the bottom metal layer, and an intermediate metal layer is deposited on the dielectric layer; b) the intermediate metal layer and the capacitor dielectric layer are defined by utilizing a lithography and etching method; c) the bottom metal layer is defined by using the lithography and etching method; d) a metal interlayer dielectric material layer is deposited on the intermediate metal layer and the bottom metal layer, and the intermetallic dielectric material layer is flattened; e) in the intermetallic dielectric material layer, the etching of a plurality of dielectric layer windows is carried out by pattern etching so that the dielectric layer windows are communicated with the bottom metal layer and the intermediate layer; f) metal (tungsten) is deposited so as to form metal intraconnection in the dielectric layer windows, and the bottom metal layer and the intermediate metal layer are connected so as to carry out chemico-mechanical polishing subsequently; g) step a) to step f) are repeated; h) a top metal layer is deposited, and the top metal layer is treated by the pattern etching.
Description
Technical field
The invention relates to a kind of structure and manufacture method thereof of capacitor.More particularly, the present invention is structure and the manufacture method thereof relevant for a kind of stack multiple layer metal electric capacity.
Background technology
For a long time, increase the capacitance density of the unit are of metal-insulator-metal type (MIM) capacitor, be the target that the manufacturing engineer pursued, to meet the requirement of microminiaturization always.Finish the material of a method of this target, for example Ta for exploitation high-k (k)
2O
5To add in this MIM capacitor.Yet, the time of the integration processing procedure of deposition tool, the insulation making step of avoiding cross pollution and new material that the method need be extra and the investment on the personnel.Moreover the introducing of this high dielectric constant material has caused the problem of Leakage Current density.
As shown in Figure 1, it is the structure of one conventional metals-insulator-metal capacitor, it only has individual layer (metal 1-insulator 2-metal 3) structure, and in the intermetallic dielectric material of two metal electrode boards, the most interlayer holes 4,5,6,7,8 and 9 of etching are made for metal interconnecting and use.Its processing procedure is: deposition includes the three-decker of bottom metal layers, insulator layer and intermediate metal layer respectively, then; With the conventional lithography etching method, this intermediate metal layer of etching and insulator are made pattern, wherein also this insulating barrier of etching only partly; Then, again with the conventional lithography etching method, this bottom metal layers of etching is to make pattern; Subsequently, deposit an intermetallic dielectric material (IMD) again and carry out cmp (CMP), subsequently, in this intermetallic dielectric material, carry out a majority interlayer hole pattern etching; Then, deposition of aluminum is also made pattern, to form respectively via metal interconnecting 4,5,6,7,8 and 9 and the metal layer at top that connects of bottom metal layers and intermediate metal layer.
In this conventional metals-insulator-metal capacitor structure, because interlayer hole can take the space (being so-called big spacing processing procedure) of a lot of intermetallic dielectric materials, so can increase the capacitor resistance.Therefore, this traditional capacitor will consume bigger capacitor area, improve brilliant side's manufacturing cost.
For this reason, when characteristic is the deep-sub-micrometer specification, significantly, be necessary to develop the processing procedure of a new MIM electric capacity,, simultaneously, increase capacitance 2 to 3 progression of unit are to avoid the problems referred to above.The process apparatus that its needs are existing, and needn't increase extra development effort.Do not have the problem of cross pollution yet.
Summary of the invention
One object of the present invention is to provide a kind of manufacture method of capacitor, and it can increase the capacitance density of the per unit area of traditional capacitor.
Another object of the present invention is to utilize existing manufacturing equipment, and needn't introduce new manufacturing equipment, simultaneously, can increase capacitance density again.
A further object of the present invention can increase capacitance density for utilizing existing manufacturing equipment, avoids the cross pollution of processing procedure again.
The invention provides the manufacture method of a kind of stack type metal-insulator-metal capacitor, comprise step: a) deposit in regular turn a bottom metal layers, a capacitance dielectric layer on this bottom metal layers, an intermediate metal layer is on this dielectric layer; B) utilize legal adopted intermediate metal layer of photoetching etching and capacitance dielectric layer; C) with the legal adopted bottom metal layers of photoetching etching; D) deposit a metal interlevel dielectric material layer on this intermediate metal layer and this bottom metal layers, and this intermetallic dielectric material layer of planarization; E) in this intermetallic dielectric material layer, carry out the etching of a plurality of interlayer holes, to pass to bottom metal layers and intermediate metal layer mutually with pattern etching; F) deposition one tungsten to form metal interconnecting in interlayer hole, connects this bottom metal layers and this intermediate metal layer and carries out cmp subsequently; G) repeating step is a) to f), and, h) deposition one metal layer at top, this metal layer at top of pattern etching.
Description of drawings
Fig. 1 is the cross-section structure of conventional metals-insulator-metal capacitor;
Fig. 2 A-2F has shown the part step stage profile of stack type metal-insulator-metal capacitor of finishing according to the present invention's first preferred embodiment, and Fig. 2 F ' is another aspect of Fig. 2 F;
Stack type metal-insulator-the metal capacitor of Fig. 3 for finishing according to first embodiment of the invention;
Fig. 4 A-4D is the profile of the part step of stack type metal-insulator-metal capacitor of finishing according to second embodiment of the invention;
Another the stack type metal-insulator-metal capacitor of Fig. 5 for finishing according to second embodiment of the invention; And
Another the stack type metal-insulator-metal capacitor of Fig. 6 for finishing according to third embodiment of the invention.
Embodiment
The present invention is the manufacture method of a kind of stack type metal-insulator-metal capacitor.This manufacture method has been used the step of a deposition second insulator layer more than the manufacture method of conventional metals-insulator-metal capacitor, to form the stacked capacitor of two-layer equation, and by its metal layer at top formation metal connecting line of pattern etching, the MIM capacitor that makes this double stacked is as two capacitor parallel connections, and then increase whole capacitor device area, and improve its capacitance.
With reference to figure 2A-2F and 3, shown the part generalized section of the sequential steps of a preferred embodiment of the present invention; At first, shown in Fig. 2 A, use conventional physical vapour deposition process (PVD), for example the DC sputtering method deposits layer of aluminum metal level 10, as bottom conductive layer, and about 4000 to 8000 dusts of its deposit thickness.Certainly, also can adopt other good conductors as this conductive layer, for example, aluminium/copper alloy, copper, tungsten, chromium/platinum/billon, molybdenum/billon and titanium/platinum/billon.Then, on this bottom conductive layer, with chemical vapor deposition (CVD) or plasma activated chemical vapour deposition (PECVD) processing procedure, with TEOS/O
3As reacting gas, deposition layer of even silicon dioxide layer, as first dielectric layer 11, about 100 to 1000 dusts of its deposit thickness.Also can adopt the material of other high-ks, for example, Ta
2O
5, BST, PZT, ONO, SiON, Si
3N
4Or the like.Then, form a metal level 12 on capacitance dielectric layer 11, these metal level 12 materials for example are aluminium, tantalum, titanium or its constituent.
Then, utilize legal adopted metal level 12 of photoetching etching and capacitance dielectric layer 11 again, with, dielectric layer 11a and metal level 12a formed.So, just on capacitive region 400, form the structure of a bottom metal 10-dielectric layer 11a-intermediate metal layer 12a capacitor, shown in Fig. 2 B.
Then, shown in Fig. 2 C, with the legal adopted metal level 10 of photoetching etching.
Then, shown in Fig. 2 D, on metal level 10 and metal level 12a, with plasma CVD method, deposition layer of metal layer dielectric material 13, about 20000 to 24000 dusts of its thickness exceed the scope of metal level 10.This dielectric material 13 can be silicon dioxide.Then, polish this dielectric material 13 with cmp (CMP).Then, carry out a majority interlayer hole pattern etching in intermetallic dielectric material 13, to form most dielectric window t, v, u, x, y and z, these communicate with the intermediate metal layer 12a of first electric capacity with bottom metal layers 10 respectively, shown in Fig. 2 E.
Then, shown in Fig. 2 F, deposit with tungsten and to fill these interlayer holes,, subsequently, polish the end face of this intermetallic dielectric material 13 and intraconnections 4 '-9 ' with cmp to form intraconnections 4 ', 5 ', 6 ', 7 ', 8 ' and 9 '.
Then, repeat the step of Fig. 2 A to 2F, subsequently, as shown in Figure 3, deposition of aluminum is as metal layer at top on the gained surface, utilize the legal justice of photoetching etching to go out metal level 40 and draw metal level 30, metal level 40 act as the connecting line in capacitive region 400 and interlayer hole district 402, and in the dielectric material 13 ' that deposits for the second time, except the intraconnections 4 that as last pattern etching step, forms ", 5 ", 6 ", 7 ", 8 " and 9 ", formed in addition and drawn intraconnections 20 and 22, it is connected to subsequently draws metal level 30.
Therefore, in Fig. 3, can find out that it defines capacitive region 400, interlayer hole district 402 and draw-out area 404 respectively, and in capacitive region 400 and interlayer hole district 402, then definition there is continuous metal connecting layer 40.In capacitive region 400, electric capacity 406 and 408 have been formed.Electric capacity 406 comprises bottom metal layers 10, capacitance dielectric layer 11a and intermediate metal layer 12a, and electric capacity 408 then comprises metal layer at top 14a, capacitance dielectric layer 11a ' and intermediate metal layer 12a '.Metal level 12a ' is then in regular turn via intraconnections 6 ", 7 ", 8 " and 9 ", metal connecting layer 40, intraconnections 4 " and 5 ", metal level 14b, intraconnections 4 ', 5 ' and bottom metal layers 10 be electrically connected.Metal level 12a then see through intraconnections 6 ', 7 ', 8 ' and 9 ' and intermediate metal layer 14a be electrically connected.Draw metal level 30 see through intraconnections 20 and 22 and intermediate metal layer 14a be electrically connected.Therefore, the structure of Fig. 3 is being drawn 40 of metal level 30 and metal connecting layer as can be seen, has formed stack type metal-insulator in parallel- metal capacitor 406 and 408, and the metal-insulator-metal capacitor compared to known has increased capacitor area.
In addition,, proceed directly to the program of Fig. 2 A, promptly obtain the structure shown in Fig. 2 F ' if big spacing processing procedure also can substitute tungsten with aluminium directly in the step (Fig. 2 F) of deposition intraconnections.Wherein, intraconnections 4 '-9 ' is finished in same step with intermediate metal layer 14.Then, carry out subsequent step, with the stack type metal-insulator-metal capacitor that obtains pair of lamina.
Fig. 4 A-D has shown the part processing procedure of another embodiment of the present invention, wherein comprises the metal-insulator-metal type-insulator-metal structure of First Five-Year Plan layer.Its manufacture method is: deposition one deck hearth electrode metal level 10 earlier, as bottom electrode plate; Then, in the above, deposit an one deck dielectric material layer 11a and a target metal level 12a in regular turn respectively; Then, another dielectric material layer 11a ' of deposition and another metal level 12a ' on metal level 12a are shown in Fig. 4 A; Then, as be same as first embodiment, divide the etching of cubic graph case, metal-dielectric material layer 12a ', 11a '; 12a, 11a; And metal level 10, respectively shown in Fig. 4 B-4D; Then, as first embodiment, carry out step as Fig. 2 D to 2F, then, deposition of aluminum utilizes the legal justice of photoetching etching to go out metal level 40 and 30 as metal layer at top on the gained surface, promptly can form stack type metal-insulant-metal capacitor structure as shown in Figure 5.In this stack type metal-insulant-metal capacitor structure, once all electrodes (being hearth electrode 10, target 12a and top electrode 12a ') are formed required contact.This processing procedure only needs an extra mask layer.
Therefore, the structure of the formed Fig. 5 of embodiment has following two advantages thus: (1) is except bottom electrode, the battery lead plate of all evenly can be resistance barrier metal level, for example Ti, Ta and composition thereof, with substitution of Al, and can use proper metal or compound to strengthen the stability of the electric capacity of finishing, and, also can use SiN with further improvement capacitance density; (2) distance between hearth electrode plate and base material can not change, and when promptly representing to use for RF, does not have extra substrate effect.
Fig. 6 has shown the structure of being derived by Fig. 5.Wherein, demonstrate insulator-metal structure of three layers.If the permission of ILD thickness then can increase more " target ", its fabrication schedule can be prolonged usefulness.
The above is specific embodiments of the invention, is not in order to limit claim of the present invention.
Claims (8)
1. the manufacture method of stack type metal-insulator-metal capacitor comprises step:
A) deposit in regular turn a bottom metal layers, a capacitance dielectric layer on this bottom metal layers, an intermediate metal layer is on this dielectric layer;
B) utilize legal adopted intermediate metal layer of photoetching etching and capacitance dielectric layer;
C) with the legal adopted bottom metal layers of photoetching etching;
D) deposit a metal interlevel dielectric material layer on this intermediate metal layer and this bottom metal layers, and this intermetallic dielectric material layer of planarization;
E) in this intermetallic dielectric material layer, carry out the etching of a plurality of interlayer holes, to pass to bottom metal layers and intermediate metal layer mutually with pattern etching;
F) deposition one tungsten to form metal interconnecting in interlayer hole, connects this bottom metal layers and this intermediate metal layer and carries out cmp subsequently;
G) repeating step is a) to f); And
H) deposition one metal layer at top, this metal layer at top of pattern etching.
2. manufacture method as claimed in claim 1 is characterized in that, this intermediate metal layer is made of aluminium, tantalum, titanium or its constituent.
3. manufacture method as claimed in claim 1 is characterized in that, this bottom metal layers and metal layer at top are selected from by one of aluminium/copper alloy, copper, tungsten, chromium/platinum/billon, molybdenum/billon and group that titanium/platinum/billon constituted.
4. manufacture method as claimed in claim 1 is characterized in that, this metal interlevel dielectric material is a silicon dioxide.
5. the manufacture method of stack type metal-insulator-metal capacitor comprises step;
A) deposit in regular turn a bottom metal layers, a capacitance dielectric layer on this bottom metal layers, an intermediate metal layer is on this dielectric layer;
B) utilize legal adopted intermediate metal layer of photoetching etching and capacitance dielectric layer;
C) with the legal adopted bottom metal layers of photoetching etching;
D) deposit a metal interlevel dielectric material layer on this intermediate metal layer and this bottom metal layers, and this intermetallic dielectric material layer of planarization;
E) in this intermetallic dielectric material layer, carry out the etching of a plurality of interlayer holes, to pass to bottom metal layers and intermediate metal layer mutually with pattern etching;
F) repeating step is a) to e), and,
G) deposition one metal layer at top, this metal layer at top of pattern etching.
6. manufacture method as claimed in claim 5 is characterized in that, these intermetallic metal series of strata are made of aluminium, tantalum, titanium or its constituent.
7. manufacture method as claimed in claim 5 is characterized in that, this bottom metal layers and metal layer at top are selected from by one of aluminium/copper alloy, copper, tungsten, chromium/platinum/billon, molybdenum/billon and group that titanium/platinum/billon constituted.
8. manufacture method as claimed in claim 5 is characterized in that, this metal interlevel dielectric material is a silicon dioxide.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200310122877XA CN100390910C (en) | 2003-12-29 | 2003-12-29 | Method for increasing unit area capacitance density of metal-insulator-metal capacitor |
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|---|---|---|---|
| CNB200310122877XA CN100390910C (en) | 2003-12-29 | 2003-12-29 | Method for increasing unit area capacitance density of metal-insulator-metal capacitor |
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|---|---|
| CN1635595A CN1635595A (en) | 2005-07-06 |
| CN100390910C true CN100390910C (en) | 2008-05-28 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109979915A (en) * | 2019-03-29 | 2019-07-05 | 上海华虹宏力半导体制造有限公司 | A kind of mim capacitor structure and preparation method thereof |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102420256B (en) * | 2011-05-13 | 2013-10-09 | 上海华力微电子有限公司 | Structure for improving density of MIM (metal injection molding) capacitor and manufacturing technology thereof |
| CN102420209A (en) * | 2011-06-17 | 2012-04-18 | 上海华力微电子有限公司 | Structure and method for increasing density of capacitors |
| CN102779729B (en) * | 2012-05-04 | 2015-08-19 | 上海华力微电子有限公司 | A kind of process route forming multilayer steps structure |
| CN102683176B (en) * | 2012-05-04 | 2014-12-10 | 上海华力微电子有限公司 | Method for improving metal-insulator-metal capacitor reliability and process structure thereof |
| CN107068650A (en) * | 2016-11-25 | 2017-08-18 | 深圳天德钰电子有限公司 | Capacitor, the manufacture method of capacitor and semiconductor integrated circuit |
| US10748986B2 (en) | 2017-11-21 | 2020-08-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of semiconductor device with capacitors |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020192919A1 (en) * | 2001-04-26 | 2002-12-19 | Subhas Bothra | Structure and method to increase density of MIM capacitors in damascene process |
| US20030197215A1 (en) * | 2002-02-05 | 2003-10-23 | International Business Machines Corporation | A dual stacked metal-insulator-metal capacitor and method for making same |
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2003
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020192919A1 (en) * | 2001-04-26 | 2002-12-19 | Subhas Bothra | Structure and method to increase density of MIM capacitors in damascene process |
| US20030197215A1 (en) * | 2002-02-05 | 2003-10-23 | International Business Machines Corporation | A dual stacked metal-insulator-metal capacitor and method for making same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109979915A (en) * | 2019-03-29 | 2019-07-05 | 上海华虹宏力半导体制造有限公司 | A kind of mim capacitor structure and preparation method thereof |
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