經濟部智慈財凌局員工消費合作社印製 200409150 A7 ______ B7 五、發明説明（彳） 發明領域 本發明關於金屬-絕緣體一金屬電容器及其製造方法 ，更具體而言，在積體電路製造中，執行金屬化製程時， 在與金屬導線相同之層中製造立體型金屬一絕緣體一金屬 電容器之方法。 發明背景 電容器爲積體電路中必要元件之一，在電路中扮演電 壓調整、濾波、等功能。在半導體積體電路中，常見的電 容器型式有多晶矽-絕緣體-多晶矽電容器、金屬一絕緣 體-金屬電容器等等。其中，金屬一絕緣體一金屬電容器 具有較低的接點阻抗，故其RC値較低，常用於要求高速的 積體電路中，其也經常見於類比電路、混合電路等不同應 用中。 近年來，隨著積體電路微小化的顯著提升，在積體電 路製程中屬於後段製程之金屬化製程中的鋁導線，已逐漸 由導電係數較小的銅導線所取代，。此外，在現今的積體 電路製程中，舉例而言，在0.1 8微米以下的製程中，已廣 泛使用雙嵌刻結構，以製造多層化的半導體積體電路。所 謂的雙嵌刻結構係指金屬沈積於已經在下介電層中圖型化 的導線孔及線中，隨後，在所謂的平坦化步驟中，以諸如 化學機械硏磨法等方法，將過量的金屬移除，以拋光晶圓 表面。 在 R. Liu 等於 Proc· 2000IITC，pp. 1 1 1 - 1 1 3(2000)上發 本紙張尺度適用中國國家榡準（CNS ) A4規格（210X29?公釐） ς ---------批衣------1Τ------^ (請先閱讀背面之注意事項再填寫本頁) 200409150 A7 B7 五、發明説明（2) --券-- (請先閱讀背面之注意事項再填寫本頁) 表的 “Single Mask MetaHnsulator-Metal(MIM) Capacitor with Copper Damascene Metallization for Sub-0.18// m Mixed Mode Signal and System-on-a-Chip(SoC) Application”一文中 ，揭示配合銅製程以製造金屬-絕緣體-金屬電容器之方 法及結構。將參考圖2A及2B說明此習知技藝。圖2A中所 顯示的結構係形成有金屬導電層且經過化學機械硏磨法平 坦化後的結構，其中，代號200代表介電層，介電層中的 溝槽20 1及202均由銅塡滿，分別作爲導線及金屬-絕緣 體-金屬電容器之下電極。接著，如圖2B所示，以諸如電 漿增強化學汽相沈積法（PECVD)，在嵌刻結構表面上，再沈 積另一介電層203以作爲金屬-絕緣體-金屬電容器之介 電質，接著，在介電層上，以物理汽相沈積法（PVD)，在介 電層203上沈積諸如鋁等金屬，以作爲上電極層204，最後 ，以微影法，蝕刻移除金屬-絕緣體-金屬電容器區以外 的上電極層，而形成所需的金屬-絕緣體-金屬電容器。 經濟部智慧財產局貝工消費合作社印製 上述習知的金屬-絕緣體-金屬電容器之結構是平板 電容器的結構，其電容値/單位面積之値較低，且其製造 方法，係在完成嵌刻結構金屬化及平坦化步驟之後，再沈 積介電層及上電極層，並以一增加的光罩執行微影法，以 圖型化上電極層而取得所需的金屬-絕緣體-金屬電容器 。由於此習知技藝並非在形成嵌刻結構金屬化製程期間， 形成所需的金屬-絕緣體-金屬電容器，所以，需要繁複的 額外製程以形成金屬-絕緣體-金屬電容器，故其成本高 ，效率低。 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 經濟部智慧財產局Μ工消費合作社印製 200409150 A7 £7_ _ 五、發明説明（3) 鑑於上述習知技術之缺失，需要能夠提供成本低、效 率高之方法，以在金屬嵌刻結構之金屬化期間形成具有高 電容値/單位面積之金屬-絕緣體-金屬電容器。 發明槪述 慮及上述問題，本發明的目的係在金屬嵌刻結構金屬 化之過程中，在與導線相同的層中，形成具有高電容値/單 位面積之立體金屬-絕緣體-金屬電容器，而不需要額外 的製程步驟。 根據本發明之一態樣，提供製造立體金屬一絕緣體一 金屬電容器之方法，在擬形成金屬導線之初始嵌刻結構（ damascene structure )中製造金屬—絕緣體—金屬電容器， 初始嵌刻結構具有絕緣層及覆蓋於該絕緣層上的金屬障壁 層，絕緣層分成電容區及導線區，電容區包括至少一溝槽 ，導線區包括至少一溝槽，嵌入於電容區中的金屬障壁層 部份作爲金屬-絕緣體-金屬電容器的下電極層，方法包 括下述步驟··圖型化步驟，在，初始嵌刻結構上塗佈光阻， 以微影法將其圖型化，以致於該電容區被光阻層遮蔽，但 使導線區曝露；導線形成步驟，在光阻層遮蔽的區域之外 的區域上，形成第一金屬層並塡滿導線區中的至少一溝槽 ;移除光阻層，使電容區曝露；介電層形成步驟，在已形 成有第一金屬層的初始嵌刻結構的表面上沈積介電層，以 覆蓋第一金屬層及電容區；上電極形成步驟，在該介電層 上沈積第二金屬層，並塡滿該電容區中的至少一溝槽；及 *7 .r / j 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐) 裝 訂 線 (請先閱讀背面之注意事項再填寫本頁) 200409150 A7 B7 五、發明説明（4) •平S ft步驟，移除金屬障壁層、第一金屬層、該介電層及 該第二金屬層的不需要部份，以使表面平坦化。 才艮»本發明的另一態樣，提供高電容値/單位面積之 立體型金屬-絕緣體一金屬電容器，其形成於設有積體電 路的基底中’基底具有金屬嵌刻結構且設有至少一島狀絕 緣體’其包括：下電極金屬層，形成爲圍繞該至少一島狀 絕緣體；介電層，形成爲圍繞該下電極金屬層；及上電極 金屬層，形成爲圍繞該介電層。 此外’根據本發明，可以以電漿增強化學氣相沈積法 (PECVD)沈積厚度在200至1000埃範圍內的SiN、或 SiCh以作爲介電層。 再者’根據本發明，可以以物理氣相沈積法（PVD)沈 積厚度在200至2000埃範圍內的W、Al、Cu、或TiN以作 爲弟一金屬層。 另外，根據本發明，以化學機械硏磨法（CMP )執行平 坦化步驟。 本發明能夠在與金屬導線相同的層中形成具有高電容 値/單位面積的金屬-絕緣體-金屬電容器，而且，金屬 -絕緣體-金屬電容器之形成與金屬導線的形成共用包括 平坦化等相同的步驟。結果，本發明能夠以更少的步驟、 更低的成本、更有效率地製造具有高電容値/單位面積之 金屬-絕緣體-金屬電容器。 圖式槪述： 本紙張尺度適用中國國家標準（CNS ) A4規格l 210X297公釐） 裝-- (請先閲讀背面之注意事項再填寫本頁)Printed by the Consumer Co-operative Society of the Intellectual Property Office of the Ministry of Economic Affairs, 200409150 A7 ______ B7 V. Description of the Invention (彳) Field of the Invention The present invention relates to a metal-insulator-metal capacitor and a method for manufacturing the same. More specifically, in the manufacture of integrated circuits A method of manufacturing a three-dimensional metal-insulator-metal capacitor in the same layer as a metal wire when performing a metallization process. BACKGROUND OF THE INVENTION Capacitors are one of the necessary components in integrated circuits, and perform voltage adjustment, filtering, and other functions in the circuits. In semiconductor integrated circuits, common types of capacitors are polycrystalline silicon-insulator-polycrystalline silicon capacitors, metal-insulator-metal capacitors, and so on. Among them, metal-insulator-metal capacitors have lower contact resistance, so their RC ratio is lower. They are often used in integrated circuits that require high speed, and they are often found in different applications such as analog circuits and hybrid circuits. In recent years, with the significant improvement in the miniaturization of integrated circuits, the aluminum wires in the metallization process, which is a later stage of the integrated circuit process, have gradually been replaced by copper wires with a lower conductivity. In addition, in today's integrated circuit manufacturing processes, for example, in processes below 0.1 to 8 microns, dual-embedded structures have been widely used to fabricate multilayer semiconductor integrated circuits. The so-called double-etched structure means that metal is deposited in the wire holes and lines that have been patterned in the lower dielectric layer. Then, in a so-called planarization step, an excess of Metal is removed to polish the surface of the wafer. Published on R. Liu equals Proc · 2000IITC, pp. 1 1 1-1 1 3 (2000) This paper size is applicable to China National Standard (CNS) A4 specification (210X29? Mm) ς ------- --Batch ------ 1Τ ------ ^ (Please read the notes on the back before filling out this page) 200409150 A7 B7 V. Invention Description (2) --Voucher-- (Please read first Note on the back, please fill in this page again) In the article "Single Mask MetaHnsulator-Metal (MIM) Capacitor with Copper Damascene Metallization for Sub-0.18 // m Mixed Mode Signal and System-on-a-Chip (SoC) Application" , Reveal the method and structure of manufacturing metal-insulator-metal capacitor with copper process. This conventional technique will be explained with reference to FIGS. 2A and 2B. The structure shown in FIG. 2A is a structure after a metal conductive layer is formed and planarized by a chemical mechanical honing method. The code 200 represents a dielectric layer, and the trenches 20 1 and 202 in the dielectric layer are made of copper. Full, respectively, as the lead and the lower electrode of the metal-insulator-metal capacitor. Next, as shown in FIG. 2B, another dielectric layer 203 is deposited on the surface of the embedded structure by a method such as plasma enhanced chemical vapor deposition (PECVD) as the dielectric of the metal-insulator-metal capacitor. Next, on the dielectric layer, a physical vapor deposition method (PVD) is used to deposit a metal such as aluminum on the dielectric layer 203 as the upper electrode layer 204. Finally, the lithography method is used to remove the metal-insulator by etching. -An upper electrode layer outside the metal capacitor region to form the required metal-insulator-metal capacitor. The above-mentioned conventional metal-insulator-metal capacitor structure printed by the Shelley Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics is a flat capacitor structure, which has a low capacitance / unit area and its manufacturing method is to complete the inscription After the steps of metallizing and planarizing the structure, a dielectric layer and an upper electrode layer are deposited, and a photolithography method is performed with an added photomask to pattern the upper electrode layer to obtain the required metal-insulator-metal capacitor. Since this conventional technique does not form the required metal-insulator-metal capacitor during the metallization process of forming the embedded structure, a complicated additional process is required to form the metal-insulator-metal capacitor, so its cost is high and its efficiency is low. . This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Printed by the Intellectual Property Bureau of the Ministry of Economy, M Industrial Consumer Cooperative, 200409150 A7 £ 7_ _ V. Description of the invention (3) In view of the lack of the above-mentioned conventional technologies, There is a need for a method that can provide low cost and high efficiency to form a metal-insulator-metal capacitor with a high capacitance / unit area during the metallization of a metal-engraved structure. The description of the invention takes into account the above problems. The object of the present invention is to form a three-dimensional metal-insulator-metal capacitor with high capacitance / unit area in the same layer as the wire during the metallization of the metal embedded structure. No additional process steps are required. According to an aspect of the present invention, a method for manufacturing a three-dimensional metal-insulator-metal capacitor is provided. A metal-insulator-metal capacitor is manufactured in an initial damascene structure where a metal wire is to be formed. The initial embedded structure has an insulating layer. And a metal barrier layer covering the insulating layer, the insulating layer is divided into a capacitor region and a wire region, the capacitor region includes at least one trench, the wire region includes at least one trench, and the metal barrier layer portion embedded in the capacitor region is used as metal -Insulator-the lower electrode layer of the metal capacitor, the method includes the following steps: a patterning step, coating a photoresist on the initial etched structure, and patterning it by lithography, so that the capacitance region is The photoresist layer is shielded, but the wire area is exposed; the wire formation step is to form a first metal layer on the area outside the area shielded by the photoresist layer and fill at least one trench in the wire area; remove the photoresist layer To expose the capacitor region; a dielectric layer forming step, depositing a dielectric layer on the surface of the initial embedded structure having the first metal layer formed thereon to cover the first metal layer and Capacitor area; upper electrode forming step, depositing a second metal layer on the dielectric layer, and filling at least one trench in the capacitor area; and * 7 .r / j This paper size applies Chinese National Standard (CNS) A4 size (210 X 297 mm) gutter (please read the precautions on the back before filling this page) 200409150 A7 B7 V. Description of the invention (4) • Flat S ft step, remove the metal barrier layer and the first metal layer Unnecessary portions of the dielectric layer and the second metal layer to planarize the surface. Caigen »Another aspect of the present invention is to provide a three-dimensional metal-insulator-metal capacitor with a high capacitance / unit area, which is formed in a substrate provided with an integrated circuit. The substrate has a metal embedded structure and is provided with at least An island-shaped insulator 'includes: a lower electrode metal layer formed to surround the at least one island-shaped insulator; a dielectric layer formed to surround the lower electrode metal layer; and an upper electrode metal layer formed to surround the dielectric layer. In addition, according to the present invention, SiN or SiCh having a thickness in a range of 200 to 1000 angstroms can be deposited by a plasma enhanced chemical vapor deposition (PECVD) method as a dielectric layer. Furthermore, according to the present invention, W, Al, Cu, or TiN having a thickness in the range of 200 to 2000 angstroms can be deposited by physical vapor deposition (PVD) as a primary metal layer. In addition, according to the present invention, the flattening step is performed by a chemical mechanical honing method (CMP). The invention can form a metal-insulator-metal capacitor with a high capacitance 値 / unit area in the same layer as the metal wire, and the formation of the metal-insulator-metal capacitor shares the same steps as the formation of the metal wire, including planarization and the like. . As a result, the present invention can manufacture a metal-insulator-metal capacitor having a high capacitance 値 / unit area more efficiently with fewer steps, lower costs, and more efficiently. Schematic description: This paper size applies to Chinese National Standard (CNS) A4 size 210x297 mm. Pack-(Please read the precautions on the back before filling this page)
、1T 線 經濟部智慧財產局員工消費合作社印製 200409150 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（5) 從參考附圖之下述詳細說明中，將可以更加淸楚地瞭 解本發明的上述及其它目的與優點，其中： 圖1A-1G係用於說明根據本發明的實施例’其中圖1A 係立體視圖，用以顯示開始製造金屬-絕緣體一金屬電容 器的初始嵌刻結構的立體結構，圖1 B -1F係剖面視圖’用 以說明根據本發明的實施例之金屬-絕緣體-金屬電容器 的製造步驟，圖1G係上視圖，顯示根據本發明的實施例製 成之形成有金屬導線及金屬-絕緣體-金屬電容器之結構 ;及 圖2A-2B係剖面視圖，用以說明習知的金屬-絕緣體 -金屬電容器之結構及製造方法。 主要元件對照表 100 金屬嵌刻結構 101 基底 102 金屬層 103 立體柱狀物 104 光阻層 105 銅栓塞及/或導線 106 介電層 107 上金屬層 108 電容器 109 金屬導線 200 介電層 ---------參！ (請先閱讀背面之注意事項再填寫本頁〕 -訂 線 Φ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） —9- 200409150 A7 B7 五、發明説明（6) 201 溝槽 202 溝槽 203 介電層 204 上電極層 較佳實施例詳述 將於下參考附圖，說明根據本發明的實施例，其用以 製造金屬-絕緣體-金屬電容器。應瞭解下述說明僅作爲 舉例說明之用，並非用以限定本發明。此外，爲了提供更 淸楚的說明，圖示並未依比例繪製。 下述說明之根據本發明的實施例的製程步驟及對應結 構，並未涵蓋製造完整的ic電路的完整製程，而是可以配 合半導體技術領域中不同的IC電路中的其它製程而製造所 需的完整1C電路。 首先，參考圖1A，其係立體視圖，顯示根據本實施例 要形成金屬導線及金屬-絕緣體-金屬電容器的初始嵌刻 結構1 00。如圖1 A所示，在可作爲層間金屬介電質之基底 101中形成有多個溝槽，舉例而言，六個溝槽，且其表面上 形成有金屬層1 02。在如此形成的初始嵌刻結構1 〇〇中，左 右二側中的個別溝槽用於在後續步驟中塡入諸如銅等金屬 ，以作爲導線（下述說明中將稱爲導線區），而在圖丨A的 中間部份具有多個溝槽及多列排列整齊的立體柱狀物1 〇3 ( 在下述說明中，稱爲電容器）。 圖1 B係剖面視圖，對應於圖1 A之立體視圖。在下述 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 裝-- (請先閲讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs on the 1T line. 200409150 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention. Understand the above and other objects and advantages of the present invention, in which: FIGS. 1A-1G are used to illustrate the embodiment according to the present invention, wherein FIG. 1A is a three-dimensional view showing the initial inscription of metal-insulator-metal capacitor manufacturing. The three-dimensional structure of the structure, FIG. 1B-1F is a cross-sectional view 'for explaining the manufacturing steps of the metal-insulator-metal capacitor according to the embodiment of the present invention, and FIG. 1G is a top view showing the structure made according to the embodiment of the present invention A structure with a metal wire and a metal-insulator-metal capacitor is formed; and FIGS. 2A-2B are sectional views for explaining the structure and manufacturing method of a conventional metal-insulator-metal capacitor. Comparison table of main components 100 Metal embedded structure 101 Base 102 Metal layer 103 Three-dimensional pillar 104 Photoresist layer 105 Copper plug and / or wire 106 Dielectric layer 107 Upper metal layer 108 Capacitor 109 Metal wire 200 Dielectric layer --- ------ Come! (Please read the precautions on the back before filling this page]-Threading Φ This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) — 9- 200409150 A7 B7 V. Description of Invention (6) 201 Groove 202 Trench 203 Dielectric layer 204 Upper electrode layer The preferred embodiment will be described in detail below with reference to the accompanying drawings to explain an embodiment of the present invention for manufacturing a metal-insulator-metal capacitor. It should be understood that the following description is only for The purpose of illustration is not to limit the present invention. In addition, in order to provide a better explanation, the diagram is not drawn to scale. The process steps and corresponding structures according to the embodiments of the present invention described below are not covered. A complete process for manufacturing a complete IC circuit, but a complete 1C circuit that can be manufactured in conjunction with other processes in different IC circuits in the field of semiconductor technology. First, referring to FIG. 1A, it is a perspective view showing an embodiment according to this embodiment. To form an initial embedded structure of metal wires and metal-insulator-metal capacitors 100, as shown in FIG. 1A, it is shaped in a substrate 101 that can be used as an interlayer metal dielectric. A plurality of grooves are formed, for example, six grooves, and a metal layer 102 is formed on the surface thereof. In the thus-formed initial etched structure 100, individual grooves on the left and right sides are used for In the subsequent steps, metal such as copper is inserted as a wire (the following description will be referred to as the wire area), and in the middle part of Figure A, there are multiple grooves and multiple columns of neatly arranged three-dimensional pillars. 1 〇3 (referred to as the capacitor in the following description). Figure 1 B is a cross-sectional view corresponding to the perspective view of Figure 1 A. In the following paper sizes, the Chinese National Standard (CNS) A4 specification (210X297 mm) is used. -(Please read the notes on the back before filling this page)
、1T 線 經濟部智慈財產局Μ工消費合作社印製'' -10- 200409150 經濟部智慧財產局員工消費合作社印製 A7 _______B7__五、發明説明（7) 說明中，爲了便於說明及瞭解，將以剖面視圖說明根據本 實施例之金屬-絕緣體-金屬電容器之製造步驟。 此處’將說明金屬嵌刻結構100的形成。舉例而言， 使用電漿增強化學汽相沈積法（PECDV)以沈積SiN層作爲基 底101。接著’以微影法（ph otolith og rap hy)，將基底101圖 型化及蝕刻成如圖1 B所示之具有多個溝槽的結構。然後， 舉例而言’以物理汽相沈積法（PVD)，在基底101上沈積厚 度在100至800埃範圍內的銅層以作爲金屬層1〇2。基底 101可作爲後續形成的金屬層102之障壁層，而金屬層102 係作爲金屬-絕緣體-金屬電容器之底部電極層，且在後 續要形成導線時作爲種子層以方便金屬導線的形成。舉例 而言，在銅製程中，基底101包括SiN、SiCh，金屬層102 之材質爲銅。 接著，在此金屬嵌刻結構上形成光阻層104並接著將 其圖型化，如圖1C所示，在完成圖型化之後，僅有要形成 導線區的光阻會被移除，而留下遮蓋電容區的光阻層1 〇4。 然後，如同圖1D所示，以電鍍法，將銅鍍著於未經光 阻遮蓋的區域並塡滿導線區中的溝槽而形成銅栓塞及/或導 線 105 〇 之後，移除光阻層104，使電容區曝露。然後，如圖 1E所示，在整個結構上沈積一層介電層1〇6以作爲金屬一 絕緣體-金屬電容器之絕緣體。關於介電層106，舉例而言 ，可以以PECVD方法沈積厚度在200- 1000A之氮化矽（SiN) 或二氧化矽（Si〇〇。在形成介電層106之後，接著，在其上 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公" — -11 - (讀先閱讀背面之注意事項再填寫本頁) 裝· 訂 線 囑 200409150 A7 B7 五、發明説明（8) 沈|貝上金屬層107以作爲金屬一絕緣體一金屬電容器之上 電極。此上金屬層107會經由導線孔（via)(未顯示於圖中）而 連接至往後可能形成的上層金屬層。關於上金屬層1 〇7，舉 例而§ ’可以以CVD或PVD方法，沈積厚度200-2〇〇〇A之 W、Al、Cu、TiN 等等。 接著’以半導體技術中所習知的化學機械硏磨法，移 除不需要的邰份金屬層1 0 2、銅栓塞及/或導線1 q 5、介電層 106、及上金屬層107，以使表面平坦化。結果，如圖π所 不’同時完成了諸如銅的金屬導線及金屬一絕緣體一金屬 電容器之製造。圖1 G係對應於圖1F之上視圖，淸楚地顯 示電容器區中形成的電容器10 8，及形成於二邊的金屬導線 109 ° 如圖1 G所示，根據本發明的實施例之金屬一絕緣體一 金屬電谷益108之構造是由作爲下電極之圍繞島狀基底1Q1 的金屬層102、作爲介電質之圍繞金屬層102的介電層106 、及作爲上電極之上金屬層107所構成。 從上述實施例說明可知，根據本發明所形成的立體電 容器的電容値/單位面積顯著地增加。此外，根據本發明 ，金屬-絕緣體-金屬電容器與諸如銅之金屬導線形成在 同一層上，在製造時，它們共用諸如圖型化及平坦化等多 個步驟，因此，可以顯著地減少繁複的製程步驟並因而大 幅地降低製造成本。 在上述說明中，以舉例方式說明本發明，但是本發明 並不限於上述之詳細說明，習於此技藝者在暸解上述說明 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 批衣-- (請先閱讀背面之注意事項再填寫本頁) -訂 線 經濟部智慧財產局員工消費合作社印製 200409150 A7 B7 五、發明説明（9) 之後，在不悖離本發明的精神及範圍下，執行不同的變化 及修改。應暸解本發明之範圍係由後述之申請專利範圍所 定 界 #f ----------裝------訂------線--- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慈財產局肖工消費合作社印製 本紙張尺度適用中國國家標準⑽）Μ規格（训X29刪 一Printed on the 1T line by the Consumer Goods Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -10- 200409150 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _______B7__ V. Description of the Invention (7) In the description, for ease of explanation and understanding, The manufacturing steps of the metal-insulator-metal capacitor according to this embodiment will be explained in a sectional view. Here, the formation of the metal engraved structure 100 will be explained. For example, plasma enhanced chemical vapor deposition (PECDV) is used to deposit a SiN layer as the substrate 101. Then, the substrate 101 is patterned and etched into a structure having a plurality of trenches as shown in FIG. 1B by photolithography (ph otolith og rap hy). Then, for example, as a metal layer 102, a copper layer having a thickness in a range of 100 to 800 angstroms is deposited on the substrate 101 by physical vapor deposition (PVD). The substrate 101 can be used as a barrier layer of the metal layer 102 to be formed later, and the metal layer 102 is used as a bottom electrode layer of the metal-insulator-metal capacitor, and is used as a seed layer to facilitate the formation of the metal wires in the subsequent formation of the wires. For example, in the copper process, the substrate 101 includes SiN and SiCh, and the material of the metal layer 102 is copper. Next, a photoresist layer 104 is formed on the metal embedded structure and then patterned, as shown in FIG. 1C. After the patterning is completed, only the photoresist to be formed in the wire region is removed, and A photoresist layer 104 covering the capacitor region is left. Then, as shown in FIG. 1D, copper is plated on the area not covered by the photoresist and fills the trench in the lead area by electroplating to form a copper plug and / or the lead 105. Then, the photoresist layer is removed. 104. The capacitor area is exposed. Then, as shown in FIG. 1E, a dielectric layer 106 is deposited on the entire structure as a metal-insulator-metal capacitor insulator. Regarding the dielectric layer 106, for example, a silicon nitride (SiN) or a silicon dioxide (SiOO) having a thickness of 200-1000A can be deposited by a PECVD method. After the dielectric layer 106 is formed, then, a dielectric layer 106 is formed thereon. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 male " — -11-(Read the precautions on the back before filling in this page) Binding and ordering orders 200409150 A7 B7 V. Description of the invention (8) Shen | The upper metal layer 107 is used as a metal-insulator-metal capacitor upper electrode. The upper metal layer 107 is connected to a possible upper metal layer through a via (not shown). About the upper layer Metal layer 107, for example, and § 'W, Al, Cu, TiN, etc. can be deposited with a thickness of 200-20000A by CVD or PVD method. Then,' Chemical machinery known in semiconductor technology ' Grinding method removes unwanted metal layers 102, copper plugs and / or wires 1q5, dielectric layer 106, and upper metal layer 107 to flatten the surface. As a result, as shown in Figure π, 'Simultaneously completed metal wires such as copper and metal-insulator-metal The manufacture of capacitors. Figure 1 G corresponds to the top view of Figure 1F, showing clearly the capacitor 10 8 formed in the capacitor area, and the metal wires 109 formed on both sides. As shown in Figure 1 G, according to the invention The structure of the metal-insulator-metal valley Y 108 in the embodiment is a metal layer 102 surrounding the island-shaped substrate 1Q1 as a lower electrode, a dielectric layer 106 surrounding the metal layer 102 as a dielectric, and a metal layer 102 as an upper electrode. The upper metal layer 107 is formed. As can be seen from the description of the above embodiments, the capacitance / unit area of the three-dimensional capacitor formed according to the present invention is significantly increased. In addition, according to the present invention, a metal-insulator-metal capacitor and a metal wire such as copper Formed on the same layer, they share multiple steps such as patterning and planarization at the time of manufacturing, so it can significantly reduce tedious process steps and thus greatly reduce manufacturing costs. In the above description, examples are given by way of example. Illustrate the present invention, but the present invention is not limited to the above detailed description. Those skilled in the art will understand the above description. (CNS) A4 size (210X297 mm) Approved clothing-(Please read the precautions on the back before filling out this page)-Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Consumption Cooperative, 200409150 A7 B7 V. Invention Description (9) After that, different changes and modifications are performed without departing from the spirit and scope of the present invention. It should be understood that the scope of the present invention is delimited by the scope of the patent application described below #f ---------- 装- ----- Order ------ Line --- (Please read the notes on the back before filling this page) Printed by Xiao Gong Consumer Cooperative, Intellectual Property Bureau of the Ministry of Economic Affairs, this paper is printed in accordance with Chinese national standards⑽) Μ specifications (training X29 delete one