CN100388417C - 半导体器件的生产管理方法及半导体衬底 - Google Patents

半导体器件的生产管理方法及半导体衬底 Download PDF

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CN100388417C
CN100388417C CNB2005101137623A CN200510113762A CN100388417C CN 100388417 C CN100388417 C CN 100388417C CN B2005101137623 A CNB2005101137623 A CN B2005101137623A CN 200510113762 A CN200510113762 A CN 200510113762A CN 100388417 C CN100388417 C CN 100388417C
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production management
wafer
semiconductor device
management method
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CN1841649A (zh
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米田义之
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Fujitsu Semiconductor Ltd
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Fujitsu Ltd
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Abstract

本发明提供一种半导体器件的生产管理方法及半导体衬底。该方法包括如下步骤：在已形成多个半导体器件的半导体衬底上设置至少一个标签区域，该标签区域设置有能够在不进行物理接触的条件下读出/写入信息的标签；在不与半导体衬底接触的条件下，将每个半导体器件的生产管理信息写入标签中；以及在划分半导体衬底之后从标签中读出生产管理信息，并基于生产管理信息选取无缺陷的半导体器件。

Description

半导体器件的生产管理方法及半导体衬底
技术领域
本发明涉及一种半导体器件的生产管理方法及一种半导体衬底，并且这种半导体器件的生产管理方法及半导体衬底适于生产晶片级封装。
背景技术
在使用铜重新配线(re-route)进行晶片级CSP(芯片尺寸封装)处理时，通常即使在晶片处理完成之后芯片也不会成为单独的个体，它们会进入封装步骤(晶片级封装步骤)。在封装步骤之间，通过以晶片为单位对晶片进行外观检查。
在进行这种外观检查时，基于晶片有效器件布局(1ayout)生成纸上的分布图(map)，并且检查者将内部和外部封装步骤的检查结果(模式等)以及它们的位置写到纸上的分布图上。另一种选择是采用自动外观检查机以将检查结果(模式等)和它们的位置转换成电子数据。这些数据作为检查分布图数据被添加到生产的产品，并且持续添加新的检查数据，或者收集并迭加失效数据作为电子数据。
此外，由于以晶片为单位对晶片进行这种晶片级CSP处理直到晶片被划成单个芯片为止，因此这种晶片级CSP处理能够以晶片为单位对晶片进行检查。作为这种晶片级检查的结果，能够获得晶片上无缺陷芯片的位置，并且测试装置(tester)能够输出作为电子数据的无缺陷芯片分布图。
将从测试装置输出的无缺陷芯片分布图与上述检查结果迭加，而生成最终的无缺陷芯片分布图。基于最终的无缺陷芯片分布图，可在划片之后挑选出无缺陷芯片。
为了选取无缺陷芯片，应该预先将无缺陷芯片分布图和晶片相互关联。因此，每个晶片被提供一个唯一的识别标志(晶片ID)，并且此晶片ID用于对照纸上的分布图或电子数据。晶片ID通常被印在晶片的电路面上。近来在专利文献#1、#2中也提出了IC标签。
在晶片级封装步骤中，由于在电路面上形成绝缘树脂和布线金属层，因此难以识别这种IC标签。在这种情况下，也可以将晶片ID写在背面上。
[专利文献#1]日本特开平2004-179234
[专利文献#2]日本特开平2004-157765
[本发明将要解决的问题]
在现有技术的生产方法中，一个晶片仅设置一个识别该晶片的晶片ID或者IC标签。通过检查而检测到的每个半导体器件的缺陷数据、批号、工序单等(下文称为“生产管理信息”)不写在晶片上，而是分别进行记录。
因此，为了在最后的步骤选出无缺陷器件，应该对照晶片ID标志和包括生产管理信息的无缺陷器件分布图。但是，难以对每个晶片进行这种对照处理，并且在无缺陷器件分布图与每个半导体器件之间进行比较是一项繁重的工作。因此，现有技术的生产管理方法存在的问题是管理复杂且繁重，并且易于发生识别错误。
发明内容
本发明的总的目的为提供一种半导体器件的生产管理方法以及使用这种生产管理方法的半导体衬底，该生产管理方法能够容易地获得高准确度的生产管理。
在下面的说明中将阐明本发明的特点和优点，并且一部分特点和优点从说明书和附图中可显而易见，或者根据说明书中提供的教导通过实施本发明可认识到。本发明的目的以及其他的特点和优点可通过在说明书中特别指出的生产管理方法以使本领域的普通技术人员能够实施本发明的这种充分、清楚、简明及严格的方式来实现和获得。
为了获得这些及其他优点，并根据本发明的目的，如在此实施及广义描述的，本发明具体如下。
本发明提供一种半导体器件的生产管理方法，包括如下步骤：
在形成多个半导体器件的半导体衬底上设置至少一个标签区域，该标签区域设置有一个能够在不进行物理接触的条件下读出以及写入信息的标签；
在不与该半导体衬底接触的条件下，将每个半导体器件的生产管理信息写入该标签中；以及
在划分该半导体衬底之后从该标签中读出该生产管理信息，并基于该生产管理信息选取无缺陷的半导体器件。
根据本发明的另一个方案，提供一种半导体衬底，该半导体衬底包括：衬底；多个半导体器件，形成在所述衬底上；以及一个标签区域，形成在所述衬底上，以非接触方式进行信息的读取以及写入。
附图说明
图1为具有标签区域的晶片的俯视平面图；
图2为说明根据本发明实施例的生产管理方法的流程图；
图3为根据本发明的第一实施例具有标签区域的晶片级CSP处理的横截面图；
图4为根据本发明的第二实施例具有标签区域的晶片级CSP处理的横截面图；
图5A为根据本发明的第三实施例具有标签区域的晶片级CSP处理的横截面图；
图5B为本发明第三实施例的天线部分的示意图；
图6A为根据本发明的第四实施例具有标签区域的晶片级CSP处理的横截面图；
图6B为本发明第四实施例的天线部分的示意图；以及
图7为说明本发明第四实施例的晶片级CSP生产方法的流程图。
具体实施方式
下面，参照附图描述本发明的实施例。
图1至3说明根据本发明第一实施例的半导体器件的生产管理方法。图1示出刚刚完成晶片处理之后的晶片10。图2为说明采用根据本发明该实施例的半导体器件生产管理方法的晶片级CSP(半导体器件)生产方法的流程图。图3示出通过根据本发明该实施例的半导体器件生产管理方法所生产的晶片级CSP的实例。参照图1至图3所示的晶片级CSP(半导体器件)生产管理方法来说明该实施例。
图1示出刚刚完成图2中的步骤S10所示的晶片处理之后的晶片10。在晶片10上，通过晶片处理形成许多半导体器件11。
在形成半导体器件11的晶片10的表面上，设置了标签区域12A。在标签区域上，形成至少一个标签(射频识别)。在不与标签进行物理接触的条件下，能够将信息写入标签和/或从标签读出信息。图1仅示出了一个标签。该标签区域12A形成在晶片10上的适当位置，以使标签不会干扰半导体器件11。因此，晶片10上的标签区域12A对形成半导体器件11的区域没有不利的影响。
在本实施例中，在晶片处理中的步骤S10，标签与半导体器件11一起形成。标签设置有天线13A，该天线13A用于通过电磁感应或电磁波通信从外部无线读出信息和/或将信息无线写到外部。在本实施例中，在晶片处理中的步骤S10，天线13A也与半导体器件11一起形成。因此，不需要专门形成天线13A的附加步骤，并且简化了生产半导体晶片的工艺。
对图1所示的晶片10进行图2中的步骤S10-S34示出的晶片级封装工艺(在晶片条件下完成所有封装工艺的处理)，以形成图3所示的晶片级CSP。
在图3所示的晶片级CSP的晶片10上，形成多个晶片器件11。为了简明起见，图3仅示出两个晶片器件11。
通过在步骤S10在由硅制成的晶片10的上表面上进行上述晶片处理，形成多个晶片器件11。在步骤S10的晶片处理期间，天线13A也形成在晶片10上的标签区域12A中。在晶片10的上表面上，形成绝缘树脂层14、17，铜重新配线15以及焊料凸起16。
在其中已经形成半导体器件11和天线13A的晶片10的上表面上形成绝缘树脂层14。
在绝缘树脂层14的预定位置处开设多个孔，以与形成在晶片10上的多个电极电连接。该绝缘树脂层14覆盖标签区域12A中的天线13A的上表面。
在绝缘树脂层14上，形成铜重新配线15。通过在绝缘树脂层14中开设的孔，铜重新配线15与形成于晶片10上的电极电连接。在铜重新配线15上，形成绝缘树脂层17。
在该绝缘树脂层17中相应于铜重新配线15的预定位置形成孔。在这些孔中设置焊料凸起16。以这种方式，在半导体器件11的生产工艺期间形成晶片级CSP。
如上所述在标签区域12A中形成标签，该标签为一个存储器件，通过天线13A能够将信息从该存储器件无线读出到外部，以及将信息从外部无线写入该存储器件。
接着，参照图2，下面说明根据本发明该实施例的晶片级CSP的生产工艺及其管理方法。
在半导体生产工艺中，图2所示的步骤S 10的晶片处理被称为预处理。通过进行该晶片处理，在晶片10上形成半导体器件11和标签区域12A(包括天线13A)。在该晶片处理中，可能发生处理失败，这会引起晶片级CSP失效或者缺陷。在现有技术中，处理失败信息被写在无缺陷器件分布图中。
另一方面，在本发明的实施例中，晶片10设置有包含标签(未示出)的标签区域12A，并且通过完成该晶片处理，进一步形成天线13A，因此，能够将这种处理失败立即写在标签中。根据本实施例，在完成晶片处理时，处理失败作为生产管理信息项目21之一被写在标签中。
这种写处理是通过在用于晶片处理的生产装置或者检查装置中设置的传输装置来进行。如果该传输装置位于生产装置中，则优选将该传输装置设置在用于最后处理的生产装置中。传输装置可以设置在承载晶片10的操作装置中。
在随后的探针测试步骤(步骤S12)中，将连接到测试装置的探针与形成于晶片10上的电极相接触，以进行电测试。电测试结果作为生产管理信息项目21之一被写入标签。
在用以在晶片10上形成绝缘树脂层14的绝缘层形成步骤(步骤S14)中，在晶片10上涂覆树脂材料，并对该树脂材料进行曝光、显影及检查，以形成绝缘层14。在该绝缘层形成步骤中，外观检查结果和层厚作为生产管理信息21被写入标签。
步骤S16至S26为用于形成铜重新配线15的步骤。在这些步骤中的溅射层形成步骤(步骤S16)中，通过溅射形成籽晶层(Ti/Cu或Cr/Cu)，该籽晶层具有供电层和紧密接触层的作用，用以电镀铜重新配线15。在溅射层形成步骤中，籽晶电阻和籽晶层的厚度，以及所使用的机器的序列号作为生产管理信息21被写在标签中。
在重新配线电镀步骤(步骤S20)中，采用步骤S16中形成的籽晶层作为一个电极，从电镀装置供电，以进行电解铜电镀，从而形成铜重新配线15。在该重新配线电镀步骤中，电镀条件等作为生产管理信息被写在标签中。
在该重新配线电镀步骤中，通过从标签中读出生产管理信息21并读出机器加工方法(machine recipe)例如每个晶片的电镀条件或者蚀刻条件等，可以防止操作错误。
在蚀刻步骤(步骤S24)中，在溅射步骤中形成的籽晶层被蚀刻，并且电连接的重新配线被籽晶层分离，从而完成重新配线。在此蚀刻步骤中，蚀刻条件和测试结果，例如该蚀刻步骤之后形成的布线的厚度，作为生产管理信息21被写在标签中。
在以上述方式形成铜重新配线15之后，对铜重新配线15或绝缘层14进行外观检查(步骤S26)。该外观检查的结果也作为生产管理信息21而被写在标签中。重新配线或者绝缘层中的失效或者缺陷能被人眼检查出来或者被自动外观检查装置检测出来；这些失效可用来制作电子分布图(electromap)。
步骤30和步骤32是用以形成焊料凸起16的步骤。在通过公知方法形成焊料凸起16(步骤S30)之后，进行外观检查步骤(步骤S32)，以检查形成的焊料凸起是否具有预定的形状。在此步骤中检查凸起的大小和形状。焊料凸起的外观检查结果或者尺寸异常性结果用以形成电子分布图，并作为生产管理信息被写在标签中。
通过进行上述步骤S10-S32，在晶片10上形成晶片级CSP。在接下来的步骤S34中，对在晶片10上形成的晶片级CSP进行晶片级最终测试(FT)。最终测试的测试结果也与失效确定结果和缺陷类别一起作为生产管理信息21而被写在标签中。
在完成上述步骤S10-S34以及在晶片10上形成多个CSP(半导体器件)之后，进行划片步骤(步骤S36)，以使晶片10独立成为多个单独的CSP。此划片步骤通过将晶片粘贴在划片带上并用划片刀切割晶片来进行。在划片完成之后，CSP便成为单独的个体，但其仍然粘贴在划片带上。
接下来，例如通过将划片带暴露于紫外光使划片带的粘着剂的粘着力减弱，并且通过挑选装置选出各单独的CSP(步骤S38)。挑选装置具有读出装置，该读出装置读出写在标签区域12A中的标签中的生产管理信息21。因此，基于写在标签中的生产管理信息21，挑选装置仅选出无缺陷的CSP。
如上所述，在根据本发明的实施例的生产管理系统中，由于生产管理信息21(所谓的无缺陷半导体分布图)被写在形成于晶片10上的标签中，从而晶片10在保存生产管理信息21的同时，进行每个步骤(步骤S12-S38)。如果每个步骤具有用以读出和写入标签信息的装置，则先前步骤的生产管理信息21能被每个后续步骤中的装置读出来，并且能被用于每个后续步骤中的处理和测试。也就是说，每个装置能提供其用于后面的步骤的生产管理信息。
在现有技术的方法中对晶片检查与晶片分离地形成的分布图来选择无缺陷器件，与之相比，在本发明的该实施例中，由于形成于晶片10上的CSP的生产管理信息21(包括半导体器件11的信息)被写在标签中，从而简化了无缺陷器件的选取并提高了其准确性。此外，在划片步骤(S36)之后，可以保持单独化的标签区域12A。在这种情况下，能够保留晶片10的历史记录(history)，这对于查寻(tracing)是有效的。
接下来，参照图4至7，下面说明能够应用本发明的晶片级CSP工艺的另一个实施例。下面说明形成于标签区域中的天线的另一个实施例。在图4至7中，与图1至3中相同或相似的元件或部分被分配相同的参考标号，并省略它们的说明。
在图4所示的晶片级CSP工艺中，在铜重新配线15上形成金属柱18。然后经由阻挡金属19在金属柱18上形成焊料凸起16。形成铸模树脂层20以覆盖金属柱18。
在这种结构中，金属柱18提供应力释放效果。铸模树脂层20支撑金属柱18，从而在CSP安装中不需要进行下填(under fill)树脂。本实施例中的标签区域12A与图3所示的标签区域相同，并包括在晶片处理中形成的一个标签和一个天线13A(步骤S10，参见图2)。
图5所示的晶片级CSP工艺类似于图3所示的晶片级CSP工艺，但其特点在于在铜重新配线形成步骤(S16-S26)期间天线13B与铜重新配线15一起形成。与第一实施例相同，在晶片处理(步骤S10，参见图2)中形成标签。
天线13B形成在标签区域12B中。通过经由形成于绝缘树脂14中的孔将形成于天线13B边缘处的接合部分13a与标签电极(未示出)相连接，来实现标签与天线13B之间的电连接。
根据这种结构，由于在晶片处理中形成标签(步骤S10)，并且天线13B与铜重新配线15一起形成，因此不需要进行专门用于形成标签12B的特殊步骤，从而简化了生产工艺。
在上述实施例中，在晶片处理过程中(步骤S10)标签与晶片10一体形成。
另一方面，图6所示的晶片级CSP工艺的特点在于一个标签包括一个IC标签22，该IC标签22为芯片部件。
在形成铜重新配线15的步骤期间，天线13C形成在绝缘树脂层14的上表面上。在形成天线13C的同时，形成与标签区域12C连接的接合部分13a，以及形成上面安装有IC标签22的虚设焊盘23，如图6B所示。
图7为说明晶片级CSP生产方法的流程图。在图7中，与图2所示相同的步骤被分配相同的步骤标号，并省略它们的说明。
在生产方法的本实施例中，在完成用以形成铜重新配线15的工艺(步骤S16-S26)之后，通过进行抗蚀层处理步骤(步骤S23-1)和铜柱电镀步骤(步骤S23-2)来形成金属柱18。此时，在形成铜重新配线15的步骤中(步骤S16-S26)中，天线13C和虚设焊盘23一起形成。
在本实施例中，在完成布线测试步骤(S26)之后，在步骤S27-1中安装IC标签22。通过使用安装型IC标签22以及将其倒装接合于天线13C的接合部分和虚设焊盘23来实现此安装步骤。在接下来的步骤S27-2中，铸模树脂层20形成在已经安装有IC标签22的晶片上，并且IC标签22被牢固地固定在晶片10上。
在生产方法的实施例中，通用的部件可用作IC标签22，并且不一定要在晶片处理(步骤S10)中形成标签；因此，能够减少晶片处理中步骤的数目(工作量)。
与使用分离的分布图的现有技术相比，根据上述实施例，能够以高准确度容易地挑选出无缺陷的半导体芯片。
此外，本发明不限于这些实施例，在不脱离本发明范围的条件下，可以进行变化和修改。
本发明基于2005年3月31日提交给日本专利局的日本优先权申请No.2005-105228，在此通过参考援引其全部内容。

Claims (11)

1.一种多个半导体器件的生产管理方法，包括如下步骤：
在形成半导体器件的半导体衬底上设置至少一个标签区域，该标签区域设置有一个能够无接触地读出以及写入信息的标签；
在不与该半导体衬底接触的条件下，将每个半导体器件的生产管理信息写入该标签中；以及
在划分该半导体衬底之后从该标签中读出该生产管理信息，并基于该生产管理信息选取无缺陷的半导体器件。
2.如权利要求1所述的生产管理方法，其中在所述半导体器件的生产工艺中使用的所有或部分生产装置设置有能够无接触地从该标签读出信息的读出装置以及将信息写入该标签的写入装置。
3.如权利要求1所述的生产管理方法，其中该生产管理信息包括所述半导体器件的检查信息。
4.如权利要求1所述的生产管理方法，其中通过晶片级封装步骤在该半导体衬底上形成半导体器件、重新配线以及焊料电极。
5.如权利要求1所述的生产管理方法，其中该标签区域形成于使该标签区域不会妨碍该半导体衬底上的半导体器件的位置处。
6.如权利要求1所述的生产管理方法，其中该标签区域包括存储元件，并且在所述半导体器件的生产步骤中形成该存储元件。
7.如权利要求1所述的生产管理方法，其中该标签区域包括与该标签连接的天线。
8.如权利要求7所述的生产管理方法，其中在所述半导体器件的生产步骤或者形成重新配线的步骤中形成该天线。
9.如权利要求7所述的生产管理方法，其中该标签为安装在该天线上的标签芯片。
10.一种半导体衬底，其包括：
衬底；
多个半导体器件，形成在所述衬底上；以及
一个标签区域，形成在所述衬底上，以非接触方式进行信息的读取以及写入。
11.如权利要求10所述的半导体衬底，其中所述标签区域与所述衬底一体形成。
CNB2005101137623A 2005-03-31 2005-10-14 半导体器件的生产管理方法及半导体衬底 Expired - Fee Related CN100388417C (zh)

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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100713121B1 (ko) * 2005-09-27 2007-05-02 한국전자통신연구원 칩과 이를 이용한 칩 스택 및 그 제조방법
US8098134B2 (en) 2006-06-21 2012-01-17 Neology, Inc. Systems and methods for interrogator multiple radio frequency identification enabled documents
JP5033447B2 (ja) * 2007-03-08 2012-09-26 富士通株式会社 Ｒｆｉｄシステム及びｒｆｉｄタグ
WO2009034496A2 (en) * 2007-09-12 2009-03-19 Nxp B.V. Wafer, method of manufacturing integrated circuits on a wafer, and method of storing data about said circuits
JP2011098809A (ja) * 2009-11-05 2011-05-19 Nikon Corp 基板カートリッジ、基板処理装置、基板処理システム、基板処理方法、制御装置及び表示素子の製造方法
TWI538861B (zh) * 2009-11-05 2016-06-21 尼康股份有限公司 A substrate processing system, and a circuit manufacturing method
JP2011098808A (ja) * 2009-11-05 2011-05-19 Nikon Corp 基板カートリッジ、基板処理装置、基板処理システム、基板処理方法、制御装置及び表示素子の製造方法
FR2973563A1 (fr) * 2011-04-01 2012-10-05 St Microelectronics Rousset Memorisation de donnees sur une plaquette de circuits electroniques
JP2015021805A (ja) * 2013-07-18 2015-02-02 株式会社日立ハイテクノロジーズ レプリカ採取装置およびそれを備えた検査システム
US10163828B2 (en) * 2013-11-18 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and fabricating method thereof
JP6377936B2 (ja) * 2014-04-01 2018-08-22 エイブリック株式会社 半導体ウェハ
JP5743005B2 (ja) * 2014-05-12 2015-07-01 株式会社ニコン 表示素子の製造方法
US10685918B2 (en) * 2018-08-28 2020-06-16 Semiconductor Components Industries, Llc Process variation as die level traceability

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000045324A2 (en) * 1999-01-29 2000-08-03 Sensormatic Electronics Corporation Managing production and operations using read/write rfid tags
CN1399796A (zh) * 1999-11-24 2003-02-26 微激光系统公司 用于半导体器件个性化的装置与方法
US6542830B1 (en) * 1996-03-19 2003-04-01 Hitachi, Ltd. Process control system
JP2004157765A (ja) * 2002-11-06 2004-06-03 Tokyo Seimitsu Co Ltd 識別タグを備える半導体ウエハ、マスク、ウエハキャリアおよびマスクキャリアならびにこれらを用いる露光装置および半導体検査装置
JP2004179234A (ja) * 2002-11-25 2004-06-24 Renesas Technology Corp 半導体装置の製造方法
WO2004072747A1 (ja) * 2003-02-14 2004-08-26 Ntn Corporation Ｉｃタグを用いた機械部品ならびにその品質管理方法および異常検査システム

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000002236A2 (en) * 1998-07-07 2000-01-13 Memc Electronic Materials, Inc. Radio frequency identification system and method for tracking silicon wafers
CN1275328C (zh) * 2000-06-21 2006-09-13 日立马库塞鲁株式会社 半导体芯片和使用了该半导体芯片的半导体器件
JP3377786B2 (ja) * 2000-06-21 2003-02-17 日立マクセル株式会社 半導体チップ
JP2002074294A (ja) * 2000-08-25 2002-03-15 Dainippon Printing Co Ltd 非接触式データキャリア
US6524881B1 (en) * 2000-08-25 2003-02-25 Micron Technology, Inc. Method and apparatus for marking a bare semiconductor die
US6974782B2 (en) * 2002-08-09 2005-12-13 R. Foulke Development Company, Llc Reticle tracking and cleaning
JP2005057203A (ja) * 2003-08-07 2005-03-03 Renesas Technology Corp ウェハ、集積回路チップおよび半導体装置の製造方法
US7348887B1 (en) * 2004-06-15 2008-03-25 Eigent Technologies, Llc RFIDs embedded into semiconductors
KR100604869B1 (ko) * 2004-06-16 2006-07-31 삼성전자주식회사 식별수단을 가지는 반도체 웨이퍼 및 이를 이용한 식별방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6542830B1 (en) * 1996-03-19 2003-04-01 Hitachi, Ltd. Process control system
WO2000045324A2 (en) * 1999-01-29 2000-08-03 Sensormatic Electronics Corporation Managing production and operations using read/write rfid tags
CN1399796A (zh) * 1999-11-24 2003-02-26 微激光系统公司 用于半导体器件个性化的装置与方法
JP2004157765A (ja) * 2002-11-06 2004-06-03 Tokyo Seimitsu Co Ltd 識別タグを備える半導体ウエハ、マスク、ウエハキャリアおよびマスクキャリアならびにこれらを用いる露光装置および半導体検査装置
JP2004179234A (ja) * 2002-11-25 2004-06-24 Renesas Technology Corp 半導体装置の製造方法
WO2004072747A1 (ja) * 2003-02-14 2004-08-26 Ntn Corporation Ｉｃタグを用いた機械部品ならびにその品質管理方法および異常検査システム

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