CN100385684C - Film transistor and manufacturing method of its lightly mixed drain area - Google Patents
Film transistor and manufacturing method of its lightly mixed drain area Download PDFInfo
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- CN100385684C CN100385684C CNB2004100806048A CN200410080604A CN100385684C CN 100385684 C CN100385684 C CN 100385684C CN B2004100806048 A CNB2004100806048 A CN B2004100806048A CN 200410080604 A CN200410080604 A CN 200410080604A CN 100385684 C CN100385684 C CN 100385684C
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Abstract
The present invention relates to a method for manufacturing a lightly mixed drain region of a film transistor. Firstly, a polycrystalline silicon layer is formed on a base plate. Secondly, a grid insulation layer is formed on the polycrystalline silicon layer. Then, a cushioning layer and a grid are formed on the grid insulation layer, wherein the grid is positioned on a cushioning layer and is exposed out of a part of the cushioning layer. Finally, a mixed manufacturing process is done to form a lightly mixed drain region in the polycrystalline silicon layer corresponding to the lower side of the cushioning layer exposed by the grid. The present invention can save manufacturing cost and raise production efficiency.
Description
Technical field
The invention relates to a kind of semiconductor element and manufacture method thereof, and particularly about the invention of the manufacture method of a kind of thin-film transistor and lightly mixed drain area thereof.
Background technology
The transistorized manufacturing employing of polycrystal silicon film solid-phase crystallization more than early stage (SolidPhase Crystallization, SPC) manufacturing process, but its manufacturing process temperature is up to 1000 degree Celsius, so the essential higher quartz base plate of fusing point that adopts.Yet because the quartz base plate cost is expensive more many than glass substrate, and under the restriction of substrate size, panel approximately only has 2 to 3 inches, therefore can only develop small panel in the past.In recent years along with the continuous progress of laser technology, develop and a kind of excite state molecular laser annealing (Excimer Laser Annealing, ELA) manufacturing process, it uses laser beam irradiation in amorphous silicon membrane, crystallization again (recrystallization) becomes polysilicon membrane after making amorphous silicon membrane fusion (melting), and can below temperature 600 degree Celsius, finish whole manufacturing process, therefore utilize the polycrystalline SiTFT of this kind manufacturing process mode gained be otherwise known as low temperature polycrystalline silicon (Low TemperaturePoly-Silicon, LTPS) thin-film transistor.
The manufacturing process temperature required owing to low-temperature polysilicon film transistor is lower, make cost also can be applied to the manufacturing of low-temperature polysilicon film transistor far below the glass substrate of quartz base plate, thereby help to reduce manufacturing cost, and have advantages such as the little and electron mobility (electron mobility) of consumed power is big because polycrystalline SiTFT is compared with amorphous silicon film transistor, therefore the driving element with the low-temperature polysilicon film transistor manufacturing has been widely used in large-sized LCD at present.
Please refer to Fig. 1, the generalized section of a kind of low-temperature polysilicon film transistor that its expression is known.As shown in Figure 1, be formed with resilient coating (bufferlayer) 102 on the substrate 100, and be formed with polysilicon layer 110 on the resilient coating 102, and be formed with source area 112, drain region 114 and channel region 116 by (dopping) manufacturing process of mixing in this polysilicon layer 110, wherein channel 116 is between source area 112 and drain region 114.
Refer again to Fig. 1, gate insulation layer 120 covers polysilicon layer 110 and resilient coating 102, and grid 130 is disposed on the gate insulation layer 120 of channel region 116 tops.Dielectric layer 140 cover gate 130 and gate insulation layers 120, and be formed with contact hole in dielectric layer 140 and the gate insulation layer 120 and open 112a, 114a.In addition, source electrode conductive layer 152 and drain electrode conductive layer 154 are disposed on the dielectric layer 140, and source electrode conductive layer 152 is opened 112a, 114a by contact hole respectively with drain electrode conductive layer 154 and is electrically connected with source area 112 and drain region 114.
What deserves to be mentioned is,, can be formed with lightly mixed drain area (Lightly Doped Drain, LDD) 118 between source area 112, drain region 114 and the channel region 116 usually for preventing the generation of short-channel effect (short channe leffect).Be known in and make when having the polycrystalline SiTFT of lightly mixed drain area 118, usually need by the above light shield manufacturing process of twice, and carry out above doping manufacturing process twice, to form different source area 112/ drain region 114 and the lightly mixed drain areas 118 of doping content.Yet above-mentioned this kind made the difficulty that the mode of lightly mixed drain area causes light mask image to aim at easily, even and the doping way by self-aligned (self-align) also can't be avoided the complicated of manufacturing technology steps.
Summary of the invention
In view of this, purpose of the present invention be exactly provide a kind of can the simplified manufacturing technique step, and then the thin-film transistor of enhancing productivity.
Another object of the present invention provides a kind of manufacturing process with comparatively simplification, and helps the manufacture method of the lightly mixed drain area of enhancing productivity.
Another purpose of the present invention provides a kind of thin-film transistor with lightly mixed drain area of gradient type.
A further object of the present invention provides a kind of manufacture method that forms the shallow doped drain region of gradient type.
Based on above-mentioned or other purpose, the present invention proposes a kind of thin-film transistor, and it for example comprises substrate, polysilicon layer, gate insulation layer, resilient coating, grid, dielectric layer, source electrode conductive layer and drain electrode conductive layer.Wherein, polysilicon layer is disposed on the substrate, and the source/drain region that has channel region in this polysilicon layer, is positioned at the lightly mixed drain area of channel region both sides and is positioned at the lightly mixed drain area outside.In addition, gate insulation layer is disposed on the substrate, and covers polysilicon layer, and resilient coating is configured on the gate insulation layer corresponding to channel region and lightly mixed drain area top, and gate configuration is on corresponding to the resilient coating above the channel region.In addition, dielectric layer is configured on the gate insulation layer, and cover gate, and the source electrode conductive layer is arranged in surface and the dielectric layer and the gate insulation layer of dielectric layer, wherein source electrode conductive layer and source area are electrically connected, and the drain electrode conductive layer is arranged in surface and the dielectric layer and the gate insulation layer of dielectric layer, and wherein drain conductive layer and drain region are electrically connected.
In the present invention's thin-film transistor, the material of grid for example is a metal, and the material of resilient coating for example can or have metal level of alloy etc. for metal oxide, metal nitride, metal carbides.In addition, the amount that contains oxygen, nitrogen, carbon or alloy of resilient coating more can shorten along with the distance of itself and gate insulation layer and increase gradually.
In the present invention's thin-film transistor, near the position of source/drain region, its doping content is high more more for lightly mixed drain area.In addition, resilient coating for example is step structure or island structure.
Based on above-mentioned or other purpose, the present invention more proposes a kind of manufacture method of lightly mixed drain area.At first, on substrate, form polysilicon layer.Then, on polysilicon layer, form gate insulation layer.Then, form resilient coating and grid on gate insulation layer, wherein grid is positioned on the resilient coating, and exposes the resilient coating of part.Afterwards, the manufacturing process of mixing, to form lightly mixed drain area in polysilicon layer, wherein the lightly mixed drain area correspondence is positioned at the below of the partial buffer layer that grid exposes.
In preferred embodiment of the present invention, the method for above-mentioned formation resilient coating and grid for example is prior to forming grid cushioned material layer and gate material layers on the gate insulation layer.Afterwards, come etch-gate cushioned material layer and gate material layers, to form resilient coating and grid simultaneously by etching solution.Wherein, etching solution for the etching speed of gate material layers greater than the etching speed of etching solution for the grid cushioned material layer.In addition, the method of above-mentioned formation grid cushioned material layer and gate material layers for example is a sputter, and more comprise the feeding reacting gas in the process that forms the grid cushioned material layer, wherein reacting gas for example is oxygen-containing gas, nitrogenous gas, carbonaceous gas or the gas that contains alloy.In addition, the amount of the above-mentioned reacting gas that feeds for example is along with the time reduces gradually.
Based on above-mentioned, the manufacture method of the present invention's lightly mixed drain area formation resilient coating provides the ion screening effect when mixing, to make required lightly mixed drain area.The manufacture method of thin-film transistor and lightly mixed drain area thereof by the present invention, the step of only need mixing together just can form source/drain region and lightly mixed drain area simultaneously, therefore helps the simplified manufacturing technique step, and then enhances productivity.
State with other purpose, feature and advantage and can become apparent on the present invention for allowing, preferred embodiment cited below particularly, and join accompanying drawing, be described in detail below.
Description of drawings
Fig. 1 is the generalized section of known a kind of thin-film transistor.
Fig. 2 A～2I is the manufacturing process schematic diagram of a kind of thin-film transistor of the present invention in regular turn.
Fig. 3 is the generalized section of the thin-film transistor of another embodiment of the present invention.
Fig. 4 is the generalized section of the thin-film transistor of the present invention's another embodiment.
The main element symbol description
100: substrate
102: resilient coating
110: polysilicon layer
112: source area
112a: contact window
114: the drain region
114a: contact window
116: channel region
118: lightly mixed drain area
120: gate insulation layer
130: grid
140: dielectric layer
152: the source electrode conductive layer
154: the drain electrode conductive layer
200: substrate
202: resilient coating
210: polysilicon layer
210a: amorphous silicon layer
212: source area
212a: source electrode contact window
214: the drain region
214a: drain electrode contact window
216: channel region
218: lightly mixed drain area
220: gate insulation layer
222: resilient coating
222a: grid cushioned material layer
224: the first resilient coatings
226: the second resilient coatings
230: grid
230a: gate material layers
240: dielectric layer
252: the source electrode conductive layer
254: the drain electrode conductive layer
260: the patterning photoresist layer
Embodiment
Please refer to Fig. 2 A～2I, it represents the manufacturing process schematic diagram of a kind of thin-film transistor of the present invention in regular turn.
At first, shown in Fig. 2 A, on substrate 200, optionally form resilient coating 202, and on resilient coating 202, form amorphous silicon layer 210a.Wherein the material of substrate 200 for example is a glass, and the material of resilient coating 202 for example is a silicon dioxide, its role is to promote the tack of substrate 200 crystal silicon layer 210 (being shown in Fig. 2 B) more than follow-up formation, and it is when for example containing metal ion such as sodium in the substrate 200, available to prevent the metal ion pollution polysilicon layer 210 (being shown in Fig. 2 B) in the substrate 200.
Then, shown in Fig. 2 B, carry out dehydrogenation and handle, and amorphous silicon layer 210a is carried out laser annealing handle, it for example is an excite state molecular laser annealing manufacturing process, is polysilicon layer 210 so that amorphous silicon layer 210a recrystallizes into.
Then, shown in Fig. 2 C, on polysilicon layer 210, form gate insulation layer 220, the method that wherein forms gate insulation layer 220 for example is chemical vapour deposition (CVD) (ChemicalVapor Deposition, and the material of gate insulation layer 220 for example is silicon nitride (SiN) or silica (SiO) etc. CVD).
Afterwards, shown in Fig. 2 D, carry out the sputter manufacturing process, on gate insulation layer 220, to form grid cushioned material layer 222a.Wherein, the target that is used during sputter for example is the metal of chromium (Cr), aluminium (Al), copper (Cu), molybdenum Low ESRs such as (Mo), and the method that forms grid cushioned material layer 222a for example is to feed reacting gas in sputter, it for example can be to contain oxygen, nitrogenous, carbon containing or contain gas of alloy etc., with with metal reaction, and form the material layer that the gate material layers 230a (being shown in Fig. 2 E) of metal oxide, metal nitride, metal carbides or other etching characteristic and follow-up formation has difference.
Then, shown in Fig. 2 E, proceed the sputter manufacturing process,, wherein when forming gate material layers 230a, no longer feed reacting gas, to deposit simple metal material to form gate material layers 230a.Wherein, because gate material layers 230a is different with the composition of grid cushioned material layer 222a, so also difference to some extent of its etching characteristic.
Then, shown in Fig. 2 F, go up to form patterning photoresist layer 260 in gate material layers 230a, the method that wherein forms patterning photoresist layer 260 comprises gold-tinted manufacturing process such as carrying out photoresistance coating and exposure, development.
Afterwards, shown in Fig. 2 G, by patterning photoresist layer 260 for etch mask carries out the etching manufacturing process, so that gate material layers 230a and grid cushioned material layer 222a form grid 230 and resilient coating 222 respectively.Wherein, the etching solution that the etching manufacturing process is used is selected for use has very fast etching speed to gate material layers 230a, and grid cushioned material layer 222a is had relatively slow etching speed person.Thus, in etched process, not being patterned gate material layers 230a and the grid cushioned material layer 222a that photoresist layer 260 covered will be removed, and because etching solution has very fast etching speed for gate material layers 230a, therefore the phenomenon of lateral erosion (over etching) will appear in the gate material layers 230a of patterning photoresist layer 260 belows as shown in FIG., thereby exposes the partial buffer layer 222 of periphery.
Then, shown in Fig. 2 H, remove patterning photoresist layer 260, and carry out comprehensive ion doping manufacturing process, wherein dopant profile for example is that the P type mixes or the N type mixes, and defines channel region 216 in the crystal silicon layer 210 by grid 230 more than can be thereunder.In addition, because 222 pairs of ions of resilient coating of the part that grid 230 exposed have the property of covering, therefore corresponding to be exposed the polysilicon layer 210 of resilient coating 222 belows in can form the lower lightly mixed drain area 218 of doping content, and lightly mixed drain area 218 both sides be not subjected to form higher source area of doping content 212 and drain region 214 respectively in the polysilicon layer 210 that resilient coating 222 covers.
Afterwards, shown in Fig. 2 I, on gate insulation layer 220, form dielectric layer 240, and a plurality of source electrode contact window 212a of formation open 214a to expose source area 212 and drain region 214 with the drain electrode contact hole in dielectric layer 240 and gate insulation layer 220.Afterwards, form a plurality of source electrode conductive layers 252 and drain electrode conductive layer 254 again on dielectric layer 240, and source electrode conductive layer 252 is opened 212a by the source electrode contact hole respectively with drain electrode conductive layer 254 and is electrically connected with source area 212 and drain region 214 with drain electrode contact window 214a.
Based on above-mentioned, the grid of the present invention's thin-film transistor below disposes resilient coating, with the shielding when mixing, and the lower lightly mixed drain area of formation doping content.Wherein, the method that forms this resilient coating for example is as described in the above-mentioned embodiment, feeds reacting gas when sputter, to make grid because lateral erosion exposes the resilient coating of part by the otherness in the etching.Certainly, in not breaking away from thought range of the present invention, the ordinary skill of technical field that the present invention belongs to more can for example be made grid and resilient coating etc. respectively with different manufacturing technology steps by other manufacture.
What deserves to be mentioned is, in another preferred embodiment of the present invention, more can the amount of the reacting gas of feeding be changed, contain the resilient coating of the amount of oxygen, nitrogen, carbon or alloy with formation with the Level Change of deposition.
Please refer to Fig. 3, the generalized section of the thin-film transistor of another embodiment of its expression the present invention.Wherein, when forming grid cushioned material layer (not shown), for example be the oxygen that feeds different amounts in two stages, with the first higher resilient coating 224 of the oxygen content that obtains lower floor, and the second lower resilient coating 226 of the oxygen content on upper strata.And, by the different etching characteristic of first resilient coating 224 with second resilient coating 226, make second resilient coating 226 expose first resilient coating 224 of part after etching, grid 230 then exposes second resilient coating 226 of part, to form step structure.Thus, after the manufacturing process of mixing, different the covering property of ion that will be caused because of first resilient coating 224 and second resilient coating 226, and form lightly mixed drain area 218 with two kinds of different levels of doping.
Except the foregoing description, the amount of the reacting gas that the present invention fed also can be linear change with the reaction time.Please refer to Fig. 4, the generalized section of the thin-film transistor of its expression the present invention's another embodiment.As shown in Figure 4, resilient coating 222 is island structure, and it for example is that the amount of the reacting gas (for example oxygen) that feeds when sputter is successively decreased in time, and forms the metal oxide layer that oxygen content is successively decreased with height of deposition.By the resilient coating 222 of this island, can after doping, form the lightly mixed drain area 218 of gradient type (doping content changes along a direction).
In other words, the present invention can form the resilient coating of the etching characteristic with difference by the change to the amount of reacting gas, obtaining having the resilient coating of varied in thickness after etching, and then forms the lightly mixed drain area of gradient type.It should be noted that, the represented resilient coating of the foregoing description only is usefulness for example, in other embodiment of the present invention, the character of the lightly mixed drain area of more visual desire formation and correspondence provides the resilient coating with different structure, wherein only need just can reach easily with the collocation of gaseous species as the variation of the amount by reacting gas as described in the above-mentioned embodiment, detailed manufacturing process is this no longer superfluous stating.
In sum, the present invention forms needed lightly mixed drain area by the resilient coating of covering property of tool ion, wherein only need one light shield manufacturing process just can define resilient coating and grid simultaneously, therefore compare with known technology and can save above light shield, and the problem that can avoid known light mask image to aim at.In addition, lightly mixed drain area can be by forming with the manufacturing process of mixing with source/drain region, and need not increase extra manufacturing process and just can form the lightly mixed drain area with doping content variation.Therefore, not only can significantly save manufacturing cost by the present invention's the thin-film transistor and the manufacture method of lightly mixed drain area thereof, but simplified manufacturing technique step more, and then enhance productivity.
Though the present invention with preferred embodiment openly as above; right its is not in order to limit the present invention; the ordinary skill of any technical field that the present invention belongs to; in thought that does not break away from the present invention and scope; when can doing a little change and improvement, so the present invention's protection range is as the criterion when looking claims person of defining.
Claims (18)
1. thin-film transistor comprises:
Substrate;
Polysilicon layer is configured on this substrate, and the source/drain region that has channel region in this polysilicon layer, is positioned at the lightly mixed drain area of these channel region both sides and is positioned at this lightly mixed drain area outside;
Gate insulation layer is configured on this substrate, and covers this polysilicon layer;
First resilient coating is configured on this gate insulation layer corresponding to this channel region and this lightly mixed drain area top;
Second resilient coating, be configured on this first resilient coating, and the width of this second resilient coating is less than the width of this first resilient coating, wherein in this lightly mixed drain area by the doping content of part that this first and second resilient coating covers less than only by the doping content of this first part that resilient coating covers;
Grid is configured on this second resilient coating corresponding to this channel region top;
Dielectric layer is configured on this gate insulation layer, and covers this grid;
The source electrode conductive layer is arranged in surface and this dielectric layer and this gate insulation layer of this dielectric layer, and wherein this source electrode conductive layer and this source area are electrically connected; And
The drain electrode conductive layer is arranged in surface and this dielectric layer and this gate insulation layer of this dielectric layer, and wherein this drain electrode conductive layer and this drain region are electrically connected.
2. the thin-film transistor according to claim 1 is characterized in that the material of this grid comprises metal.
3. the thin-film transistor according to claim 2 is characterized in that the material of this first and second resilient coating comprises metallic compound.
4. the thin-film transistor, the material that it is characterized in that this first and second resilient coating according to claim 3 be selected from group that metal oxide, metal nitride and metal carbides form one of them.
5. the thin-film transistor according to claim 3 is characterized in that the tenor of this first resilient coating is lower than the tenor of this second resilient coating.
6. the thin-film transistor according to claim 1 is characterized in that the material of this first and second resilient coating comprises alloy.
7. the thin-film transistor according to claim 6 is characterized in that the amount of the alloy of this first resilient coating is higher than the amount of the alloy of this second resilient coating.
8. the thin-film transistor according to claim 1, the doping content that it is characterized in that this lightly mixed drain area is a gradient type.
9. the thin-film transistor according to claim 1 is characterized in that this first and second resilient coating constitutes step structure.
10. the thin-film transistor according to claim 1 is characterized in that this first and second resilient coating constitutes the island structure of ramped shaped.
11. the thin-film transistor according to claim 1 is characterized in that more comprising resilient coating, and this resilient coating is disposed between this substrate and this polysilicon layer.
12. the manufacture method of a lightly mixed drain area is characterized in that comprising:
On substrate, form polysilicon layer;
On this polysilicon layer, form gate insulation layer;
On this gate insulation layer, form first resilient coating;
On this first resilient coating, form second resilient coating, and the width of this second resilient coating is less than the width of this first resilient coating;
Form grid on this second resilient coating, wherein this grid exposes this second resilient coating of part; And
The manufacturing process of mixing, in this polysilicon layer, to form lightly mixed drain area, wherein in this lightly mixed drain area by the doping content of part that this first and second resilient coating covers less than only by the doping content of this first part that resilient coating covers.
13., it is characterized in that the method that forms this first and second resilient coating and this grid comprises according to the manufacture method of the described lightly mixed drain area of claim 12:
On this gate insulation layer, form grid cushioned material layer and gate material layers; And
Come this grid cushioned material layer of etching and this gate material layers by etching solution, to form this first and second resilient coating and this grid simultaneously, wherein this etching solution for the etching speed of this gate material layers greater than the etching speed of this etching solution for this grid cushioned material layer.
14. according to the manufacture method of the described lightly mixed drain area of claim 13, it is characterized in that the method that forms this grid cushioned material layer and this gate material layers comprises sputter, and in the process that forms this grid cushioned material layer, more comprise the feeding reacting gas.
15. according to the manufacture method of the described lightly mixed drain area of claim 14, it is characterized in that this reacting gas comprise oxygen-containing gas, nitrogenous gas and carbonaceous gas one of them.
16., it is characterized in that this reacting gas has alloy according to the manufacture method of the described lightly mixed drain area of claim 14.
17. according to the manufacture method of claim 14 a described lightly mixed drain area, the amount that it is characterized in that this reacting gas of being fed is along with the time reduces gradually.
18., it is characterized in that before forming this polysilicon layer, more being included on this substrate and forming resilient coating according to the manufacture method of the described lightly mixed drain area of claim 12.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100806048A CN100385684C (en) | 2004-10-08 | 2004-10-08 | Film transistor and manufacturing method of its lightly mixed drain area |
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| CNB2004100806048A CN100385684C (en) | 2004-10-08 | 2004-10-08 | Film transistor and manufacturing method of its lightly mixed drain area |
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| CN1758446A CN1758446A (en) | 2006-04-12 |
| CN100385684C true CN100385684C (en) | 2008-04-30 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101488477B (en) * | 2008-01-16 | 2012-06-06 | 中芯国际集成电路制造(上海)有限公司 | Integrated method for protecting polycrystalline and substrate surface |
| CN104733536B (en) * | 2013-12-20 | 2018-02-13 | 昆山工研院新型平板显示技术中心有限公司 | Thin film transistor (TFT) and its manufacture method |
| CN106711087A (en) * | 2016-12-26 | 2017-05-24 | 武汉华星光电技术有限公司 | Film transistor manufacturing method |
| CN110112099A (en) * | 2019-04-08 | 2019-08-09 | 深圳市华星光电技术有限公司 | The method for making LTPS TFT substrate |
Citations (4)
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| JPH07202210A (en) * | 1993-12-28 | 1995-08-04 | Sharp Corp | Thin film transistor and manufacture thereof |
| CN1296643A (en) * | 1999-03-10 | 2001-05-23 | 松下电器产业株式会社 | Thin-film transistor, liquid crystal panel, and method for producing the same |
| CN1319781A (en) * | 2000-03-27 | 2001-10-31 | 株式会社半导体能源研究所 | Semiconductor display device and making method thereof |
| CN1471136A (en) * | 2002-07-01 | 2004-01-28 | 株式会社半导体能源研究所 | Method for manufacturing semiconductor device |
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2004
- 2004-10-08 CN CNB2004100806048A patent/CN100385684C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07202210A (en) * | 1993-12-28 | 1995-08-04 | Sharp Corp | Thin film transistor and manufacture thereof |
| CN1296643A (en) * | 1999-03-10 | 2001-05-23 | 松下电器产业株式会社 | Thin-film transistor, liquid crystal panel, and method for producing the same |
| CN1319781A (en) * | 2000-03-27 | 2001-10-31 | 株式会社半导体能源研究所 | Semiconductor display device and making method thereof |
| CN1471136A (en) * | 2002-07-01 | 2004-01-28 | 株式会社半导体能源研究所 | Method for manufacturing semiconductor device |
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