CN100383947C - Method for inspecting pipe seam defect - Google Patents
Method for inspecting pipe seam defect Download PDFInfo
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- CN100383947C CN100383947C CNB2005100655822A CN200510065582A CN100383947C CN 100383947 C CN100383947 C CN 100383947C CN B2005100655822 A CNB2005100655822 A CN B2005100655822A CN 200510065582 A CN200510065582 A CN 200510065582A CN 100383947 C CN100383947 C CN 100383947C
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- Prior art keywords
- contact plunger
- semiconductor
- mentioned
- detector tube
- seam defect
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 230000007547 defect Effects 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 54
- 238000009413 insulation Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 31
- 229920005591 polysilicon Polymers 0.000 claims description 31
- 238000010894 electron beam technology Methods 0.000 claims description 12
- 238000001514 detection method Methods 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000009825 accumulation Methods 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 65
- 239000011229 interlayer Substances 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 15
- 230000002950 deficient Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000012544 monitoring process Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005429 filling process Methods 0.000 description 2
- 230000003760 hair shine Effects 0.000 description 2
- 238000003701 mechanical milling Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000000427 thin-film deposition Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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Abstract
The present invention provides a method for detecting the defect of a pipe seam, which comprises the steps that a semiconductor substrate on which an active region and an insulation region are arranged is offered; a plurality of semiconductor elements are formed on the semiconductor substrate, and a dielectric layer which is covered on the semiconductor substrate and the semiconductor elements is deposited. A first and a second contact plugs are formed in the dielectric layer for connecting with the active region and the insulation region on the semiconductor substrate respectively, and the first and the second contact plugs are irradiated by cathode beam so electric charges are accumulated on the second contact plug for connecting the insulation region. By the brightness contrast between the first and the second contact plugs, whether the defect of the pipe seam is formed between the contact plugs is judged.
Description
Technical field
The present invention relates to a kind of method in order to formed pipe flaw (piping) in the detecting production process of semiconductor, particularly relate to a kind of in the FEOL of semiconductor production, in order to the method for formed pipe flaw (piping) in detecting interlayer dielectric layer (inter-layer dielectric).
Background technology
In the semiconductor fabrication process, when in forming electronic component in the substrate for example after the MOS (metal-oxide-semiconductor) transistor (MOS transistor), deposit for example so-called interlayer dielectric layer of a dielectric layer usually and be covered in above-mentioned electronic component with as insulation or protect.Then in above-mentioned dielectric layer, form a plurality of contacts holes (contact hole), and fill a conductive layer in each contact hole, to form contact plunger (contact plug), thus, above-mentioned electronic component then can be via contact plunger and the electronic component of an outside lead and being electrically connected for example, and data-signal also can be passed to for example transistorized source electrode of electronic component or drain electrode through above-mentioned lead and contact plunger, with the running of control electronic component.
Below pass through Figure 1A～1B to set forth in the prior art manufacturing process of the contact plunger of a dynamic random access memory (DRAM).Shown in Figure 1A, a wafer 10 at first is provided, it comprises semiconductor substrate 12, and this semiconductor-based end 12, be preferably silicon base.Then form in the semiconductor-based end 12 or it in order to define active region isolation structure 13, wherein isolation structure 13 accessible region territory oxidation technologies (LOCOS) or shallow ditch groove separation process (STI) and form.Transistor 14,16,18,20 is positioned on the surface at the semiconductor-based end 12, wherein transistor 14 and transistor 18 shared identical polysilicon layer with as grid, and share identical doped region with as its source electrode with transistor 16, and transistor 20 is also shared the polysilicon layer of grids or the doped region of source electrode with transistor 16 and transistor 18 equally respectively.
Shown in Figure 1B, then utilize and deposit a dielectric layer 22 as Low Pressure Chemical Vapor Deposition (LPCVD), aumospheric pressure cvd method (APCVD) or plasma chemical vapor deposition thin film deposition processes such as (PECVD) on wafer 10, it can for example be but be not limited to contain tetraethoxysilane (the borophospho-tetra-ethyl-ortho silicate of boron, phosphorus; BPTEOS).Then carry out photoetching and etch process in dielectric layer 22, to form a plurality of contacts hole until the semiconductor-based end 12, afterwards again on dielectric layer 22 deposition one conductive layer for example a polysilicon layer form conductive plunger 26,28,30,32,34 and 36 filling above-mentioned contact hole.
Yet when for example transistorized size of semiconductor element heals to become to reducing and integration heals the cumulative added-time, then dielectric layer 22 does not easily form a plurality of spaces (void) 24 with pipe seam shape because of its fillibility is good between above-mentioned semiconductor element, and therefore contact hole partly will interconnect.Reflux (reflow) technology with the space in the minimizing dielectric layer 22 although can be undertaken one by the quick heat treatment mode usually, yet under the situation of major part, still can't avoid the existence in space.Therefore in the process that next forms contact plunger, partly contact plunger will interconnect or short circuit, for example shown in the contact plunger among Figure 1B 34 and 36, and it will cause transistor 14,16,18 and 20 to lose efficacy and can't suitably operate, and this is so-called pipe flaw.
Because above-mentioned technology is the technology of semiconductor product than leading portion, and according to the complexity of its production step, still need approximately just can finish after one to several months, then carry out the detection of rate of finished products, then observe at the element enforcement section or the membrane removal mode that lost efficacy again.Yet aforesaid way is not easy to do comprehensive detection, and be difficult to detect at the pipe flaw place, and sample treatment and detecting time are long, more can't do the monitoring of production online in real time, and may cause scrapping of online large-tonnage product when detecting problem.Therefore, the dealer utilizes the check of producing online product sampling property usually, yet and can't solve above-mentioned utilization section or the problem of fault detection is carried out in membrane removal, and expend huge manpower, time, and cost, and effect is also very limited.
In view of this, the dealer needs a kind of simple and easy, the effective method that also can monitor production line pipe flaw that dielectric layer deposition produces in real time, to increase the rate of finished products (yield) and the reliability (reliability) of product.
United States Patent (USP) the 6th, 825 provides a kind of method of detecting pipe flaw No. 119, and can be in order to solve the shortcoming of above-mentioned prior art.At first be to form in the dielectric layer polysilicon contact plunger in order to after connecting electronic component, implement polysilicon layer and the part dielectric layer of a chemical mechanical milling tech earlier to remove the dielectric layer top, implement a wet etch process afterwards again to remove partly dielectric layer, follow the pipe flaw in the dielectric layer of detecting sample under the irradiation of a ultraviolet light again, utilize polysilicon layer and dielectric layer (for example silicon oxide layer) to present the contrast (brightness contrast) of different brightness, by a real-time automatic defect classification tool (real-time automatic defect classification in following of the irradiation of ultraviolet light; ADC) do the detection of online (in-line) product.Thus, the rate of finished products of product and reliability all can obtain significant improvement.
Summary of the invention
The invention provides a kind of in order to the method for formed pipe flaw in the detecting production process of semiconductor, particularly relate to a kind of in production process of semiconductor, in order to the method for formed pipe flaw in the detecting interlayer dielectric layer.
Provided by the present invention in order in the detecting production process of semiconductor in interlayer dielectric layer the method for formed pipe flaw, its have non-destructive, real time and on line monitoring, detecting time short, can detect comprehensively and save time and advantage such as cost.
For reaching above-mentioned purpose, the invention provides a kind of method of detector tube seam defect, comprising: the semiconductor substrate is provided, has an active area and an insulation layer on it; On the above-mentioned semiconductor-based end, form a plurality of semiconductor elements, and deposit a dielectric layer and be covered on the above-mentioned semiconductor-based end and the semiconductor element; Formation one first and active area and the insulation layer of one second contact plunger in above-mentioned dielectric layer to be connected the above-mentioned semiconductor-based end respectively, and shine in above-mentioned first and second contact plunger with electron beam, make electric charge accumulate on second contact plunger that connects above-mentioned insulation layer, by the brightness contrast of first and second contact plunger, judge whether form pipe flaw between the two.
For above and other objects of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and conjunction with figs. is described in detail below.
Description of drawings
Figure 1A～1B sets forth the manufacturing process of the contact plunger of a dynamic random access memory of the prior art.
Fig. 2 A～2B sets forth the phenomenon that the present invention utilizes sweep electron microscope to observe.
Fig. 3 A～3B sets forth the embodiment that detects the tube gap defective according to the present invention.
The simple symbol explanation
110～wafer; 12～substrate; 13～isolation structure; 14,16,18,20～transistor; 22～dielectric layer; 24～space; 26,28,30,32,34,36～conductive plunger; 202,302～substrate; 204,304～active area; 206,306～insulation layer; 208,308～dielectric layer; 210,310,312～contact plunger; 314～electron beam; 316～tube gap defective;---～electrical conductance path.
Embodiment
In semi-conductive manufacture process, sweep electron microscope (scanning electronmicroscope; SEM) be commonly used to measure the live width of semiconductor element, and can be in order to the defective of observation product surface, the present invention then utilizes sweep electron microscope as detecting instrument, detects formed pipe flaw in the dielectric layer.
Fig. 2 A～2B sets forth the phenomenon that the present invention utilizes sweep electron microscope to observe.Fig. 2 A shows as has now the structure of contact plunger.Semiconductor substrate 202, it is preferably silicon base, on this semiconductor-based end 202 or wherein then have active area 204 and an insulation layer 206, wherein active area 204 for example is a doped well zone, and insulation layer 206 then can be including but not limited to existing regional oxidation structure (LOCOS) or fleet plough groove isolation structure (STI).Interlayer dielectric layer 208 shown in Fig. 2 A and contact plunger 210 then can form by deposition, photoetching, the engraving method of prior art, and wherein contact plunger 210 is preferably polysilicon.Polysilicon contact plunger 210 shown in Fig. 2 A is connected in the active area 204 at the semiconductor-based end 202.
For asking simplified illustration, so the symbology among Fig. 2 B is same as the explanation of same-sign among Fig. 2 A at this, and right main difference wherein is connected in the insulation layer 206 at the semiconductor-based end 202 for the polysilicon contact plunger 210 shown in Fig. 2 B.
With reference to Fig. 2 B, when the electron beam that utilizes sweep electron microscope scanned, owing to polysilicon contact plunger 210 is positioned on the insulation layer 206 at the semiconductor-based end 202, so its electronics can't be discharged via substrate 202.And work as electron charge gradually in accumulating and being full of in polysilicon contact plunger 210, then electron beam can't enter in the polysilicon contact plunger 210 again, thereby detecting reduces from the secondary electron quantity of polysilicon contact plunger 210, cause polysilicon contact plunger 210 images that observe with respect to polysilicon contact plunger 210 images of being looked among Fig. 2 A for dark.
Given this plant phenomenon, the present invention proposes a kind of method in order to formed pipe flaw in the detecting production process of semiconductor, and is specially adapted to detect the method for formed pipe flaw in the interlayer dielectric layer.
Fig. 3 A～3B sets forth implementation method of the present invention, and is simplified illustration at this, therefore adopts same-sign to indicate in Fig. 3 A～3B, to represent identical symbol description.The present invention in the manufacturing process of the contact plunger of semiconductor element, the spaciousness place of element on the Cutting Road of chip or chip and together form as shown in Figure 3A structure.Semiconductor substrate 302 at first is provided, and it is preferably silicon base.Then be formed with source region 304 and insulation layer 306 in semiconductor or on it, wherein insulation layer 306 can be including but not limited to existing regional oxidation structure (LOCOS) or fleet plough groove isolation structure (STI).With the oxidation of above-mentioned silicon base surface heat to form the silicon oxide dielectric layer, then blanket-deposited one conductive layer for example be a polysilicon layer, last utilize again existing skill for example photoetching and etch process with respectively with the gate dielectric and the gate electrode of above-mentioned silicon oxide dielectric layer and polysilicon layer formation metal-oxide half field effect transistor.
Utilize ion implantation technique to mix to form ion doped region at the active area 304 at the semiconductor-based end 302.Then utilize Low Pressure Chemical Vapor Deposition (LPCVD), aumospheric pressure cvd method (APCVD) or plasma chemical vapor deposition existing thin film deposition processes such as (PECVD) to form an interlayer dielectric layer 308.Yet, when semiconductor element for example the size of MOS (metal-oxide-semiconductor) transistor heal to become to dwindling, and productive set density is when increasing gradually, then deposit interlayer dielectric layer 308 to cover or to fill (gap fill) on the above-mentioned semiconductor-based end and semiconductor element the time, to be easy to wherein form pipe flaw 316, shown in Fig. 3 B.
Then as utilizing existing photoetching and etch process to form active area 304 and the insulation layer 306 that contact hole (contact opening) is connected in the semiconductor-based end 302, then deposit a conductive layer for example polysilicon layer to fill above-mentioned contact hole and to be covered on the interlayer dielectric layer 308, at last utilize chemical mechanical milling method or etching method to remove the polysilicon layer that is covered in interlayer dielectric layer 308 tops again, stay the polysilicon layer of contact in the hole to form first contact plunger (contact plug), 312 and second contact plunger 310, it is connected to the active area 304 and insulation layer 306 at the semiconductor-based end 302.
With reference to Fig. 3 A, it is shown in polysilicon contact plunger 312 and 310 structures under the interlayer dielectric layer 308 normal sedimentation situations.At first according to the above-mentioned phenomenon of utilizing structure shown in sweep electron microscope observation Fig. 2 A～2B, when the electron beam 314 that utilizes sweep electron microscope shines in polysilicon contact plunger 312 shown in Fig. 3 A and 310 structures, pass through to change voltage, irradiation time or the observation multiplying power of electron beam earlier, electric charge is accumulated in the polysilicon contact plunger 310 that connects insulation layer 306, thereby its detected secondary electron negligible amounts, and image is also comparatively gloomy.In addition, because polysilicon contact plunger 312 is positioned on the active area 304 at the semiconductor-based end 302, thereby electric charge can via the semiconductor-based end 302 as conducting path (shown in dotted line) and unlikely accumulation, therefore the secondary electron quantity that is observed is more, image is also comparatively bright.The image that the image that is observed like this will have different brightness contrast.
Fig. 3 B shows that interlayer dielectric layer 308 forms the polysilicon contact plunger 312 and 310 structures of tube gap defective 316 in filling process.When the electron beam 314 that utilizes sweep electron microscope shines in polysilicon contact plunger 312 shown in Fig. 3 B and 310 structures, form the electric charge accumulation to impel the polysilicon contact plunger 310 that is arranged on the insulation layer 306 by voltage, irradiation time or the observation multiplying power that changes electron beam.Yet because interlayer dielectric layer 308 forms tube gap defective 316 in filling process, thereby cause polysilicon contact plunger 310 and 312 to form short circuit, therefore the electron charge in polysilicon contact plunger 310 can be via the 316 formed short circuits of tube gap defective as charge-conduction approach (shown in dotted line), and discharge via the semiconductor-based end 302 together with the electric charge in the polysilicon contact plunger 312, therefore the image that both observed does not then have the image as the different brightness contrast of being observed among Fig. 3 A, and expression has pipe flaw.
Therefore, the present invention can utilize said method to carry out the detection of formed pipe flaw in the interlayer dielectric layer, and right the present invention is not subject to and utilizes sweep electron microscope as testing tool, also can utilize other fault detection machine that comprises electron beam to detect.
Method in order to formed pipe flaw in the detecting interlayer dielectric layer provided by the present invention, it is a kind of nondestructive detection, simple and the efficient height of method, and can be used as comprehensive detection, more can directly do real-time monitoring at line products, have real-time control production technology and save time, advantage such as manpower and cost.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (8)
1. the method for a detector tube seam defect comprises the following steps:
The semiconductor substrate is provided, has an active area and an insulation layer on it;
On this semiconductor-based end, form a plurality of semiconductor elements;
Depositing a dielectric layer is covered on the above-mentioned semiconductor-based end and the semiconductor element;
In this dielectric layer, form one first and be connected this active area and this insulation layer respectively with one second contact plunger; And
Shine in above-mentioned first and second contact plunger with electron beam, make electric charge accumulate on second contact plunger that connects above-mentioned insulation layer,, judge whether form pipe flaw between the two by the brightness contrast of first and second contact plunger.
2. the method for detector tube seam defect as claimed in claim 1 is wherein utilized sweep electron microscope or fault detection machine sensed luminance.
3. the method for detector tube seam defect as claimed in claim 1, wherein this active area comprises an ion doping zone.
4. the method for detector tube seam defect as claimed in claim 1, wherein this insulation layer inclusion region oxidation structure or fleet plough groove isolation structure.
5. the method for detector tube seam defect as claimed in claim 1, wherein above-mentioned semiconductor element comprises metal-oxide semiconductor transistor component.
6. the method for detector tube seam defect as claimed in claim 1, wherein above-mentioned first and second contact plunger is the polysilicon contact plunger.
7. the method for detector tube seam defect as claimed in claim 1, the wherein above-mentioned step of utilizing the electron beam irradiation to make second contact plunger form the electric charge accumulation also comprise voltage, irradiation time or the observation multiplying power that changes electron beam.
8. the method for detector tube seam defect as claimed in claim 1, wherein when first and second contact plunger did not have brightness contrast, expression had pipe flaw.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100655822A CN100383947C (en) | 2005-04-18 | 2005-04-18 | Method for inspecting pipe seam defect |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100655822A CN100383947C (en) | 2005-04-18 | 2005-04-18 | Method for inspecting pipe seam defect |
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| CN1855410A CN1855410A (en) | 2006-11-01 |
| CN100383947C true CN100383947C (en) | 2008-04-23 |
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| CNB2005100655822A Expired - Fee Related CN100383947C (en) | 2005-04-18 | 2005-04-18 | Method for inspecting pipe seam defect |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104465616B (en) * | 2013-09-23 | 2017-10-27 | 中芯国际集成电路制造(上海)有限公司 | The fail-safe analysis test structure and its method of testing of integrated circuit |
| CN109285793B (en) * | 2018-09-13 | 2021-01-01 | 武汉新芯集成电路制造有限公司 | Method for detecting void in dielectric layer and method for manufacturing semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6806104B1 (en) * | 2003-09-25 | 2004-10-19 | Powerchip Semiconductor Corp. | Method for detecting defect of semiconductor device |
| US6825119B1 (en) * | 2003-08-28 | 2004-11-30 | Powerchip Semiconductor Corp. | Method of piping defect detection |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6825119B1 (en) * | 2003-08-28 | 2004-11-30 | Powerchip Semiconductor Corp. | Method of piping defect detection |
| US6806104B1 (en) * | 2003-09-25 | 2004-10-19 | Powerchip Semiconductor Corp. | Method for detecting defect of semiconductor device |
Non-Patent Citations (1)
| Title |
|---|
| Electrical Characteristics of Non-visual Defects Detected byE-beam Inspection. Akihiro Miura, Masami Ikota, Issmu Sckihara, et al.Semiconductor Manufacturing, 2003 IEEE International Symposium. 2003 * |
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