KR20230084752A - Test Element Group and Semiconductor Device incluindg the same - Google Patents

Abstract

A test element group according to an embodiment of the present invention may include an active region extending in a first direction on a substrate; gate structures extending in a second direction crossing the active region on the substrate; first gate contact plugs disposed on the gate structures and contacting gate electrode layers of each of the gate structures; source/drain regions disposed on the active region on at least one side of the gate structures; and source/drain contact plugs disposed on each of the source/drain regions and electrically connected to each of the source/drain regions. The first gate contact plug may extend in the first direction while being spaced apart from the source/drain contact plugs in the second direction.

Description

Test element group and semiconductor device including the same {Test Element Group and Semiconductor Device includg the same}

The present invention relates to a test device group and a semiconductor device including the test device group.

In a process of manufacturing a semiconductor device using a semiconductor wafer, a test element group (TEG) for verifying a process may be provided on the wafer. Reliability defects can be prevented in advance and yield can be improved by preventing defects of actual chips from being transferred to the next process through defect detection of the test device group. Various studies have been conducted on the layout design of test element groups to accurately and quickly verify the causes of defects.

One of the technical problems to be achieved by the technical idea of the present invention is to provide a test element group for detecting defects such as open or short, and a semiconductor device including the same.

A test element group according to example embodiments may include an active region extending in a first direction on a substrate; gate structures extending in a second direction crossing the active region on the substrate; first gate contact plugs disposed on the gate structures and contacting gate electrode layers of each of the gate structures; source/drain regions disposed on the active region on at least one side of the gate structures; and source/drain contact plugs disposed on each of the source/drain regions and electrically connected to each of the source/drain regions. The first gate contact plug may extend in the first direction while being spaced apart from the source/drain contact plugs in the second direction.

A test element group according to example embodiments may include an active region extending in a first direction on a substrate; A first portion on the substrate extending in a second direction crossing the active region, and spaced apart from the first portion in the second direction on the substrate, facing the first portion and extending in the second direction. gate structures each including a second portion; a source/drain region disposed on the active region between the first portions of adjacent gate structures; a source/drain contact plug including a portion disposed on the source/drain region, electrically connected to the source/drain region, and extending in the second direction and disposed between the second portions of adjacent gate structures. ; and a gate contact plug disposed on the source/drain contact plug and the second parts of the gate structures and contacting gate electrode layers of the second parts of each of the gate structures.

A semiconductor device according to example embodiments includes an integrated circuit region in which a transistor is disposed; and a dummy area adjacent to the integrated circuit area and in which a plurality of test element groups are disposed. Each of the plurality of test element groups may include gate structures extending in a second direction crossing an active region extending in a first direction on a substrate; and a gate contact plug disposed on the gate structures, contacting gate electrode layers of each of the gate structures, and extending in the first direction, and including a pad region to which an electrical signal is applied.

By forming the detection pad of the test element group at the gate contact plug level for detecting an open or short circuit of a semiconductor element, it is possible to accurately detect a defect in a lower structure while reducing a test around time.

The various beneficial advantages and effects of the present invention are not limited to the above, and will be more easily understood in the process of describing specific embodiments of the present invention.

1 is a layout diagram illustrating a wafer including test element groups according to an exemplary embodiment.
Fig. 2 is a layout diagram illustrating a group of test elements according to an exemplary embodiment.
3A and 3B are cross-sectional views illustrating a test element group according to exemplary embodiments.
4 is a layout diagram illustrating a test element group according to exemplary embodiments.
5A and 5B are cross-sectional views illustrating a test element group according to exemplary embodiments.
6 is a layout diagram illustrating a test element group according to exemplary embodiments.
7A and 7B are cross-sectional views illustrating a test element group according to exemplary embodiments.
Fig. 8 is a layout diagram illustrating a test element group according to exemplary embodiments.
9A and 9B are cross-sectional views illustrating a test element group according to exemplary embodiments.
Fig. 10 is a layout diagram illustrating a test element group according to exemplary embodiments.
11A to 13B are cross-sectional views illustrating a manufacturing process of a test element group according to exemplary embodiments.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described as follows.

Hereinafter, terms such as "upper", "middle" and "lower" are replaced with other terms, such as "first", "second" and "third" to describe the components of the specification. may also be used for Terms such as "first", "second", and "third" may be used to describe various components, but the components are not limited by the above terms, and "first component" means " It may be named as "the second component".

1 is a layout diagram illustrating a wafer including test device groups according to exemplary embodiments.

Referring to FIG. 1 , a semiconductor device 10 according to example embodiments includes a plurality of chip regions 11 in which an integrated circuit chip is formed and a partition region defined between the plurality of chip regions 11 . (12) may be included. A plurality of chip regions 11 may be arranged along a plurality of rows and columns on the wafer.

Each of the plurality of chip areas 11 may include an integrated circuit area and a dummy area.

Semiconductor elements may be provided in the integrated circuit area, and various circuit elements such as resistors, capacitors, transistors, and diodes may be formed. The semiconductor device may be, for example, a memory cell device. In an illustrative example, the semiconductor device may be a flash memory device, a phase-change random access memory (PRAM) device, a resistive RAM (RRAM) device, a ferroelectric RAM (FeRAM) device, a magnetic RAM (MRAM) device, or a dynamic RAM (DRAM) device. , a static RAM (SRAM) device, a synchronous dynamic RAM (SDRAM) device, or the like, but is not limited thereto. In another embodiment, the semiconductor device may be a logic device.

A plurality of semiconductor processes may be performed to form semiconductor devices in the integrated circuit region of the plurality of chip regions 11 . When any one of a plurality of semiconductor processes does not proceed properly, a defect such as an open or short circuit may occur, which may be a major factor in significantly deteriorating the performance of a semiconductor device. For example, when the contact plug is misaligned and lands on the source/drain region, a contact failure occurs between the contact plug and the source/drain region, resulting in a gap between the contact plug and the source/drain region. Open defects may occur. Such defects may be a major factor in greatly degrading the performance of a semiconductor chip. Therefore, in the course of manufacturing a semiconductor device in the integrated circuit area, detection may be required to determine whether each of a plurality of semiconductor processes has been properly performed.

In order to determine the appropriateness of a semiconductor process in the integrated circuit area, a test element group (TEG) (such as 100 in FIG. 2 ) may be provided on the wafer. A plurality of test device groups may be disposed on the wafer. In an exemplary embodiment, the test device group may be disposed in a dummy area where no semiconductor devices are formed. The dummy area may be defined as an area other than the integrated circuit area. In another embodiment, the test element groups may be disposed in the partition region 12 or may be disposed in both the dummy region and the partition region 12 . The test element group disposed in the dummy area may remain in the final manufactured chip, whereas the test element group disposed in the division area 12 may not remain in the final manufactured chip.

The test element group may be formed at the same time as the semiconductor element in the integrated circuit area. By inspecting the electrical characteristics of the test element group in the middle of manufacturing the semiconductor element, it can be confirmed whether the semiconductor element is normally formed. The structure and defect detection method of the test element group TEG will be described in detail with reference to FIGS. 2, 3A, and 3B to be described later.

The division region 12 may be a region for separating the plurality of chip regions 11 from each other by a scribing process, for example, a scribe lane. Semiconductor devices formed in the integrated circuit region may not be disposed in the division region 12 . Considering the efficiency and reliability of the scribing process, the division area 12 may be defined as a plurality of straight lines defined between the plurality of chip areas 11 arranged along a plurality of rows and columns.

Hereinafter, a test element group 100 according to exemplary embodiments will be described with reference to FIGS. 2, 3A, and 3B.

2 is a layout diagram of a test element group according to exemplary embodiments, and FIGS. 3A and 3B are test element groups along lines I-I', II-II', III-III', and IV-IV' of FIG. 2 It shows cross-sectional views of (100).

Referring to FIGS. 2, 3A and 3B, the test device group 100 includes a substrate 101, an active region 105 on the substrate, a device isolation layer 110 defining the active region 105, and an active region ( 105), a plurality of channel layers 140 vertically spaced apart from each other, source/drain regions 150 in contact with the plurality of channel layers 140, and extending to cross the active region 105. The gate structures 160 , source/drain contact plugs 191 contacting the source/drain regions 150 , and gate contact plugs 192 contacting the gate structures 160 may be included.

The substrate 101 may have an upper surface extending in the x and y directions. The substrate 101 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the group ₃ semiconductor may include silicon, germanium, or silicon-germanium. The substrate 101 may be provided as a bulk wafer, an epitaxial layer, an epitaxial layer, a Silicon On Insulator (SOI) layer, or a Semiconductor On Insulator (SeOI) layer.

The device isolation layer 110 may define the active region 105 in the substrate 101 . The device isolation layer 110 may be formed by, for example, a shallow trench isolation (STI) process. According to example embodiments, the device isolation layer 110 may further include a region extending deeper and having a step below the substrate 101 . The device isolation layer 110 may partially expose an upper portion of the active region 105 . According to example embodiments, the device isolation layer 110 may have a curved upper surface having a higher level as it is closer to the active region 105 . The device isolation layer 110 may be made of an insulating material. The device isolation layer 110 may be, for example, oxide, nitride, or a combination thereof.

The active region 105 is defined by the device isolation layer 110 in the substrate 101 and may be disposed to extend in the x direction. The active region 105 may have a structure protruding from the substrate 101 . An upper end of the active region 105 may protrude from the top surface of the isolation layer 110 to a predetermined height. The active region 105 may be made of a part of the substrate 101 or may include an epitaxial layer grown from the substrate 101 . A portion of the active region 105 on the substrate 101 may be recessed at both sides of the gate structure 160 , and source/drain regions 150 may be disposed on the recessed active region 105 . The active region 105 may include impurities or doped regions including impurities.

The channel layers 140 may include two or more channel layers disposed spaced apart from each other in a direction perpendicular to the upper surface of the active region 105 , eg, in the z direction, on the active region 105 . The channel layers 140 may be spaced apart from the upper surface of the active region 105 while being connected to the source/drain region 150 . The channel layers 140 may have the same or similar width as the active region 105 in the y direction, and may have the same or similar width as the gate structure 160 in the x direction. However, according to embodiments, the channel layers 140 may have a reduced width such that side surfaces are located under the gate structure 160 in the x direction.

The channel layers 140 may be made of a semiconductor material, and may include, for example, silicon (Si). The channel layers 140 may be formed of, for example, the same material as the substrate 101 . The number and shape of the channel layers 140 may be variously changed in embodiments. For example, according to embodiments, the channel layers 140 may further include a channel layer disposed on the upper surface of the active region 105 .

Source/drain regions 150 may be disposed on the active region 105 on at least one side of the gate structure 160 . The source/drain regions 150 may be disposed in recess regions recessed from the upper surface of the active region 105 . As shown in FIG. 3A, the source/drain regions 150 have a generally flat top surface in the x-direction, and a circular portion, an elliptical portion, or a curved shape similar thereto is formed as a lower portion of the top surface. may have, but is not limited thereto. The shape of the source/drain regions 150 may be variously changed according to the distance between adjacent gate structures 160, the height of the active region 105, and the like.

As shown in FIG. 3B , the source/drain regions 150 may have pentagonal or similar shapes with cross sections along the y-direction, and may be partially recessed by the source/drain contact plug 191 . However, the shape of the source/drain region 150 is not limited thereto. According to embodiments, the source/drain regions 150 may have various shapes, for example, any one of a polygonal shape, a circular shape, and a rectangular shape.

The plurality of gate structures 160 are arranged to cross the active region 105 and the channel layers 140 over the active region 105 and the channel layers 140 and extend in one direction, for example, in the y direction. It can be. Channel regions of transistors may be formed in the active region 105 and the channel layers 140 crossing each of the gate structures 160 . The gate structures 160 include a gate electrode layer 163, a gate dielectric layer 162 between the gate electrode layer 163 and the channel layers 140, spacer layers 161 on side surfaces of the gate electrode layer 163, and a gate capping layer 164 on a top surface of the gate electrode layer 163 .

The gate dielectric layer 162 may be disposed between the active region 105 and the gate electrode layer 163 and between the channel layers 140 and the gate electrode layer 163, and may include at least some of the surfaces of the gate electrode layer 163. It can be arranged to cover. For example, the gate dielectric layer 162 may be disposed to surround all surfaces except for the top surface of the gate electrode layer 163 . The gate dielectric layer 162 may extend between the gate electrode layer 163 and the spacer layers 161, but is not limited thereto. The gate dielectric layer 162 may include an oxide, nitride, or high-k material. The high-k material may mean a dielectric material having a higher dielectric constant than that of silicon oxide (SiO ₂ ). The high dielectric constant material may be, for example, aluminum oxide (Al ₂ O ₃ ), tantalum oxide (Ta ₂ O ₃ ), titanium oxide (TiO ₂ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ) , zirconium silicon oxide (ZrSi _x O _y ), hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSi _x O _y ), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAl _x O _y ), lanthanum hafnium oxide (LaHf _x O _y ), hafnium aluminum oxide (HfAl _x O _y ), and praseodymium oxide (Pr ₂ O ₃ ).

The gate electrode layer 163 may fill a space between the channel layers 140 on top of the active region 105 and extend to the top of the channel layers 140 . The gate electrode layer 163 may be spaced apart from the channel layers 140 by the gate dielectric layer 162 . The gate electrode layer 163 may include a conductive material. For example, metal nitrides (e.g., at least one of titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN)), metal materials (e.g., aluminum (Al), tungsten (W), and molybdenum ( Mo)) and at least one of silicon (e.g., doped polysilicon).

The gate electrode layer 163 may be composed of two or more multi-layers. Spacer layers 161 may be disposed on both sides of the gate electrode layer 163 . The spacer layers 161 may insulate the source/drain regions 150 and the gate electrode layer 163 . The spacer layers 161 may have a multilayer structure according to example embodiments. The spacer layers 161 may include at least one of oxide, nitride, oxynitride, and low-k dielectric.

The gate capping layer 164 may be disposed on the gate electrode layer 163 and may be surrounded by the gate electrode layer 163 and the spacer layers 161 on a lower surface. The gate capping layer 164 may include, for example, silicon nitride.

Interlayer insulating layers may be disposed to cover the source/drain regions 150 , the gate structure 160 and the device isolation layer 110 . A plurality of interlayer insulating layers may be formed, and may include, for example, first to third interlayer insulating layers 181 , 182 , and 183 . In an exemplary embodiment, the first interlayer insulating layer 181 is disposed to cover the source/drain regions 150, the gate structure 160, and the device isolation layer 110, and the second interlayer insulating layer 182 may be disposed on the first interlayer insulating layer 181 , and the third interlayer insulating layer 183 may be disposed on the second interlayer insulating layer 182 . The first to third interlayer insulating layers 181 , 182 , and 183 may include, for example, at least one of oxide, nitride, oxynitride, and low-k dielectric. Defect detection by the test element group 100 is performed by the charged particle beam on the gate contact plug 192 after the formation of the first and second interlayer insulating layers 181 and 182 and before the formation of the third interlayer insulating layer 183. This can be done by investigating A specific defect detection method using the test element group 100 will be described later.

The source/drain contact plugs 191 may pass through the first and second interlayer insulating layers 181 and 182 to come into contact with the source/drain regions 150, and the source/drain regions 150 may be electrically connected to each other. signal can be applied.

The source/drain contact plug 191 may be disposed on the source/drain region 150, and as shown in the cross-sectional view III-III' of FIG. 3B, the source/drain contact plug 191 is longer than the source/drain region 150 along the y direction. can have any length. The source/drain contact plugs 191 may be disposed between adjacent gate structures 160 and may have shorter lengths along the y-direction than the gate structures 160 . As shown in FIG. 3A , an upper surface of the source/drain contact plug 191 may be disposed at a higher level than a lower surface of the gate contact plug 192 .

The source/drain contact plug 191 may have an inclined side surface in which a width of a lower part is narrower than a width of an upper part according to an aspect ratio, but is not limited thereto. The source/drain contact plug 191 may be disposed to recess the source/drain region 150 to a predetermined depth. The source/drain contact plug 191 may include, for example, a metal nitride (e.g., at least one of titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN)) and a metal material (aluminum (Al), tungsten ( W) and at least one of molybdenum (Mo)).

The test element group 100 may further include dummy contact plugs 191'. The dummy contact plugs 191 ′ may not cross the active region 105 and may not contact the source/drain region 150 . The dummy contact plugs 191' may be disposed at the same locations as source/drain contact plugs formed in actual chip regions, and may be formed simultaneously with the source/drain contact plugs 191. The dummy contact plugs 191' are not used for defect detection, but may be configured to minimize a change point with an actual chip. The dummy contact plugs 191' may not contact the gate contact plug 192 that is a detection pad, and the dummy contact plugs 191' may be omitted according to embodiments.

The gate contact plug 192 may be disposed on the plurality of gate structures 160 on top of the device isolation layer 110 . The gate contact plug 192 may be spaced apart from the active region 105 in the y direction and may be spaced apart from the source/drain contact plug 191 in the y direction. The gate contact plug 192 may contact the gate electrode layers 163 by recessing the gate capping layers 164 of the plurality of gate structures 160 . The gate contact plug 192 may apply an electrical signal to the gate electrode layers 163 . At least some of the gate capping layers 164 may remain without being recessed. For example, as shown in the IV-IV' cross-sectional view of FIG. 3B , both side portions of the gate capping layers 164 contacting the spacer layers 161 may remain.

The gate contact plug 192 may be disposed to recess at least a portion of the first and second interlayer insulating layers 181 and 182 covering the source/drain regions 150 and the gate structures 160 to a predetermined depth. As shown in the IV-IV′ cross-sectional view of FIG. 3B , the first interlayer insulating layer 181 may be recessed to a greater depth than the gate capping layers 164 . This is due to a difference in selectivity between the first interlayer insulating layer 181 and the gate capping layer 164 . For example, when the first interlayer insulating layer 181 includes silicon oxide and the gate capping layers 164 include silicon nitride, oxide has a higher selectivity than nitride, so The etching rate of the first interlayer insulating layer 181 may be higher than the etching rate of the gate capping layer 164 . For this reason, the gate contact plug 192 may be disposed to be recessed to a greater depth in the first interlayer insulating layer 181 than the gate capping layers 164 . However, the shape of the gate contact plug 192 is not limited thereto, and the recessed shape may vary depending on the types of materials of the gate capping layers 164 and the first interlayer insulating layer 181 .

Referring to FIG. 2 , the gate contact plug 192 may have a substantially H shape when viewed from the top. The gate contact plug 192 may cross the plurality of gate structures 160 and extend in the x direction and may have a shape having a predetermined thickness in the z direction. Since the gate contact plug 192 has such a shape, it is easy to apply an electrical signal, and it is possible to easily identify a difference in brightness of an SEM image depending on whether or not a defect is present. That is, the gate contact plug 192 may function as a pad for detecting defects. The shape of the gate contact plug 192 may be variously changed within the range of functioning as a detection pad. For example, the upper surface of the gate contact plug 192 may have a rectangular shape, an elliptical shape, a ladder shape, or the like.

The gate contact plug 192 may include, for example, a metal nitride (e.g., at least one of titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN)) and a metal material (aluminum (Al) or tungsten (W)). and at least one of molybdenum (Mo). In an exemplary embodiment, the gate contact plug 192 may include the same material as the source/drain contact plug 191 .

The test device group 100 illustrated in FIGS. 2 to 3B may detect defects in a lower structure of a semiconductor device. In the test device group 100, a short between the gate structures 160 and the source/drain contact plugs 191 adjacent thereto and a short between the gate structures 160 and the source/drain regions 150 adjacent thereto are checked. can be detected.

Defect detection by the test element group 100 irradiates a charged particle beam such as an electron beam to the gate contact plug 192 to induce a voltage difference, and the test element group 100 It can be performed by analyzing the brightness of the gate contact plug 192 in a scanning electron microscope (SEM) image of .

As shown in FIGS. 2 and 3A , the gate contact plug 192 may contact the gate electrode layers 163 of each of the plurality of gate structures 160 and transmit an electrical signal to the gate electrode layers 163 . can be authorized. Charges are also accumulated in the gate electrode layers 163 contacting the gate contact plug 192 by the charged particle beam irradiated onto the gate contact plug 192 .

When the test element group 100 is normally formed, charges due to the charged particle beam may be accumulated in the gate contact plug 192 and the gate electrode layers 163 . The gate contact plug 192 on the SEM image may appear bright due to accumulated charges.

In contrast, when a defect occurs in the lower structure of the test device group 100, the gate contact plug 192 may appear dark on the SEM image. For example, when a short circuit failure occurs between the gate structure 160 and the adjacent source/drain contact plug 191, charges accumulated in the gate electrode layer 163 through the gate contact plug 192 are transferred to the source/drain contact plug ( 191), it may move to the source/drain region 150 and leak. Because of this, since charges are not accumulated in the gate contact plug 192, the gate contact plug 192 may appear dark on the SEM image.

Similarly, even when a short circuit failure occurs between the gate structure 160 and the source/drain region 150, the gate contact plug 192 appears dark on the SEM image, so the lower structure of the test device group 100 defects can be detected.

As described above, defect detection by the test element group 100 may be performed by forming the gate contact plug 192 and then irradiating the gate contact plug 192 with a charged particle beam. That is, the test element group according to the present embodiment may detect device defects by using the gate contact plug 192 as a detection pad before forming a BEOL (Back End Of Line). Since the test element group according to the present embodiment performs a defect test before forming the BEOL, the test around time of the semiconductor device is reduced, and only the defect in the lower structure is selectively detected by excluding the effect of the BEOL defect. can do. In this way, the efficiency and accuracy of inspection can be improved.

In an exemplary embodiment, the test device group 100 may not include wires in a BEOL level layer (eg, M1 layer). As shown in FIGS. 3A and 3B , the test device group 100 may further include a third interlayer insulating layer 183 covering an upper surface.

Next, FIG. 4 is a layout diagram illustrating a test element group 100A according to exemplary embodiments, and FIGS. 5A and 5B are cross-sectional views illustrating the test element group 100A according to exemplary embodiments.

5A and 5B show cross-sectional views of the test element group 100 along lines I-I', II-II', III-III' and IV-IV' in FIG. 4 .

In the embodiment of FIGS. 4 to 5B, if the same reference numbers as those of FIGS. 2 to 3B but different alphabets are used to describe a different embodiment from FIGS. 2 to 3B, the same reference numbers as described above. Features described in may be the same or similar.

The test device group 100A of FIGS. 4 to 5B further includes an upper contact plug 193 and some of the gate structures spaced apart in the y direction, so that the test device group of FIGS. 2 to 3B There is a difference from (100).

Referring to FIGS. 4 to 5B , the test device group 100A may include a first gate structure 160A_1 and second gate structures 160A_2 .

The first gate structure 160A_1 may cross the active region 105 on the substrate 101 and may extend in the y direction to contact the gate contact plug 192A. Each of the second gate structures 160A_2 may include a first portion P1 and a second portion P2. The first portion P1 may cross the active region 105 on the substrate 101 and extend in the y direction, and may overlap a portion of the first gate structure 160A_1 in the x direction. The second portion P2 may be spaced apart from the first portion P1 in the y-direction, face the first portion P1, extend in the y-direction, and overlap a portion of the first gate structure 160A_1 in the x-direction. there is. The first gate structure 160A_1 may have a longer length in the y direction than the first and second portions P1 and P2 of the second gate structure 160A_2 .

4 to 5B show an embodiment including one first gate structure 160A_1 and a plurality of second gate structures 160A_2, but the first and second gate structures 160A_1 and 160A_2 The number, location, etc. are not limited thereto, and may be changed according to a connection structure of elements, a defect detection target, and the like.

The test element group 100A may further include an upper contact plug 193 in addition to the source/drain contact plug 191A and the gate contact plug 192A.

The source/drain contact plugs 191A may be disposed on the source/drain regions 150 and electrically connected to the source/drain regions 150 . The source/drain regions 150 and the source/drain contact plugs 191A are interposed between the first gate structure 160A_1 and the first part P1 of the second gate structure 160A_2 adjacent to the first gate structure 160A_2, and between the adjacent second gate structure 160A_2. It may be disposed between the first portions P1 of the structures 160A_2.

The upper contact plug 193 may be disposed on the source/drain contact plug 191A and the first gate structure 160A_1. The upper contact plug 193 may contact and be electrically connected to the source/drain contact plug 191A. The upper contact plug 193 may be disposed to recess the second interlayer insulating layer 182 and the gate capping layer 164 of the first gate structure 160A_1 to contact the gate electrode layer 163 . The source/drain contact plug 191A and the first portion P1 of the second gate structure 160A_2 may be electrically connected by the upper contact plug 193 .

The upper contact plug 193 may be formed in the same process as the gate contact plug 192A. The upper contact plug 193 may have an upper surface disposed at the same level as the upper surface of the gate contact plug 192A, and may include the same material as the gate contact plug 192A.

The gate contact plug 192A may be disposed on the second portion P2 of the first gate structure 160A_1 and the second gate structure 160A_2. The gate contact plug 192A may contact and be electrically connected to the gate electrode layer 163 of the first gate structure 160A_1 and the gate electrode layers 163 of the second part P2 of the second gate structure 160A_2. there is.

The test element group 100A shown in FIGS. 4 to 5B may detect an open defect between the source/drain contact plug 191A and the upper contact plug 193 .

The gate contact plug 192A may contact the gate electrode layers 163 of the second portions P2 of the first gate structure 160A_1 and the second gate structures 160A_2 , respectively. Charges are accumulated in the gate electrode layers 163 contacting the gate contact plug 192A by the charged particle beam irradiated onto the gate contact plug 192A.

When the test element group 100A is normally formed, the charge accumulated in the gate contact plug 192A by the charged particle beam is transferred to the gate electrode layer 163 of the first gate structure 160A_1, the upper contact plug 193, and the source/drain. It may move to the source/drain region 150 through the contact plug 191A. That is, since charges are not accumulated in the gate contact plug 192A, the gate contact plug 192A may appear dark on the SEM image.

In contrast, when a defect occurs in the lower structure of the test element group 100A, for example, when an open defect occurs between the source/drain contact plug 191A and the upper contact plug 193, the charge by the charged particle beam Since it does not move to the source/drain region 150 and accumulates in the gate contact plug 192A, the first gate structure 160A_1, and the upper contact plug 193, the gate contact plug 192A on the SEM image may appear bright. .

In the test element group 100A of FIGS. 4 to 5B, the gate contact plug 192A is configured as a detection pad, as in the embodiment of FIGS. Accuracy can be improved.

Next, FIG. 6 is a layout diagram illustrating a test element group 100B according to exemplary embodiments, and FIGS. 7A and 7B are cross-sectional views illustrating a test element group 100A according to exemplary embodiments.

7A and 7B are cross-sectional views of the test element group 100B along lines I-I', II-II', III-III' and IV-IV' of FIG. 6 .

In the embodiment of FIGS. 6 to 7B, if the same reference numbers as those of FIGS. 2 to 3B but different alphabets are used to describe a different embodiment from FIGS. 2 to 3B, the same reference numbers as described above. Features described in may be the same or similar.

The test element group 100B of FIGS. 6 to 7B has gate structures 160B separated in the y direction and gate contact plug 192B contacting source/drain contact plug 191B_2. There is a difference from the test element group 100 of FIGS. 2 to 3B.

Referring to FIGS. 6 to 7B , the gate structures 160B of the test device group 100B may include a first part P1 and a second part P2 . The first portion P1 may cross the active region 105 on the substrate 101 and extend in the y direction. The second portion P2 may be spaced apart from the first portion P1 in the y direction, face the first portion P1, and may extend in the y direction. The second portion P2 is disposed on the device isolation layer 110 and may not cross the active region 105 .

The test device group 100B may include a first source/drain contact plug 191B_1 and a second source/drain contact plug 191B_2. The first and second source/drain contact plugs 191B_1 and 191B_2 may be disposed on the source/drain regions 150 and electrically connected to the source/drain regions 150 .

The first source/drain contact plugs 191B_1 may be disposed between the first portions P1 of adjacent gate structures 160B. The first source/drain contact plugs 191B_1 may have a length similar to that of the first portions P1 of the gate structures 160B along the y direction.

The second source/drain contact plug 191B_2 is disposed on the source/drain region 150 between the first portions P1 of the gate structures 160B and extends in the y direction, thereby forming the gate structures 160B. It may include a part disposed between the second parts P2 of . The second source/drain contact plug 191B_2 may have a longer length along the y-direction than the first source/drain contact plug 191B_1.

The gate contact plug 192B may be disposed on the second portion P2 of the gate structure 160B and the second source/drain contact plug 191B_2. The gate contact plug 192B may be disposed on the isolation layer 110 . The gate contact plug 192B may be disposed to recess the second interlayer insulating layer 182 and the gate capping layers 164 of the second portion P2 of the gate structures 160B. The gate contact plug 192B may contact and be electrically connected to the gate electrode layers 163 of the second portions P2 of the gate structures 160B. The gate contact plug 192B may contact and be electrically connected to the second source/drain contact plug 191B_2.

The number and arrangement positions of the first and second source/drain contact plugs 191B_1 and 191B_2 are not limited to those illustrated and may be changed according to the structure of a semiconductor device.

The test element group 100B illustrated in FIGS. 6 to 7B may detect an open defect due to disconnection of the second source/drain contact plug 191B_2.

The gate contact plug 192B may contact the second portion P2 of the gate structures 160B and the second source/drain contact plug 191B_2. Charges are charged on the second portion P2 of the gate structures 160B and the second source/drain contact plug 191B_2 contacting the gate contact plug 192B by the charged particle beam irradiated to the gate contact plug 192B. is accumulated

When the test element group 100B is normally formed, charges accumulated in the second source/drain contact plug 191B_2 by the charged particle beam may move to the source/drain region 150 and leak. That is, since charges are not accumulated in the gate contact plug 192B, the gate contact plug 192B may appear dark on the SEM image.

In contrast, when a defect occurs in the lower structure of the test element group 100B, for example, when a disconnection defect occurs in the second source/drain contact plug 191B_2, the charge by the charged particle beam is transferred to the second source/drain contact It cannot move to the source/drain region 150 through the plug 191B_2. Accordingly, since charges are accumulated in the gate contact structure 192B, the gate contact plug 192B may appear bright on the SEM image.

Since the test element group 100B of FIGS. 6 to 7B configures the MOL level gate contact plug 192B as a detection pad, as in the embodiment of FIGS. 2 to 3B , the test required time is reduced and the BEOL Since the influence of defects is excluded, the accuracy of defect detection can be improved.

Next, FIG. 8 is a layout diagram illustrating a test element group 100C according to exemplary embodiments, and FIGS. 9A and 9B are cross-sectional views illustrating the test element group 100C according to exemplary embodiments.

9A and 9B show cross-sectional views of the test element group 100 along lines I-I', II-II', III-III' and IV-IV' of FIG. 8 .

In the embodiment of FIGS. 8 to 9B, if the same reference numbers as those of FIGS. 2 to 3B but different alphabets are used to describe a different embodiment from FIGS. 2 to 3B, the same reference numbers as described above. The features described above may be the same or similar.

In that the test device group 100C of FIGS. 8 to 9B further includes second gate contact plugs 193C in addition to the first gate contact plug 192C, the test device group of FIGS. 2 to 3B There is a difference from (100).

The second gate contact plugs 193C may be disposed on the gate structures 160C. The second gate contact plugs 193C may be disposed to recess the gate capping layers 164 of the gate structures 160C and may contact the gate electrode layers 163 . The second gate contact plugs 193C may be disposed between the source/drain contact plugs 191C.

8 to 9B, one second gate contact plug 193C is provided on each gate structure 191C, but the number of gate contact plugs 193C disposed on each gate structure 191C is Not limited to this. According to example embodiments, a plurality of gate contact plugs may be disposed on each gate structure. For example, as shown in FIG. 10 , three second gate contact plugs 193D may be disposed on each gate structure 160D.

In the test device group 100C shown in FIGS. 8 to 9B , a short circuit between the gate structures 160C and the source/drain contact plugs 191C adjacent thereto, and the source/drain regions adjacent thereto the gate structures 160C Short circuits 150 and short circuits between the second gate contact plugs 193C and source/drain contact plugs 191C adjacent to the second gate contact plugs 193C may be detected.

The first gate contact plug 192C may be electrically connected to the gate structures 160C and the second gate contact plug 193C. The first gate contact plug 192C, the gate electrode layers 163 of the gate structures 160C, and the second gate contact plugs 193C are affected by the charged particle beam irradiated to the first gate contact plug 192C. Charge accumulates.

When the test element group 100C is normally formed, charges due to the charged particle beam may be accumulated in the first gate contact plug 192C, the gate electrode layers 163, and the second gate contact plugs 193C. As a result, the first gate contact plug 192C on the SEM image may appear bright due to accumulated charges.

In contrast, when a defect occurs in the lower structure of the test device group 100C, the first gate contact plug 192C may appear dark on the SEM image. For example, when a short circuit failure occurs between the source/drain contact plug 191C and the second gate contact plug 193C, charges due to the charged particle beam are transferred from the second gate contact plug 193C to the adjacent source/drain contact plug. It may leak by moving to the source/drain region 150 through 191C. That is, since charges are not accumulated in the first gate contact plug 192C, the first gate contact plug 192C may appear dark on the SEM image.

The above-described test element groups 100, 100A, 100B, and 100C of FIGS. 2 to 10 are disposed in the plurality of chip regions 11 of the semiconductor device 10 shown in FIG. It can be used to detect defects that have occurred.

In an exemplary embodiment, the plurality of chip areas ( 11 in FIG. 1 ) include a plurality of test element groups of different types, and a cause of defect detection may be identified by comparing test results of each test element group.

For example, the test device group 100 shown in FIGS. 2 to 3B has short circuits between gate structures and source/drain contact plugs adjacent thereto, and short circuits between gate structures and source/drain regions adjacent thereto. can be detected. In addition to the defects detectable by the test element group 100 of FIGS. 2 to 3B , the test element group 100C shown in FIGS. 8 to 9B has a gap between gate contact plugs and source/drain contact plugs adjacent thereto. A short circuit defect can be additionally detected.

As a result of defect detection by the test element groups 100 and 100C, the test element group 100 of FIGS. 2 to 3B is determined to be normal (the pad is bright on the SEM image), and the test element group 100C of FIGS. 8 to 9B ) is determined to be defective (the pad is dark on the SEM image), it can be determined that the cause of the defect is a short defect between gate contact plugs and source/drain contact plugs adjacent thereto.

In the test element groups according to the present embodiment, since the detection pad for irradiating the charged particle beam is a gate contact plug formed at the MOL level, unlike the case where the pad is formed at the BEOL level, defects at the BEOL level (e.g., contact plug and M1 Defects between layer pads, etc.) can be selectively detected at the MOL level without detection. Accordingly, the accuracy of defect detection can be increased, and since the detection is possible before the BEOL level is formed, the inspection time can be shortened.

In the embodiments of FIGS. 2 to 10 , test device groups in the case where the semiconductor device is an MBCFET ^TM (Multi Bridge Channel FET) have been described, but are not limited thereto. In another embodiment, even when the semiconductor device is a finFET device, which is a transistor having a fin structure in an active region, the test device groups according to the present invention may be applied.

Next, in FIGS. 11A to 13B , cross-sections are shown according to a process sequence to describe a method of manufacturing the test element group 100 according to exemplary embodiments. 11A to 13B describe an embodiment of a manufacturing method for manufacturing the semiconductor device of FIGS. 2 to 3B and show cross-sections corresponding to FIGS. 3A and 3B.

First, steps prior to forming the source/drain regions 150 in the manufacturing method of the test element group will be briefly described.

A stack structure in which the sacrificial layers 120 and the channel layers 140 are alternately stacked may be formed on the substrate 101 . An active structure may be formed by removing a portion of the laminated structure and the substrate 101 . The active structure may include sacrificial layers 120 and channel layers 140 that are alternately stacked with each other, and a portion of the substrate 101 is removed to protrude from the upper surface of the substrate 101. 105) may be further included. The device isolation layer 110 may be formed in a region where a portion of the substrate 101 is removed by filling an insulating material and then recessing the active region 105 so as to protrude.

Referring to FIGS. 11A and 11B , sacrificial gate structures 170 and spacer layers 161 may be formed on the active structure. A recess is formed by removing the exposed sacrificial layers 120 and the channel layers 140 between the sacrificial gate structures 170 using the sacrificial gate structures 170 and the spacer layers 161 as a mask. area can be formed.

Source/drain regions 150 may be formed in the recess region. The source/drain regions 150 may be formed by performing an epitaxial growth process in the recess region. The source/drain regions 150 may contact side surfaces of the channel layers 140 . The source/drain regions 150 may include impurities by in-situ doping, and may include a plurality of layers having different doping elements and/or doping concentrations.

Referring to FIGS. 12A and 12B , a first interlayer insulating layer 181 may be formed between the sacrificial gate structures 170 and the sacrificial layers 120 and the sacrificial gate structures 170 may be removed.

The first interlayer insulating layer 181 may be formed by forming an insulating film covering the sacrificial gate structures 170 and the source/drain regions 150 and performing a planarization process.

The sacrificial layers 120 and the sacrificial gate structures 170 may be selectively removed with respect to the spacer layers 161 , the first interlayer insulating layer 181 , and the channel layers 140 . After the sacrificial gate structures 170 are removed to form the upper gap regions UR, the lower gap regions LR are formed by removing the sacrificial layers 120 exposed through the upper gap regions UR. can form For example, when the sacrificial layers 120 include silicon germanium (SiGe) and the channel layers 140 include silicon (Si), the sacrificial layers 120 contain peracetic acid. It can be selectively removed by performing a wet etching process using an etchant.

Referring to FIGS. 13A and 13B , a gate structure 160 may be formed in the upper gap regions UR and the lower gap regions LR.

The gate dielectric layer 162 may be formed to conformally cover inner surfaces of the upper gap regions UR and the lower gap regions LR. The gate electrode layer 163 may be formed to completely fill the upper gap regions UR and lower gap regions LR. The gate electrode layer 163 and the spacer layers 161 may be removed to a predetermined depth from the top of the upper gap regions UR. A gate capping layer 164 may be formed in a region from which the gate electrode layer 163 and the spacer layers 161 are removed in the upper gap regions UR. Accordingly, the gate structure 160 including the gate dielectric layer 162 , the gate electrode layer 163 , the spacer layers 161 , and the gate capping layer 164 may be formed.

Then, the second interlayer insulating layer 182 may be formed by forming an insulating film covering the gate structure 160 and the first interlayer insulating layer 181 and performing a planarization process.

Next, referring to FIGS. 2 , 3A and 3B together, a source/drain contact plug 191 and a gate contact plug 192 may be formed.

The source/drain contact plug 191 may be formed by patterning the first and second interlayer insulating layers 181 and 182 to form a contact hole and filling the contact hole with a conductive material. A lower surface of the contact hole may be recessed into the source/drain region 150 . The contact hole may be formed to extend along the y direction between adjacent gate structures 160 .

The gate contact plug 192 is formed by patterning the first and second interlayer insulating layers 181 and 182 and the gate capping layer 164 of the gate structure 160 to form a contact hole and filling the contact hole with a conductive material. It can be. As shown in the layout diagram of FIG. 2 , the top surface of the gate contact plug 192 may be formed to have a substantially H shape, but is not limited thereto and may be variously changed.

After the semiconductor device ( 10 in FIG. 1 ) is selectively inspected for defects, a subsequent BEOL process may be performed on the integrated circuit area of the plurality of chip areas ( 11 in FIG. 1 ). At the same time, a third interlayer insulating layer 183 covering an entire upper surface of the test element group 100 may be formed.

The present invention is not limited by the above-described embodiments and accompanying drawings, but is intended to be limited by the appended claims. Therefore, various forms of substitution, modification, and change will be possible by those skilled in the art within the scope of the technical spirit of the present invention described in the claims, which also falls within the scope of the present invention. something to do.

10: semiconductor device 11: chip regions
12: partition area 100: test element group (TEG)
101: substrate 105: active area
110: element isolation layer 140: channel layer
150: source/drain region 160: gate structure
181: first interlayer insulating layer 182: second interlayer insulating layer
183 third interlayer insulating layer 191 source/drain contact plug
192 gate contact plug 193 upper contact plug

Claims (10)

an active region extending in a first direction on the substrate;
gate structures extending in a second direction crossing the active region on the substrate;
first gate contact plugs disposed on the gate structures and contacting gate electrode layers of each of the gate structures;
source/drain regions disposed on the active region on at least one side of the gate structures; and
including source/drain contact plugs disposed on each of the source/drain regions and electrically connected to each of the source/drain regions;
The first gate contact plug is spaced apart from the source/drain contact plugs in the second direction and extends in the first direction.
group of test elements.
According to claim 1,
Further comprising second gate contact plugs;
The second gate contact plugs are spaced apart from the first gate contact plug in the second direction, and are disposed on the gate structures to contact gate electrode layers of the gate structures.
According to claim 2,
The second gate contact plugs are disposed between adjacent source/drain contact plugs.
According to claim 2,
A plurality of second gate contact plugs are disposed on each of the gate structures.
According to claim 1,
An upper surface of the source/drain contact plug is disposed at a level higher than a lower surface of the gate contact plug.
an active region extending in a first direction on the substrate;
A first portion on the substrate extending in a second direction crossing the active region, and spaced apart from the first portion in the second direction on the substrate, facing the first portion and extending in the second direction. gate structures each including a second portion;
a source/drain region disposed on the active region between the first portions of adjacent gate structures;
a source/drain contact plug including a portion disposed on the source/drain region, electrically connected to the source/drain region, and extending in the second direction and disposed between the second portions of adjacent gate structures. ; and
a gate contact plug disposed on the source/drain contact plug and the second portions of the gate structures and contacting gate electrode layers of the second portions of each of the gate structures;
group of test elements.
According to claim 6,
The active region is limited by a device isolation layer,
The test device group of claim 1, wherein the gate contact plug is disposed on the device isolation layer.
According to claim 6,
and an insulating layer covering upper surfaces of the gate contact plug and the source/drain contact plug.
an integrated circuit area where transistors are disposed; and
A dummy area adjacent to the integrated circuit area and in which a plurality of test element groups are disposed;
Each of the plurality of test element groups,
gate structures extending in a second direction crossing the active region extending in a first direction on the substrate; and
A gate contact plug disposed on the gate structures, contacting gate electrode layers of each of the gate structures, and extending in the first direction, and including a pad region to which an electrical signal is applied.
semiconductor device.
According to claim 9,
Each of the plurality of test element groups further includes an insulating layer covering upper surfaces of the gate structures and the pad region.

Images