CN100435308C - Improved semiconductor wafer structure and its producing method - Google Patents
Improved semiconductor wafer structure and its producing method Download PDFInfo
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- CN100435308C CN100435308C CNB2005101119714A CN200510111971A CN100435308C CN 100435308 C CN100435308 C CN 100435308C CN B2005101119714 A CNB2005101119714 A CN B2005101119714A CN 200510111971 A CN200510111971 A CN 200510111971A CN 100435308 C CN100435308 C CN 100435308C
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Abstract
This invention discloses a semiconductor chip, including : semiconductor substrate; the plural trench formed on the substrate surface; the isolation layer covering the substrate surface trench; and the first hole array and the second hole array formed on the isolation layer and corresponding to the trench. The invention also discloses correspondingly a semiconductor chip production method, including: providing a semiconductor substrate; the plural trench formed on the substrate; the isolation layer deposited on the substrate surface using CVD technology to fill and cover the trench; etching the first hole array and the second hole array on the isolation layer and corresponding to the trench; on the first hole array, etching the groove of through-hole; depositing the metal layer on the isolation layer surface; using CMP technology to remove the said metal layer until exposing the first and the second hole array. The invention can use electronic beam scanning to detect the trench gap in time, so that the failure can be early detected, and reduce defective rate and lower manufacturing costs.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly a kind of semiconductor wafer and the manufacture method thereof that can find the insulating barrier internal voids in advance.
Background technology
Along with the develop rapidly of semiconductor fabrication, semiconductor device has had the deep-submicron structure, and surface of silicon comprises the huge span of quantity less than 0.2 micron groove and fin among the semiconductor integrated circuit IC.In metal-oxide semiconductor (MOS) (MOS) circuit, fin is used to form polysilicon gate, and groove is used for forming separator between grid.Utilize chemical vapor deposition CVD or plasma-reinforced chemical vapor deposition pecvd process at the surface of silicon deposition insulating layer, as the separator between the first metal layer of polysilicon gate and MOS transistor.Because this separator generally deposits before any levels of metal in multistage metal structure, therefore it is called (PMD) layer of preceding metal and dielectric (premetal-dielectric).For PMD, importantly have good evenness and trench fill ability.For the sub-micron semiconductor device, the high density dynamic random access memory (DRAM) or the logical storage that for example have groove, wherein the groove narrower and aspect ratio ratio of width (groove height with) higher (about more than 6: 1) that becomes generally uses boron phosphorus silicate glass (BPSG) as the insulating barrier packing material at present.Deposit boron phosphorus silicate glass on substrate is so that form in the technical process of separator, need accurately parameter and flow rate of reactive gas such as control temperature, pressure, deposit power, if therefore process conditions control is improper, for example underlayer temperature is crossed low or sputtering deposit than improper probably can not the complete filling groove when boron phosphorus silicate glass refluxes, thereby in groove, form space (Void).
Figure 1A is for existing the vertical view of the chip structure in space in the deposit separator on the grid structure of Semiconductor substrate.Figure 1B be among Figure 1A A-A to transverse cross-sectional view.Shown in Figure 1A and Figure 1B, be formed with grid structure 110 and groove 120 on silicon substrate 100 surfaces, utilization utilizes chemical vapor deposition CVD or plasma-reinforced chemical vapor deposition pecvd process deposit BPSG separator 200 in the groove 120 on silicon substrate 100 surfaces, thereby covers the grid structure 110 and the groove 120 on silicon substrate 100 surfaces.The grid structure 110 on extensive CMOS integrated circuit such as the dynamic ram chip and the quantity of groove 120 are normally very huge.Groove 120 has higher aspect ratio, if process conditions control is improper in the process of deposit and backflow, will form space 210 in the separator 200 of filling in groove 120.
In ensuing processing step, further on separator 200, form interconnection structure.Fig. 2 A-Fig. 2 C is the schematic diagram of the interconnection structure that forms on the chip separator in the prior art.Fig. 2 A is the vertical view of the interconnection structure that forms on the chip separator in the prior art.Fig. 2 B be among Fig. 2 A A-A to transverse cross-sectional view.Fig. 2 C be among Fig. 2 A B-B to longitudinal sectional drawing.Shown in Fig. 2 A, Fig. 2 B and Fig. 2 C, be included in the numerous hole 230 that etches on the groove 120 at the interconnection structure that forms on the chip separator, hole 230 is by vertical etching and through substrate 100 surfaces of the degree of depth, and the groove 220 of horizontal through hole 230.Laterally the groove 220,220 of through hole 230 ' with 220 " parallel side by side each other, hole 230,230 ' and 230 " each interval forms interconnection graph on separator.Suppose in groove 120, to have formed space 210, and space 210 just be positioned at groove 220 ' and 220 " two holes 230 ' and 230 " between.
In ensuing processing step, deposited metal 300 on separator 200 with interconnection graph.Fig. 3 A to Fig. 3 C is the schematic diagram after deposited metal 300 on the separator 200 with interconnection graph, specifically, Fig. 3 A is the vertical view after deposited metal 300 on the separator 220 with interconnection graph, Fig. 3 B be the A-A of Fig. 3 A to horizontal profile, Fig. 3 C be among Fig. 3 A B-B to longitudinal sectional drawing.Shown in Fig. 3 A, Fig. 3 B and Fig. 3 C, on separator 200 after the deposited metal 300 with interconnection graph, hole 230,230 ' and 230 " in deposit metal level 300 form plated-through holes, groove 220,220 ' and 220 " in deposit metal level 300 form interconnecting lines.And, hole 230 ' and 230 " between space 210 in the also deposit metal of having entered.Therefore, by Fig. 3 C as can be seen, metal aperture 230 ' and 230 " between owing to the existence in space 210 has formed short circuit.
In ensuing processing step, utilize CMP technology that metal level 300 is worn until exposing the interconnection graph layer.Fig. 4 A to Fig. 4 C be utilize CMP technology with metal level 300 schematic diagram after worn.Fig. 4 A is the vertical view of the separator after worn with metal level 300; Fig. 4 B be the A-A of Fig. 4 A to horizontal profile, Fig. 4 C be among Fig. 4 A B-B to longitudinal sectional drawing.Shown in Fig. 4 A, Fig. 4 B and Fig. 4 C, utilize CMP technology that metal level 300 is worn, the interconnection graph of forming with the lead-in wire 220 of horizontal through hole 230 until the hole 230 of having exposed by deposit metal level.By Fig. 4 A and Fig. 4 C as can be seen because the existence in space 210, the hole 230 after the metallization ' and 230 " between space 210 in metals deposited cause going between 220 ' and 220 " between form short circuit.
In the prior art, the inspection of above-mentioned short-circuit conditions is to proceed steps such as subsequent technique such as mask, photoetching, deposit and etching so that after forming multilayer interconnection circuit chip structure, adopts electromotive force method of comparison (voltage contrast) to carry out.Fig. 5 is the schematic diagram that the employing voltage comparison method of prior art is checked short circuit.As shown in Figure 5, the lead-in wire 220 ' and 220 " between apply a voltage V, judge whether the existence in space by the variation of monitoring current.If there is space 210, go between 220 so ' and 220 " between electric current will surpass normal value.If accurately locate the position in space 210, need wait until that entire wafer finishes fully, the general area of utilizing the project analysis method to find this space to exist is then cut off the lead-in wire between each aperture one by one, finds the particular location of space existence with the electromotive force method of comparison.This shows that this process is quite loaded down with trivial details and efficient that check is very low.And this electromotive force method of comparison must form in whole wafer interconnect structure and carry out after finishing, in a single day find the short circuit that cause in the space this moment, and entire wafer just need be scrapped.Trace it to its cause be because the lead-in wire 220 of the interconnection structure of prior art ' and 220 " between be to determine approximate region that the space exists when the state shown in Fig. 4 A, also can't utilize electromotive force to contrast the particular location of finding out the space.Therefore, because the hysteresis that the limitation of the method for testing that the defective of the interconnection structure of above-mentioned prior art causes and space are detected can't in time be found the early failure of chip, cause the increase of defect rate and the raising of manufacturing cost.
Summary of the invention
Therefore, the interconnection structure that the purpose of this invention is to provide a kind of improved semiconductor chip, described interconnection structure can form the early stage of interconnection structure, utilize electron beam scanning in time to find the space that occurs in the separator in the groove, lost efficacy thereby reject early stage short circuit, and improved yields and reduce manufacturing cost.
For achieving the above object, the invention provides a kind of semiconductor wafer, comprising: Semiconductor substrate; A plurality of grooves in substrate surface formation; Cover the separator of substrate surface groove; And the interconnection graph that the position corresponding with groove forms on described separator; The resolution chart that forms with position corresponding with groove on described separator, arrange with the interconnection graph parallel interval.
Described interconnection graph comprises the hole of each interval and traverses the groove in described hole.
Described resolution chart comprises the hole of each interval.
The hole of described interconnection graph and resolution chart is etched out and connects the through substrate surface of groove downwards in insulation surface.
Parallel to each other and the arrangement correspondingly in the hole of described interconnection graph and resolution chart.
In the groove of described interconnection graph and hole and in the hole of resolution chart, be filled with metal material.
Described interconnection graph is included in the multilayer interconnect structure of wafer microcircuit.
Described resolution chart is the beam bombardment test zone.
Correspondingly, the invention provides a kind of production method of semiconductor wafer, comprising: semi-conductive substrate is provided; On substrate, form a plurality of grooves; Utilize chemical vapor deposition (CVD) technology at substrate surface deposit separator so that fill and covering groove; Position etching first hole array and the second hole array corresponding on separator with groove; On the first hole array, etch the groove of transversal openings; In the insulation surface deposited metal; Utilizing cmp (CMP) technology to remove described metal level isolates between the first empty array and the second hole array and second each hole of hole array fully; Utilize electron beam scanning to bombard the first hole array and the second hole array; If the color in the hole, array somewhere, second hole that discovery is bombarded is different with the color in other hole, illustrate that then there is the space in the below in hole, described somewhere; Otherwise proceed ensuing processing step.
The hole of the described first hole array and the second hole array is etched out on separator and connects the through substrate surface of groove downwards.
Each row hole arrangement spaced in parallel to each other of each the row hole of described first hole matrix and the second hole array.
Parallel to each other and the arrangement correspondingly in the hole of the described first hole array and the second hole array.
The described first hole array is included in the multilayer interconnect structure of wafer microcircuit.
The described second hole array is the beam bombardment test zone.
Compared with prior art, the present invention has the following advantages:
Chip interconnection structure of the present invention is owing to the interconnection graph of the groove of hole that comprises each interval of having adopted position corresponding with groove on the separator of substrate to form and transversal openings, the alternately resolution chart in hole that arrange, that comprise each interval that form with the position corresponding with groove, parallel with interconnection array, its mesopore is etched out and connects the groove substrate surface that goes directly downwards in insulation surface.Because the hole of interconnection graph and resolution chart is parallel to each other and arrangement correspondingly, the groove of interconnection graph forms the plated-through hole array that lead-in wire is connected with the hole, is filled with metal material in the hole of resolution chart and forms corresponding and independent of each other plated-through hole with the hole of interconnection graph.This structure makes and proceeds to this moment at processing step, just can utilize electron beam scanning in time to find to be deposited on the space that exists in the interior separator of groove.
In the groove of electron bombard interconnection graph and hole and during the hole of resolution chart, if below the hole of interconnection graph hole and resolution chart, have the space, just there is the situation of short circuit to take place, so in resolution chart, thereby since electronics on hole independently aggregation extent and below have the aggregation extent on the hole of space and the hole short circuit of interconnection graph different, so the change color in the hole of the resolution chart that can be scanned by judgement is located the space.This space localization method that is based upon on the chip structure of the present invention basis has improved testing efficiency greatly, if being arranged, the space cause the phenomenon of short circuit just can in time analyze, and then repair the step that causes fault to produce, needn't form multilayer interconnect structure by the time and afterwards again chip be carried out the space check and analysis.Therefore the present invention can in time pinpoint the problems, and has striven for for dealing with problems the time having reduced defect rate, and then has reduced manufacturing cost.
Description of drawings
Figure 1A is for existing the vertical view of the chip structure in space in the deposit separator on the grid structure of Semiconductor substrate;
Figure 1B be among Figure 1A A-A to transverse cross-sectional view;
Fig. 2 A is the vertical view of the interconnection structure that forms on the chip separator in the prior art;
Fig. 2 B be among Fig. 2 A A-A to transverse cross-sectional view;
Fig. 2 C be among Fig. 2 A B-B to longitudinal sectional drawing;
Fig. 3 A is the vertical view after deposited metal 300 on the separator 220 with interconnection graph;
Fig. 3 B is that the A-A of Fig. 3 A is to horizontal profile;
Fig. 3 C be among Fig. 3 A B-B to longitudinal sectional drawing;
Fig. 4 A is the vertical view of the separator after worn with metal level 300;
Fig. 4 B is that the A-A of Fig. 4 A is to horizontal profile;
Fig. 4 C be among Fig. 4 A B-B to longitudinal sectional drawing;
Fig. 5 is the schematic diagram that the employing voltage comparison method of prior art is checked short circuit;
Fig. 6 A is for existing the vertical view of the chip structure in space in the deposit separator on the grid structure of Semiconductor substrate;
Fig. 6 B be among Fig. 6 A A-A to transverse cross-sectional view;
Fig. 7 A is the vertical view that forms interconnection graph and resolution chart on the separator of semiconductor chip structure of the present invention;
Fig. 7 B be among Fig. 7 A A-A to transverse cross-sectional view;
Fig. 7 C be among Fig. 7 A B-B to longitudinal sectional drawing;
Fig. 8 A is the vertical view of semiconductor wafer of the present invention after deposited metal 300 on the separator 220 with interconnection graph;
Fig. 8 B is that the A-A of Fig. 8 A is to horizontal profile;
Fig. 8 C be among Fig. 8 A B-B to longitudinal sectional drawing;
Fig. 9 A is the vertical view that semiconductor chip structure of the present invention utilizes CMP technology separator after worn with metal level 300;
Fig. 9 B is that the A-A of Fig. 9 A is to horizontal profile;
Fig. 9 C be among Fig. 9 A B-B to longitudinal sectional drawing;
Figure 10 A is the vertical view of semiconductor chip structure of the present invention;
Figure 10 B be among Figure 10 A A-A to transverse cross-sectional view;
Figure 11 is the schematic diagram that utilizes space in the semiconductor wafer separator of the present invention of electron beam scanning location.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated.
Figure 10 A and Figure 10 B are semiconductor chip structure schematic diagram of the present invention.Figure 10 A is the vertical view of semiconductor chip structure of the present invention, Figure 10 B be among Figure 10 A A-A to transverse cross-sectional view, shown in Figure 10 A and Figure 10 B, semiconductor wafer of the present invention comprises Semiconductor substrate 100 and a plurality of grids 110 and the groove 120 that form on substrate 100 surfaces; Cover the separator 200 of substrate surface groove 120; And the interconnection graph that the position corresponding with groove 120 forms on separator 200; The resolution chart that forms with position corresponding with groove 120 on separator 200, arrange with the interconnection graph parallel interval.Interconnection graph comprise by numerous plated-through holes 230,230 ' and 230 " the first hole array of forming and respectively the numerous plated-through holes 230,230 of lateral direction penetrating ' and 230 " metallic leads 220,220 ' and 220 ".Resolution chart is made up of the second hole array of plated-through hole 240,240 numerous, independent of each other ' constitute.The hole 230,230 of interconnection graph and resolution chart ' and 230 " and 240,240 ' be etched out on separator 200 surfaces and connect groove 120 through substrate 100 surfaces downwards, and the hole of the hole of interconnection graph and resolution chart is parallel to each other and arrange correspondingly.Interconnection graph is included in the multilayer interconnect structure of wafer microcircuit, and resolution chart is the beam bombardment test zone.
The manufacture method of semiconductor chip structure of the present invention is described below, and there is the space that causes short circuit in hypothesis in the separator of semiconductor wafer of the present invention.
In the MOS circuit, have polysilicon gate on the substrate usually and between grid, be used to form the groove of separator.Utilize chemical vapor deposition CVD or plasma-reinforced chemical vapor deposition pecvd process at the surface of silicon deposition insulating layer as the separator between grid and the MOS transistor the first metal layer.For the sub-micron semiconductor device, groove become narrower and also aspect ratio higher, adopt boron phosphorus silicate glass (BPSG) as the separator packing material in an embodiment of the present invention.Deposit boron phosphorus silicate glass on substrate is so that form in the technical process of separator, need accurately parameter and flow rate of reactive gas such as control temperature, pressure, deposit power, if process conditions control is improper, then can be when boron phosphorus silicate glass refluxes can not the complete filling groove, thereby in groove, form the space.
The object of the present invention is to provide a kind of interconnection structure of improved semiconductor chip, described interconnection structure can be found the space that occurs in the separator in the groove in advance.Fig. 6 A and Fig. 6 B are for existing the schematic diagram in space in the deposit separator on the grid structure of Semiconductor substrate.Fig. 6 A is for existing the vertical view of the chip structure in space in the deposit separator on the grid structure of Semiconductor substrate.Fig. 6 B be among Fig. 6 A A-A to transverse cross-sectional view.Shown in Fig. 6 A and Fig. 6 B, be formed with grid structure 110 and groove 120 on silicon substrate 100 surfaces, utilization utilizes chemical vapor deposition CVD or plasma-reinforced chemical vapor deposition pecvd process deposit BPSG separator 200 in the groove 120 on silicon substrate 100 surfaces, thereby covers the grid structure 110 and the groove 120 on silicon substrate 100 surfaces.Groove 120 has higher aspect ratio, if process conditions control is improper in the process of deposit and backflow, will form space 210 in the separator 200 of filling in groove 120.
In ensuing processing step, on separator 200, form interconnection graph and resolution chart.Fig. 7 A-Fig. 7 C is the schematic diagram that forms interconnection graph and resolution chart on the separator of semiconductor chip structure of the present invention.Fig. 7 A is the vertical view that forms interconnection graph and resolution chart on the separator of semiconductor chip structure of the present invention.Fig. 7 B be among Fig. 7 A A-A to transverse cross-sectional view.Fig. 7 C be among Fig. 7 A B-B to longitudinal sectional drawing.Shown in Fig. 7 A, Fig. 7 B and Fig. 7 C, the interconnection graph that the position corresponding with groove 120 forms on chip separator 200 comprise numerous hole 230,230 of each interval ' and 230 " and laterally through hole 230,230 ' and 230 " groove 220,220 ' and 220 ".Position corresponding with groove 120 on separator 200 forms resolution chart, resolution chart comprise numerous hole 240,240 of each interval ', and the parallel alternately arrangement with interconnection graph of resolution chart is shown in Fig. 7 A.The hole 230,230 of interconnection graph and resolution chart ' and 230 " and 240,240 ' be etched out on separator 200 surfaces and connect groove 120 through substrate 100 surfaces downwards, and the hole 240 of the hole 230 of interconnection graph and resolution chart is parallel to each other and arrange correspondingly.In groove 120, formed space 210, and space 210 be positioned at the groove 220 of interconnection graph ' and the hole 240 of 220 " two holes 230 ' and 230 " and resolution chart ' between, lateral direction penetrating hole 230 ', 230 " and 240 ', shown in Fig. 7 C.
Then, deposited metal 300 on separator 200 with interconnection graph.Fig. 8 A to Fig. 8 C is the structural representation of semiconductor wafer of the present invention after deposited metal 300 on the separator 200 with interconnection graph and resolution chart.Fig. 8 A is the vertical view of semiconductor wafer of the present invention after deposited metal 300 on the separator 220 with interconnection graph, Fig. 8 B be the A-A of Fig. 8 A to horizontal profile, Fig. 8 C be among Fig. 8 A B-B to longitudinal sectional drawing.Shown in Fig. 8 A, Fig. 8 B and Fig. 8 C, on separator 200 after the deposited metal 300 with interconnection graph and resolution chart, in the hole 230,230 of interconnection graph ', 230 " thereby and the hole 240,240 of resolution chart ' middle deposited metal 300 form plated-through holes, the groove 220,220 of interconnection graph ' and 220 " in deposit metal level 300 form interconnecting lines.And, metal aperture 230 ', 240 ' and 230 " between space 210 in also deposit advanced metal.Therefore, by Fig. 8 C as can be seen, metal aperture 230 ', 240 ' and 230 " between owing to the existence in space 210 has formed short circuit.
In ensuing processing step, utilize CMP technology that metal level 300 is worn until exposing interconnection graph and resolution chart, and isolate fully between interconnection graph and resolution chart and each hole of resolution chart.Fig. 9 A to Fig. 9 C be semiconductor chip structure of the present invention utilize CMP technology with metal level 300 schematic diagram after worn.Fig. 9 A is the vertical view that semiconductor chip structure of the present invention utilizes CMP technology separator after worn with metal level 300; Fig. 9 B be the A-A of Fig. 9 A to horizontal profile, Fig. 9 C be among Fig. 9 A B-B to longitudinal sectional drawing.Shown in Fig. 9 A, Fig. 9 B and Fig. 9 C, utilize CMP technology, metal level 300 is worn, until interconnection graph that exposes deposited metal and resolution chart, and isolate fully between interconnection graph and resolution chart and each hole of resolution chart.The interconnection graph of this moment comprises lateral direction penetrating plated-through hole 230,230 respectively ' and 230 " metallization interconnect lead-in wire 520,520 ' and 520 ".The hole array that the resolution chart of this moment is made up of plated-through hole 240 numerous, independent of each other.If do not have the space to exist then proceed ensuing processing step this moment.In groove 120, formed under the situation in space 210, by Figure 10 A and Figure 10 C as can be seen, in the space 210 deposit after the metal, cross connection the hole 230 after the metallization ', 240 ' and 230 ", thereby cause metallic leads 220 ' and 220 " between short circuit.
Figure 11 is the schematic diagram that utilizes the space in the separator of electron beam scanning semiconductor wafer of the present invention location.As shown in figure 11, chip architecture of the present invention has been arranged interconnection graph and resolution chart on separator.Interconnection graph comprises metallic leads and numerous plated-through holes, and metallic leads laterally runs through numerous plated-through holes.The hole array that resolution chart is made up of numerous plated-through holes.The plated-through hole of interconnection graph and the plated-through hole of resolution chart are etched out in separator 200 surface and groove 120 corresponding positions and connect the groove substrate surface that goes directly downwards.The plated-through hole each interval of resolution chart, and parallel to each other and arrangement correspondingly with the hole of interconnection graph.Have space 210 in the groove of separator 200, it has formed a metal space owing in the space 210, thereby has caused metallic leads 410 and metallic leads 420 short circuits between plated-through hole 411,412 and 413 when depositing metal.
With electron beam scanning interconnection graph and resolution chart, if below the hole of interconnection graph hole and resolution chart, have the space, just there is the situation of short circuit to take place, so when electron bombard to the metallic leads 410 with space and 420 and during the plated-through hole of middle resolution chart, the electronics that bombards on the plated-through hole 412 can scatter along metallic leads 410 and 420, and the electronics that bombards on the plated-through hole of the resolution chart that does not have the space below it can accumulate on the plated-through hole, and the color of observing plated-through hole 412 and on every side plated-through hole on chromatograph is different.Therefore, with electron beam scanning interconnection graph and resolution chart, just can locate the space by the change color of observing plated-through hole.
Be based upon the method in the space, this electron beam scanning location on the chip structure of the present invention basis, early stage in technical process, just can carry out the inspection in space in the separator after just having ground off the ground floor metal interconnecting layer, not only improved testing efficiency, and can find in time that the space causes the situation of short circuit, thereby in time reject failure chip, needn't form multilayer interconnect structure by the time and again chip be carried out the space detection afterwards.Therefore the present invention has striven for for dealing with problems the time having reduced defect rate, has reduced manufacturing cost.
Though oneself discloses the present invention as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (19)
1, a kind of semiconductor wafer comprises:
Semiconductor substrate;
At a plurality of grooves that substrate surface forms, described a plurality of grooves are parallel to each other;
Cover the separator of substrate surface groove; And
The position corresponding with groove forms in described separator the first hole array and the second hole array, each hole of the described second hole array isolates mutually, each row hole of each the row hole of the described first hole array and the second hole array is alternately arranged with each other, the hole of the described first hole array and the second hole array is etched out in separator and connects the through substrate surface of groove downwards, the described first hole array has the groove that traverses each row hole, be filled with metal material in the groove of the described first hole array and the hole and in the hole of the second hole array, each row hole of each the row hole of the described first hole array and the second hole array distributes along the direction vertical with groove, and each row hole of each the row hole of the described first hole array and the second hole array isolates fully.
2, semiconductor wafer as claimed in claim 1 is characterized in that: the parallel to each other and alternately arrangement in each row hole of each the row hole of the described first hole array and the second hole array.
3, semiconductor wafer as claimed in claim 2 is characterized in that: the parallel to each other and arrangement correspondingly in the hole of the described first hole array and the second hole array.
4, semiconductor wafer as claimed in claim 3 is characterized in that: the described first hole array is included in the multilayer interconnect structure of wafer microcircuit.
5, semiconductor wafer as claimed in claim 3 is characterized in that: the described second hole array is the beam bombardment test zone.
6, a kind of production method of semiconductor wafer comprises:
Semi-conductive substrate is provided;
Form a plurality of grooves on substrate, described a plurality of grooves are parallel to each other;
Utilize chemical vapor deposition method at substrate surface deposit separator so that fill and covering groove;
Position etching first hole array and the second hole array corresponding in separator with groove, the hole of the described first hole array and the second hole array is etched out in separator and connects the through substrate surface of groove downwards, each row hole of each the row hole of the described first hole array and the second hole array is alternately arranged with each other, and each row hole of each the row hole of the described first hole array and the second hole array distributes along the direction vertical with groove;
On the first hole array, etch the groove that traverses each row hole;
In the insulation surface deposited metal, fill each row hole of the described first hole array, each row hole of the second hole array and the groove that traverses each row hole of the first hole array;
Utilizing chemical mechanical milling tech to remove described metal level isolates between the first hole array and the second hole array and second each hole of hole array fully.
7, the production method of semiconductor wafer as claimed in claim 6 is characterized in that: the parallel to each other and alternately arrangement in each row hole of each the row hole of the described first hole array and the second hole array.
8, the production method of semiconductor wafer as claimed in claim 7 is characterized in that: the parallel to each other and arrangement correspondingly in the hole of the described first hole array and the second hole array.
9, the production method of semiconductor wafer as claimed in claim 8 is characterized in that: the described first hole array is included in the multilayer interconnect structure of wafer microcircuit.
10, the production method of semiconductor wafer as claimed in claim 8 is characterized in that: the described second hole array is the beam bombardment test zone.
11, a kind of production method of semiconductor wafer comprises:
Semi-conductive substrate is provided;
Form a plurality of grooves on substrate, described a plurality of grooves are parallel to each other;
Utilize chemical vapor deposition method at substrate surface deposit separator so that fill and covering groove;
Position etching first hole array and the second hole array corresponding in separator with groove, the hole of the described first hole array and the second hole array is etched out on separator and connects the through substrate surface of groove downwards, each row hole of each the row hole of the described first hole array and the second hole array is alternately arranged with each other, and each row hole of each the row hole of the described first hole array and the second hole array distributes along the direction vertical with groove;
On the first hole array, etch the groove that traverses each row hole;
In the insulation surface deposited metal;
Utilizing chemical mechanical milling tech to remove described metal level isolates between the first hole array and the second hole array and second each hole of hole array fully;
Utilize electron beam scanning to bombard the first hole array and the second hole array;
When finding that chromatograph shows that the color in the hole of being bombarded, array somewhere, second hole is different with the color in other hole of array, second hole, illustrates that then there is the space in the below in hole, described somewhere; When finding that chromatograph shows that the color in the hole of being bombarded, array somewhere, second hole is identical with the color in other hole of array, second hole, then,
Proceed ensuing processing step.
12, the production method of semiconductor wafer as claimed in claim 11 is characterized in that: the parallel to each other and alternately arrangement in each row hole of each the row hole of the described first hole array and the second hole array.
13, the production method of semiconductor wafer as claimed in claim 12 is characterized in that: the parallel to each other and arrangement correspondingly in the hole of the described first hole array and the second hole array.
14, the production method of semiconductor wafer as claimed in claim 13 is characterized in that: the described first hole array is included in the multilayer interconnect structure of wafer microcircuit.
15, the production method of semiconductor wafer as claimed in claim 13 is characterized in that: the described second hole array is the beam bombardment test zone.
16, a kind of semiconductor wafer comprises:
Semiconductor substrate;
At a plurality of grooves that substrate surface forms, described a plurality of grooves are parallel to each other;
Cover the separator of substrate surface groove; And
The interconnection graph that the position corresponding with groove forms in described separator, described interconnection graph comprise the hole that isolates each other and traverse the groove in each row hole; With
The resolution chart that the position corresponding with groove forms in described separator, described resolution chart comprises the hole that isolates each other, each row hole of described resolution chart is listed as the parallel and alternately arrangement in hole with each of interconnection graph, each row hole of each row hole of described interconnection graph and resolution chart distributes along the direction vertical with groove, each row hole of each row hole of described interconnection graph and resolution chart isolates fully, the hole of described interconnection graph and resolution chart is etched out and connects the through substrate surface of groove downwards in insulation surface, is filled with metal material in the groove of described interconnection graph and hole and in the hole of resolution chart.
17, semiconductor wafer as claimed in claim 16 is characterized in that: the parallel to each other and arrangement correspondingly in the hole of described interconnection graph and resolution chart.
18, semiconductor wafer as claimed in claim 17 is characterized in that: described interconnection graph is included in the multilayer interconnect structure of wafer microcircuit.
19, semiconductor wafer as claimed in claim 17 is characterized in that: described resolution chart is the beam bombardment test zone.
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| CN104091769B (en) * | 2014-07-25 | 2017-03-01 | 上海华力微电子有限公司 | A kind of not enough detection method of via etch |
| CN110473799B (en) * | 2019-09-09 | 2021-04-30 | 上海华力微电子有限公司 | Method for detecting hole defects in shallow trench isolation structure |
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|---|---|---|---|---|
| JP2000216210A (en) * | 1999-01-27 | 2000-08-04 | Matsushita Electronics Industry Corp | Method and structure for evaluation of level embedding in insulating film |
| US6828239B2 (en) * | 2002-01-25 | 2004-12-07 | Nanya Technology Corporation | Method of forming a high aspect ratio shallow trench isolation |
| US20050026376A1 (en) * | 2003-07-31 | 2005-02-03 | Kim Jae Young | Methods for forming shallow trench isolation |
| JP2005064360A (en) * | 2003-08-19 | 2005-03-10 | Renesas Technology Corp | Evaluation apparatus and method for semiconductor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000216210A (en) * | 1999-01-27 | 2000-08-04 | Matsushita Electronics Industry Corp | Method and structure for evaluation of level embedding in insulating film |
| US6828239B2 (en) * | 2002-01-25 | 2004-12-07 | Nanya Technology Corporation | Method of forming a high aspect ratio shallow trench isolation |
| US20050026376A1 (en) * | 2003-07-31 | 2005-02-03 | Kim Jae Young | Methods for forming shallow trench isolation |
| JP2005064360A (en) * | 2003-08-19 | 2005-03-10 | Renesas Technology Corp | Evaluation apparatus and method for semiconductor |
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