CN101651095B - Method for manufacturing gate structure - Google Patents
Method for manufacturing gate structure Download PDFInfo
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- CN101651095B CN101651095B CN2008101184030A CN200810118403A CN101651095B CN 101651095 B CN101651095 B CN 101651095B CN 2008101184030 A CN2008101184030 A CN 2008101184030A CN 200810118403 A CN200810118403 A CN 200810118403A CN 101651095 B CN101651095 B CN 101651095B
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- metaphosphoric acid
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Abstract
The invention provides a method for manufacturing a gate structure. The method comprises the following steps of: providing a semiconductor substrate provided with a phosphorus doped polysilicon layer; using a solvent capable of dissolving metaphosphoric acid to wash the polysilicon layer; forming a layer or multi-layers of stacks on the polysilicon layer; and etching the composite layer on the semiconductor substrate to form the gate structure. By using the solvent capable of dissolving metaphosphoric acid to wash the polysilicon layer, the metaphosphoric acid generated on the surface of the polysilicon layer can be removed, the gate structure deformation which is caused by the metaphosphoric acid can be avoided, and furthermore the problem of transistor electric leakage caused by the deformation of the gate structure, can be solved.
Description
Technical field
The application relates to field of semiconductor manufacture, relates in particular to a kind of manufacturing approach of grid structure.
Background technology
Along with the continuous development of integrated circuit technique, electronic product more and more develops to miniaturization, intellectuality, high-performance and high reliability direction.For economy and the efficient that improves storage element, (Dynamic Random-Access Memory, integrated level DRAM) is also high more and more more as the dynamic random access memory of memory.
The DRAM storage element be by metal oxide semiconductor transistor (Metal OxideSemiconductor, MOS) and series capacitor constituted.MOS transistor includes a grid and corresponding two doped regions.Two doped region visual functions are defined as source electrode and drain electrode.
Grid in the typical DRAM storage element generally is the structure that is designed to have stacking-type.Wherein, be included in one deck oxide dielectric layers on the Semiconductor substrate, one deck polysilicon layer on oxide dielectric layers, one deck silicon nitride dielectric layer on polysilicon layer.
One Chinese patent application has openly had the manufacturing approach of above-mentioned typical gates structure for No. 98804946.5, comprises step: cvd silicon oxide dielectric layer on silicon substrate; Deposit spathic silicon layer on the silicon oxide dielectric layer; Deposited silicon nitride layer forms the multilayer stack layer on polysilicon layer; The patterned multilevel stack layer defines the position of grid.
And in order to reduce the resistance of polysilicon layer, those skilled in the art can carry out phosphonium ion usually and mix in polysilicon layer.
And along with the development gradually of ultra-large type integrated circuit, the design size of device is constantly dwindled, thereby in the manufacturing process of grid, small flaw all may cause the inefficacy of entire device.The situation that also can occur component failure with the grid of existing processes manufacturing DRAM.Certainly, the manufacturing of grid is not limited to the DRAM storage element, in other semiconductor device, can relate to the manufacturing process of grid equally.
Summary of the invention
The application's technical problem to be solved is: how to avoid the semiconductor device failure that causes because of the grid flaw.
For solving the problems of the technologies described above, the application provides a kind of manufacturing approach of grid structure, it is characterized in that, comprises step: Semiconductor substrate is provided, has the polysilicon layer of phosphorus doping on the said Semiconductor substrate; With the said polysilicon layer of the solvent clean of solubilized metaphosphoric acid; On polysilicon layer, form one or more layers storehouse; Composite bed on the etching semiconductor substrate forms grid structure.
Alternatively, said solvent comprises vitriolated solvent or basic solvent.
Alternatively, also comprise hydrogen peroxide in the said vitriolated solvent.
Alternatively, in the said vitriolated solvent, the volume ratio of sulfuric acid and hydrogen peroxide is 1: 5 to 1: 7.
Alternatively, the volume ratio of said sulfuric acid and hydrogen peroxide is 1: 6.
Alternatively, the temperature of said vitriolated solvent is 100 ℃～150 ℃.
Alternatively, the temperature of said vitriolated solvent is 120 ℃～130 ℃.
Alternatively, the time of cleaning is 3 minutes to 15 minutes.
Alternatively, described cleaning is carried out at twice, cleans 4-6 minute at every turn.
Alternatively, also comprise silica on the wash-out polysilicon layer.
Alternatively, after step, also comprise deposit tungsten suicide layers on the polysilicon layer that cleaned with the said polysilicon layer of solvent clean of solubilized metaphosphoric acid.
By the polysilicon layer of phosphorus doping, can remove the metaphosphoric acid that the polysilicon layer surface produces with the solvent clean of solubilized metaphosphoric acid, prevent the grid structure distortion that metaphosphoric acid causes, and then solve consequent transistor leakage problem.The application increases the step with the solvent clean polysilicon layer of solubilized metaphosphoric acid in the process of manufacturing grid, with the problem that solves transistor leakage, to those skilled in the art, its effect is beyond thought.
Description of drawings
The transistor drain current situation of Fig. 1 on the wafer yardstick, finding among the embodiment of the application's grid production method;
Fig. 2 is the SEM photo of grid fault location among another embodiment of the application's grid production method;
Fig. 3 is for carrying out the result that defective scans to wafer among the embodiment of the application's grid production method;
Fig. 4 is the SEM photo of a defective among Fig. 3;
Fig. 5 is along the sectional drawing of A-A ' among Fig. 4;
Fig. 6 is the EDX results of elemental analyses of part in Fig. 5 centre circle;
Fig. 7 is the flow chart of an embodiment of the application's grid production method;
Fig. 8 cleans and the contrast of not carrying out existing defects count on the wafer that metaphosphoric acid cleans for carrying out metaphosphoric acid among the embodiment of the application's grid production method;
Fig. 9 be among the embodiment of the application's grid production method on the wafer yield of MOS transistor distribute.
Embodiment
Present embodiment provides a kind of manufacturing approach of grid, can remove the metaphosphoric acid that the polysilicon layer surface produces.Below (be word line, Word-line) be fabricated to example, the application's embodiment is elaborated with the grid of MOS transistor among the DRAM.
The present inventor finds, when making DRAM according to prior art, is easy to produce the transistor leakage phenomenon, causes the yield of product to descend.The transistor drain current situation of Fig. 1 on the wafer yardstick, finding; As shown in Figure 1, when being checked, 101,102,103,104,105,106,107 and 108 8 wafers find that the transistor yield on the wafer is uneven; Yield height to 72.95% is low to moderate 26.77%.
The present inventor also finds, utilizes in the stack structure of MOS transistor of the DRAM storage element that prior art produces, and outstanding (Footing) problem of foot can appear in the place in that polysilicon layer and tungsten silicide layer have a common boundary.Fig. 2 is the SEM photo of grid fault location.The part of from Fig. 2, irising out can be found out, outstanding 201 problems of tangible foot in a grid, occurred, and outstanding 201 position is positioned at below the stage casing of grid tangent plane.
In order to analyze the reason that the problems referred to above occur, the present inventor utilizes the defective scanning device that crystal column surface is scanned, and the result of scanning is as shown in Figure 3.In Fig. 3, the position of rhombus 301,302,303,304 marks is the grid anomalad that the defective scanning device is found.In order to keep image clear, only defective locations has been made a spot of schematic mark.
A present inventor and then a defective locations that extracts among Fig. 3 are taken the SEM photo, have obtained the SEM photo result among Fig. 4.Can find that the part 401 in Fig. 4 centre circle is compared with other positions, apparent in view form difference is arranged.
The present inventor has taken the littler SEM photo of yardstick to the A-A ' tangent plane among Fig. 4, and is as shown in Figure 5.And the position from Fig. 5 centre circle 501, promptly sample of material is extracted at the outstanding position of polysilicon and tungsten silicide intersection, and carries out elementary analysis with energy dispersion X-ray detector (EDX).The result who analyzes is as shown in Figure 6.The result who detects finds, the position 501 in Fig. 5 centre circle promptly a spot of P elements occurred in the material at the outstanding position of the foot of grid.
The present inventor thinks that the appearance of above-mentioned P elements is outstanding related with MOS transistor electric leakage existence with the foot of grid, and has carried out analysis as mentioned below.
For improving the electric conductivity of polysilicon layer, those skilled in the art are meeting Doping Phosphorus element in polysilicon usually.Therefore, the surface of polysilicon layer can occur elemental phosphorous.Phosphorus can with water and oxygen reaction, the product of reaction is different and different according to the deal of water and oxygen and reaction temperature, product comprises phosphoric acid and metaphosphoric acid etc.Phosphorus and not enough water gaging and a certain amount of oxygen react at normal temperatures and can generate metaphosphoric acid, and its reaction equation is following:
4P+2H
2O+5O
2→4HPO
3
Because wafer can not contact a large amount of water, only can contact, and be in the normal temperature state usually, so the reaction of the phosphorus in the polysilicon and water and oxygen is also followed with above-mentioned course of reaction and generated metaphosphoric acid with airborne small amount of water vapor.
Metaphosphoric acid under the normal temperature is hard and transparent glassy mass.Therefore generate the process of metaphosphoric acid in continuous reaction, what can make polysilicon and tungsten silicide constantly accumulates the metaphosphoric acid product at the interface, thereby causes grid foot distinct issues.
The acidity of metaphosphoric acid is better than phosphoric acid, and this is a known conclusion.Therefore, the present inventor infers that the metaphosphoric acid that acidity is better than phosphoric acid has produced complicated chemical reaction with polysilicon and/or tungsten silicide, the problem generation that this reaction finally causes MOS transistor to leak electricity.
The present inventor reaches a conclusion from above-mentioned analysis, and metaphosphoric acid is to produce the outstanding main cause of leaking electricity with MOS transistor of grid foot, therefore should in the technology of existing manufacturing grid, increase the step of removing metaphosphoric acid.
For this reason, the application provides a kind of manufacturing approach of grid, may further comprise the steps:
On Semiconductor substrate, form gate oxide level;
Clean gate oxide level;
On gate oxide level, form the polysilicon layer of phosphorus doping;
With the said polysilicon layer of the solvent clean of solubilized metaphosphoric acid;
Clean polysilicon layer with hydrogen fluoride, remove the silica on the polysilicon layer;
On polysilicon layer, form tungsten silicide layer;
On tungsten silicide layer, form one or more layers storehouse;
MULTILAYER COMPOSITE coating on the etching semiconductor substrate forms grid structure.
In said method, form the technology of gate oxide level, the technology that forms polysilicon layer and the technology of in polysilicon layer, mixing and can adopt technology well-known to those skilled in the art, repeat no more at this.
And clean the used solvent of gate oxide level can be saturated ammoniacal liquor (NH
3H
2O), the mixed solution of hydrogen peroxide and water, wherein saturated ammoniacal liquor can be 1: 5: 100 than hydrogen peroxide than the ratio of water.
Though metaphosphoric acid is soluble in water; But can know through aforesaid analysis; Metaphosphoric acid can generate phosphoric acid with the water reaction; If in the process of wash-out metaphosphoric acid, introduce water again, will inevitably cause continuing to generate phosphoric acid in the subsequent process, thereby need to increase special special processing step phosphoric acid is removed fully.Therefore, in the application's a embodiment, the solvent that cleans metaphosphoric acid is the mixed solution (SPM) or the basic solvent of sulfuric acid and hydrogen peroxide.
Use the reason of SPM to be; SPM is a kind of common solvent of field of semiconductor manufacture; Use SPM not only can improve SPM simultaneously but also can remove metaphosphoric acid impurity here, that is to say, use the purpose of SPM to have two here in the technology versatility of field of semiconductor manufacture.
In above-mentioned SPM, the volume ratio of sulfuric acid and hydrogen peroxide can be 1: 5 to 1: 7, but when the volume ratio of sulfuric acid and hydrogen peroxide was 1: 6, SPM was best to the solubility property of metaphosphoric acid.
Most of solvent is to the solvability of solute and the temperature positive correlation of dissolution velocity and solvent, and in this application, SPM roughly also meets above-mentioned rule to the dissolution properties of metaphosphoric acid.Therefore, in the application's a embodiment, the serviceability temperature of SPM can be 100 ℃～150 ℃.But the present inventor finds that also when the temperature of SPM was 120 ℃～130 ℃, it dissolved the fastest of metaphosphoric acid.So, in another embodiment of the application, the temperature of SPM is controlled at 120 ℃～130 ℃.
In another embodiment of the application, when the temperature with SPM is controlled at 120 ℃～130 ℃, can be 3 minutes to 15 minutes with its time of cleaning polysilicon layer, concrete example was as 5 minutes or 10 minutes.
Clean with SPM and can once accomplish also and can carry out several times.When employing was repeatedly cleaned, the relative scale of impurity and SPM was more and more littler, that is to say, the concentration of impurity in cleaning agent is more and more lower, thereby can improve cleansing power.But the increase of wash number will inevitably increase the technology cost.In the application's a embodiment, can adopt at twice and clean, the mode of at every turn cleaning 4-6 minute is carried out, to reach best cleaning performance.
Though in the above-described embodiments, hydrogen peroxide is contained in employed SPM solution the inside, dissolves the main matter or the sulfuric acid of metaphosphoric acid, and therefore, the solvent of solubilized metaphosphoric acid can be other solution that comprise sulfuric acid.
After step with the said polysilicon layer of solvent clean of solubilized metaphosphoric acid, also comprise and clean polysilicon layer with aqueous hydrogen fluoride solution, remove the step of the silica on the polysilicon layer.HF excessive concentration then reaction speed is too fast; Be unfavorable for the control of technology; The present inventor finds that in the aqueous hydrogen fluoride solution, the ratio of hydrogen fluoride and water is between 1: 50 to 1: 150; Concrete example is as under 1: 100 the condition, and the speed of reaction and the complexity of control can reach preferable balance.
When the solvent of solubilized metaphosphoric acid was SPM, the order of these two steps can not be exchanged.Because hydrogen fluoride is with removing the silica on the polysilicon layer.And SPM comprises sulfuric acid and hydrogen peroxide, has strong oxidizing property.If clean the silica on the polysilicon layer with hydrogen fluoride earlier; Clean metaphosphoric acid with SPM again; To cause the part silicon on the polysilicon layer to be oxidized into silica, see on the whole, and make hydrogen fluoride have a greatly reduced quality the cleaning performance of the silica on the polysilicon layer by SPM.When the solvent of solubilized metaphosphoric acid can not produce extra negative cleaning performance, the order of above-mentioned two steps can be exchanged.
Deposit tungsten suicide layers on the polysilicon layer that cleaned then.Here, the effect of deposit tungsten suicide layers is the resistance that reduces grid.
Next be on tungsten silicide layer, to form one or more layers storehouse, for example as the silicon nitride layer of etching barrier layer and/or protective layer or photoresist layer or the like.At this, the meaning of storehouse is the composite coating of multilayer, and tungsten silicide layer and the MULTILAYER COMPOSITE coating on it also can lump together and be called storehouse.
Last again with the above-mentioned MULTILAYER COMPOSITE coating on dry method or the wet etching Semiconductor substrate, form grid structure.These technologies can adopt those skilled in the art institute well-known processes, repeat no more at this.
After forming grid, then can accomplish the manufacturing of MOS, and then accomplish the manufacturing of DRAM according to those skilled in the art institute well-known processes.
After the step that has increased the cleaning metaphosphoric acid, the defects count of the MOS transistor that produces significantly reduces, and yield improves, its effect such as Fig. 8 and shown in Figure 9.Fig. 8 cleans and the contrast of not carrying out existing defects count on the wafer that metaphosphoric acid cleans for carrying out metaphosphoric acid among the embodiment of the application's grid production method.In Fig. 8, vertical line passes through the step of cleaning metaphosphoric acid with the wafer 801 on a left side, and vertical line has passed through the step of cleaning metaphosphoric acid with the wafer 802 on the right side.As can beappreciated from fig. 7, passed through the wafer 802 that metaphosphoric acid cleans, its defects count declines to a great extent greater than 200 ratio, far fewer than the wafer 801 that does not clean through metaphosphoric acid.
Fig. 9 be among the embodiment of the application's grid production method on the wafer yield of MOS transistor distribute.It is the statistics to 1302 wafers that this yield distributes.Can know that from Fig. 9 the average yield of MOS transistor is that 85.69%, 3 σ scope is 80% to 90%, minimum yield also is higher than 75%, and this compares with yield shown in Figure 1 and significantly improves.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (1)
1. the manufacturing approach of a grid structure is characterized in that, comprises step:
Semiconductor substrate is provided, on Semiconductor substrate, forms gate oxide level;
Clean gate oxide level, the cleaning solvent of employing is the mixed solution of saturated ammoniacal liquor, hydrogen peroxide and water, and wherein saturated ammoniacal liquor is 1:5:100 than hydrogen peroxide than the ratio of water;
On gate oxide level, form the polysilicon layer of phosphorus doping;
With the said polysilicon layer of the solvent clean of solubilized metaphosphoric acid,, improve the yield of product to solve the transistor leakage phenomenon;
To the polysilicon layer of having crossed with the solvent clean of solubilized metaphosphoric acid, utilize aqueous hydrogen fluoride solution to clean, in the said aqueous hydrogen fluoride solution, the ratio of hydrogen fluoride and water is between 1:50 to 1:150;
Deposit tungsten suicide layers on the polysilicon layer that cleaned with aqueous hydrogen fluoride solution;
On tungsten silicide layer, form one or more layers storehouse;
Composite bed on the etching semiconductor substrate forms grid structure;
Wherein, the solvent of said solubilized metaphosphoric acid comprises vitriolated solvent, also comprises hydrogen peroxide in the said vitriolated solvent; In the said vitriolated solvent, the volume ratio of sulfuric acid and hydrogen peroxide is 1:6; The temperature of said vitriolated solvent is 120 ℃～130 ℃; Cleaning step with the said polysilicon layer of solvent clean of solubilized metaphosphoric acid carries out at twice, cleans 4 minutes～6 minutes at every turn.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2008101184030A CN101651095B (en) | 2008-08-14 | 2008-08-14 | Method for manufacturing gate structure |
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|---|---|---|---|
| CN2008101184030A CN101651095B (en) | 2008-08-14 | 2008-08-14 | Method for manufacturing gate structure |
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| CN101651095B true CN101651095B (en) | 2012-10-31 |
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| CN102881771A (en) * | 2012-09-29 | 2013-01-16 | 湖南红太阳光电科技有限公司 | Metaphosphoric acid piece rework method in diffusion of monocrystalline silicon solar cell |
| CN104517823B (en) * | 2014-05-29 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | Tungsten silicide film forming process |
| CN108281382B (en) * | 2018-01-22 | 2021-01-15 | 京东方科技集团股份有限公司 | Display substrate manufacturing method and display substrate |
| CN110534412A (en) * | 2019-09-09 | 2019-12-03 | 上海华虹宏力半导体制造有限公司 | Avoid the method for phosphor doped polysilicon defect and the manufacturing method of memory cell |
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