CN100377097C - Error eliminating device - Google Patents
Error eliminating device Download PDFInfo
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- CN100377097C CN100377097C CNB021422281A CN02142228A CN100377097C CN 100377097 C CN100377097 C CN 100377097C CN B021422281 A CNB021422281 A CN B021422281A CN 02142228 A CN02142228 A CN 02142228A CN 100377097 C CN100377097 C CN 100377097C
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Abstract
The present invention provides a debugging device which retrieves, analyzes and debugs the information of target systems. The debugging device comprises a user interface, a trigger event converter, a control logic device, a programmable comparator, a storage device and an analyzer, wherein the user interface is used for setting data to be recorded and triggered and transferring the data to the trigger event converter; the trigger event converter gives a code to each trigger event, logically simplifies each trigger event and transfers each trigger event to the control logic device so as to set the simplified data to the programmable comparator; the programmable comparator receives an input signal of the target system so as to compare whether the input signal accords with beforehand set triggering conditions; after comparison by the programmable comparator, the corresponding code indexes of qualified input data are transferred to the control logic device and are stored in the storage device. Besides, the analyzer extracts the code indexes from the storage device and restores the code indexes into the originally set trigger events so as to obtain the executing states of a large quantity of target systems in real environments, and the target systems are analyzed and debugged.
Description
Technical field
The present invention relates to a kind of apparatus for debugging that is used for program detection and definite abort situation, particularly relate to a large amount of computer object of a kind of fechtable system, as the data such as executing state of microprocessor (Microprocessor) under true environment, and the apparatus for debugging of system performance, error condition being analyzed according to these data.
Background technology
Have in the disposal system of complete CPU (central processing unit) subroutine at some, as microprocessor, when system when carrying out running, the information such as lot of data, address that promptly have are constantly being carried out transmitted in both directions, but, easily cause system's generation deadlock and influence its operational function owing to having logic error or the inconsiderate mistake (bug) that causes program run to take place in the system program.For improving and avoiding system in case of system halt, normally whether there are mistake or fault part in the detection system program and determine this abort situation, to reach the purpose of debug (debug).
Many perfect instruments are arranged in the design of system at present, yet for but failing relative improvement in the debug of final finished, main difference is that the target when being to design is all comparatively clear and definite, but where all do not know removing the mistake of staggering the time then, this moment, system often combined still more, complexity increases many especially, causes the user can't effectively carry out debug.Sometimes have to utilize monitor (watchdog) to monitor the incident whether certain predetermined state occurs in the official hour in system, if belonging to the timing of normal event takes place, then guidance system is handled this incident, if when having abnormal occurrence to occur, then normally system is reset (reset); But the monitor that this only can take stopgap measures and can't effect a permanent cure, the thorough problem that crashes of resolution system at all.
In addition, under embedded microprocessor (embedded microprocessor) environment, the spendable instrument of known program debugging has oscillograph (Scope) or logic analyzer instruments such as (logicanalyzer).With oscillograph and logic analyzer, the occasion that their relatively can play a role all is than the debug under short period, the situation of duplicating easily; Because understood wrong direction generally, so could set trigger condition in suspicious place, in case have under the sporadic wrong or long-time situation about just making a mistake afterwards, because the limited time of the program execution state that can write down is difficult to find error reason.
Therefore, the present invention promptly at above-mentioned puzzlement, proposes a kind of execution that can not influence real system, and the apparatus for debugging of register system executing state in a large number.
Summary of the invention
Fundamental purpose of the present invention provides a kind of apparatus for debugging that can write down, analyze in the executing state under the true environment goal systems for a long time, to carry out the interpretation of system performance analysis and program error scope according to the information that it was write down.
Another object of the present invention provides a kind of apparatus for debugging, it is with the conversion of tabulating in advance of address (address), data (data) and I/O information such as (I/O) that desire is understood, provide the user to edit setting, when triggering above-mentioned condition with convenient goal systems execution, via its corresponding code or index, can reduce corresponding required recording capacity, transmitting bandwidth widely, so can write down bulk information.
For achieving the above object, the present invention includes user's interface, in order to set the data that the desire record triggers, and be sent to a trigger event converter, be sent to a steering logic after making it give a code and carry out logic simplifying to each trigger event, so that this reduced data is set to a programmable comparator, and programmable comparator is the input signal of receiving target system, uses the trigger condition whether this input signal of comparison meets prior setting; Pass to this steering logic via the corresponding code index of input data that programmable comparator comparison condition meets, be stored in the memory storage together with clocking value, one trigger event analyzer is from this memory storage reading of data, so that the trigger event of former setting is taken out and be reduced to this code index, and it is analyzed debug.
Therefore, a kind of apparatus for debugging provided by the invention, it is connected to a goal systems, analyzes the debug operation with the information that captures this goal systems, and this apparatus for debugging comprises: user's interface provides the user can carry out the trigger condition editor thereon and sets; One trigger event converter is made logic simplifying with this trigger event; One steering logic is in order to the reduced data of the trigger event of exporting desire record; One programmable comparator, its connection also receives the input signal of this goal systems, and this steering logic is that this reduced data is set in this programmable comparator, to compare the data whether this input signal meets prior setting, the corresponding code index that will meet the input signal of this prior setting data sends this steering logic to; One memory storage is stored so far in order to the code index that this programmable comparator is sent to this steering logic; And an analyzer, can this code index be taken out and is reduced to the trigger event of setting originally from this memory storage.
To the detailed description of specific embodiments of the invention, can be more prone to the effect of understanding purpose of the present invention, technology contents, characteristics and being reached in conjunction with the drawings.
Description of drawings
Fig. 1 is a preferred embodiment synoptic diagram of the present invention.
Fig. 2 is another synoptic diagram of Fig. 1.
Fig. 3 is all module integrated embodiment synoptic diagram together of the present invention.
Embodiment
The present invention links with a principal computer, and be connected to a goal systems, and the index (index) of address (address), data (data) and the I/O information translation such as (I/O) set in advance according to the user, with the index that captures the conditional information that is triggered when this goal systems is carried out and with its storage, analyze the debug operation in order to the user, so can reduce corresponding required recording capacity and transmitting bandwidth widely, and then record bulk information.
As shown in Figure 1, the goal systems of now wanting debug (debug) is special IC (the Application specific integratedcircuit that microprocessor (microprocessor) 12 is arranged in, ASIC) 10, its program is to be placed in the internal memory 14.Because this special IC 10 is when aging (burn-in) test of screening electronic package; regular meeting of system crashes; do not know but where problem comes from; therefore this special IC 10 is connected to an apparatus for debugging 20; with the non-volatile recording program circuit; so can assist to understand the situation when ASIC 10 systems are actual to be carried out, further dwindle the scope of problem.
This apparatus for debugging 20 comprises user's interface 22, providing the user can carry out the trigger condition editor thereon sets, the condition of setting is that all want the signal analyzed, mode record with strip columnwise, and this signal is the combination of address, data and I/O, and the data of desire record triggering (trigger) are sent to a trigger event converter (Translator of Triggering Event) 24.Because the program of microprocessor 12 is to produce object code (objectcode) via compiler (complier), after using connector (linker) to produce machine code (machine code) again, promptly can produce entering the address and leaving the address of all subroutines (subroutine), be used as all trigger points with this; As long as detecting the address that internal memory reads is one of them, then can be judged as microprocessor 12 programs and carry out or leave a certain subroutine, be entered as trigger condition so those can be entered the address and leave data such as address by this user's interface 22.Then give a code respectively, and this converter 24 can do this trigger event to be sent to an interface (interface) 26 behind the logic simplifying, be transferred to a steering logic (control logic) 28 by transmission interface again all trigger events; The reduced data that steering logic 28 is then spread out of this converter 24 respectively according to host-host protocol is set to a programmable comparator (Programmable Comparator) 30, it comprises a multiple trigger (Multi-Trigger) 32 and a signal mapper (Signal Mapping) 34, and this programmable comparator 30 connects and receives the input signal of these ASIC 10 goal systems, to compare the data whether this input signal meets prior setting trigger condition.This steering logic 28 connects a timer (Timer) 36, in order to the timing Time To Event.
When microprocessor 12 is carried out, all meet the input signal of this trigger event, be entering the address and leaving the address of subroutine, the signal that the capital meets the multiple trigger 32 generation conditions in the programmable comparator 30 is given this steering logic 28, this moment, the signal of these signal mapper 34 outputs was the corresponding code of these trigger events, then export the corresponding code of trigger event to steering logic 28, make steering logic 28 that its received all messages such as signal and trigger event code index that meet are sent back interface 26 together with the time of origin of timer 36 trigger event that provides, this interface 26 is again with in these message data storage to memory storages (Storage) 38.Where carry out on earth when understanding past microprocessor 12, the user utilizes its trigger event analyzer that connects (Analyzer of Triggering Event) 40 from this memory storage 38 data to be taken out, reduced by user's interface 22, make the code index of taking-up be reduced to the trigger event that originally sets, to carry out the debug analysis, whether the microprocessor 12 that can understand in the ASIC 10 runs not come out in certain subroutine, whether interruption has abnormal conditions to take place, and whether program is gone to the place that should not carry out or the like; Add timer 36, make the execution number of times of all subroutines, execution time also can learn, thereby offer the foundation that the user improves program.
In above-mentioned embodiment shown in Figure 1, except external storage device 38 connects this interface 26 and trigger event analyzer 40, consideration based on memory capacity and frequency range demand, the present invention also can be connected directly to memory storage 38 this steering logic 28, as shown in Figure 2, all messages and time value that then this steering logic 28 can be received with it directly are stored in the memory storage 38, need not transmit by interface 26 again; Otherwise, when will analyzing to remove by user's interface 22, the user staggers the time, and 40 of this trigger event analyzers must could take out data, reduce, so that carry out the debug analysis from this memory storage 38 earlier via after interface 26 and the steering logic 28.
Above-mentioned two embodiment utilize an interface 26 that the module (Module) of front and back two parts is combined, and transmit the usefulness of data so that both to be provided.The present invention also can be directly together not module integrated with all by this interface 26; As shown in Figure 3, steering logic 28 is connected directly to trigger event converter 24, and this converter 24 is done this trigger event directly to be sent to steering logic 28 behind the logic simplifying; Steering logic 28 can directly be stored in all messages and the time value that receives in the memory storage 38, and trigger event analyzer 40 also can directly take out data from memory storage 38, reduction, to carry out the debug analysis, remaining describes in detail, and then the embodiment with Fig. 1 is identical, does not repeat them here.
Wherein, the part that the present invention can be higher to rate request with part as the multiple trigger 32 and the signal mapper 34 of programmable comparator 30, is built in the integrated circuit (IC) of goal systems in directly.And (analog todigital converter ADC), can get off it to the signal record of all excessive or too small levels (1evel) also can to set up analogue-to-digital converters at the front end of this programmable comparator.
Aforementioned apparatus for debugging is except being the setting means with single trigger condition, this triggering mode also can be multiple triggering, it is to utilize programmable comparator 30 to finish earlier to set trigger event 1～N, when this input signal successively this incident 1 takes place in regular turn to incident N, promptly represents it is real triggering; So, at specific event schema (event pattern) but also real time record need not be waited until ex-post analysis, therefore be used in particular for the debug of serial line interface (serial interface).And this trigger event pattern can be set many groups simultaneously and exist, and user's interface 22 then can provide the editor's of this state-transition (statetransition) usefulness.
Apparatus for debugging of the present invention is to convert information such as address, data and the I/O tabulation in advance that desire is understood to code index, provide the user to edit setting, when triggering above-mentioned condition with convenient goal systems execution, via its corresponding index, can reduce corresponding required recording capacity, transmitting bandwidth widely, and because the present invention only imposes a condition at situation about will analyze, the signal of other pilot process can be omitted, so can write down bulk information.In other words, suppose that on average each subroutine contains 100 little processing instructions (instruction), then average 100 instructions are as long as write down one, so the processing speed of record needs only 1/100, as long as the data volume of record is also 1/100; Add as long as the code of record trigger event, data quantity stored also can further reduce, make the present invention to write down, to analyze in the executing state under the true environment goal systems for a long time, and carry out the interpretation of program error scope according to the information that it write down.
Moreover, the present invention also can utilize above-mentioned principle and processing mode to carry out system performance analysis, make it need not add signal line analysis more in addition, when carrying out performance analysis of program, apparatus for debugging can write down the time point of each program of turnover, subroutine, and then judge the time of (certain) execution in step action required whenever, and carry out performance evaluation according to this time length.Therefore, the present invention not only can carry out the debug interpretation to the system mistake state, and can carry out performance evaluation to system simultaneously according to need.
Be based upon under the main framework of the present invention, range of application of the present invention is quite extensive, for example: the external device (ED) that is connected to goal systems, and to next order of the integrated circuit on the goal systems circuit board (IC) (command), remove to insert the register (register) in this IC, can be set as trigger pip that register writes and corresponding data/address this moment, so just can learn whether this IC is set to the state of mistake (error).Also can be applicable to DVD player (player) or MPEG code translator medium such as (decoder), when it is ordered next ATAPI of servo control mechanism (servo), can be triggered all ATAPI order, can be learnt that thus that whether not right order or the sequencing of order are arranged is wrong.In addition, timer is one of input of programmable comparator, can also utilize this timing long or too short certain device bus (device bus) that judged whether at interval to produce pinning (lock) or collision error.
Above-described embodiment only is for technological thought of the present invention and characteristics are described, its purpose is enabling those skilled in the art to understand content of the present invention and enforcement according to this, and can not limit claim scope of the present invention with this, all equalizations of doing according to the disclosed spirit of the present invention change or modify, and all should be encompassed in the claim scope of the present invention.
Claims (11)
1. apparatus for debugging, it is connected to a goal systems, analyzes the debug operation with the information that captures this goal systems, and this apparatus for debugging comprises:
One user's interface provides the user can carry out the trigger condition editor thereon and sets;
One trigger event converter is made logic simplifying with trigger event;
One steering logic is in order to the reduced data of the trigger event of exporting desire record;
One programmable comparator, its connection also receives the input signal of this goal systems, and this steering logic is set in this reduced data in this programmable comparator, so that programmable comparator is compared the data whether this input signal meets prior setting, the corresponding code index that will meet the input signal of this prior setting data sends this steering logic to;
One memory storage is stored so far in order to the code index that this programmable comparator is sent to this steering logic; And
One analyzer can take out this code index and be reduced to the trigger event of setting originally from this memory storage.
2. apparatus for debugging as claimed in claim 1, wherein this programmable comparator comprises a multiple trigger and a signal mapper, when this input signal meets this trigger event, this multiple trigger produces one and meets signal to this steering logic, and this signal mapper is then exported the corresponding code index of trigger event to this steering logic.
3. apparatus for debugging as claimed in claim 1 or 2, wherein the data that should set in advance are signal mode records to tabulate that all desires are analyzed, and this signal is the combination of address, data and I/O signal.
4. apparatus for debugging as claimed in claim 1, wherein this steering logic also connects a timer, the time that this timer provides this steering logic trigger event to take place.
5. apparatus for debugging as claimed in claim 1 wherein also can will be built in the integrated circuit in directly the higher part of rate request in this programmable comparator.
6. apparatus for debugging as claimed in claim 1, wherein this trigger event is multiple triggering, sets trigger event 1～N earlier, after this incident 1～N took place this input signal in regular turn, promptly expression was real triggering.
7. apparatus for debugging as claimed in claim 6, wherein this multiple triggering is set and is finished by this programmable comparator.
8. apparatus for debugging as claimed in claim 4, wherein this timer is set at one of input of this programmable comparator, to utilize this input signal timing long or too short generation conflict or mistake of judging whether at interval.
9. apparatus for debugging as claimed in claim 1, wherein the front end of this programmable comparator also is provided with analogue-to-digital converters.
10. apparatus for debugging as claimed in claim 1 wherein also is provided with an interface between this steering logic and this converter, transmit the usefulness of data for both.
11. apparatus for debugging as claimed in claim 10, wherein this memory storage also carries out the access of data by this interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021422281A CN100377097C (en) | 2002-08-26 | 2002-08-26 | Error eliminating device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021422281A CN100377097C (en) | 2002-08-26 | 2002-08-26 | Error eliminating device |
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| Publication Number | Publication Date |
|---|---|
| CN1479204A CN1479204A (en) | 2004-03-03 |
| CN100377097C true CN100377097C (en) | 2008-03-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB021422281A Expired - Fee Related CN100377097C (en) | 2002-08-26 | 2002-08-26 | Error eliminating device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI741488B (en) * | 2020-01-22 | 2021-10-01 | 宏正自動科技股份有限公司 | Debugging system and early warning system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4445192A (en) * | 1980-11-25 | 1984-04-24 | Hewlett-Packard Company | Logic state analyzer with time and event count measurement between states |
| US4835736A (en) * | 1986-08-25 | 1989-05-30 | Tektronix, Inc. | Data acquisition system for capturing and storing clustered test data occurring before and after an event of interest |
| US4959772A (en) * | 1988-03-24 | 1990-09-25 | Gould Inc. | System for monitoring and capturing bus data in a computer |
| CN1252875A (en) * | 1997-02-28 | 2000-05-10 | 全斯美达有限公司 | Method and apparatus for correcting errors in computer system |
| US6389558B1 (en) * | 1996-10-28 | 2002-05-14 | Altera Corporation | Embedded logic analyzer for a programmable logic device |
-
2002
- 2002-08-26 CN CNB021422281A patent/CN100377097C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4445192A (en) * | 1980-11-25 | 1984-04-24 | Hewlett-Packard Company | Logic state analyzer with time and event count measurement between states |
| US4835736A (en) * | 1986-08-25 | 1989-05-30 | Tektronix, Inc. | Data acquisition system for capturing and storing clustered test data occurring before and after an event of interest |
| US4959772A (en) * | 1988-03-24 | 1990-09-25 | Gould Inc. | System for monitoring and capturing bus data in a computer |
| US6389558B1 (en) * | 1996-10-28 | 2002-05-14 | Altera Corporation | Embedded logic analyzer for a programmable logic device |
| CN1252875A (en) * | 1997-02-28 | 2000-05-10 | 全斯美达有限公司 | Method and apparatus for correcting errors in computer system |
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| CN1479204A (en) | 2004-03-03 |
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