CN100365605C - Apparatus and method of multi-grade interrupt applicant - Google Patents
Apparatus and method of multi-grade interrupt applicant Download PDFInfo
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- CN100365605C CN100365605C CNB2005101256603A CN200510125660A CN100365605C CN 100365605 C CN100365605 C CN 100365605C CN B2005101256603 A CNB2005101256603 A CN B2005101256603A CN 200510125660 A CN200510125660 A CN 200510125660A CN 100365605 C CN100365605 C CN 100365605C
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Abstract
The present invention discloses a multi-level interruption application device and a method. The device comprises an interruption mark register, a level interruption mark register, a total interruption mark register, an interruption enabling register, a level interruption enabling register and a total interruption enabling register. The method comprises following steps that the present invention is provided with the interruption mark register, every position in the interruption mark register and simultaneously the corresponding interruption enabling register. The interruption mark register and the corresponding interruption enabling register are combined to obtain the original level interruption application, and then the application is used as an interruption source of the next higher level interruption application. The former step is repeated to the last level. By associating the total interruption enabling register, the interruption application is carried out. The present invention can reduce chip pipe feet, avoids the appearance of a very large multiway selector and simultaneously also has very good expansion ability.
Description
Technical field
The present invention relates to the circuit system design field, relate in particular to a kind of interruption application apparatus and method.
Background technology
In the circuit system design, the processor in the circuit system is when carrying out processing instruction, and central processing unit can asynchronous or synchronous event interruptions by some continually.
Above-mentioned asynchronous or synchronous event is called as and interrupts or unusual.
Interruption is an asynchronous event, mainly by hardware, as I/O (I/O) equipment, processor call, clock or timer cause, is the incident of the interrupt processor that takes place at random; Unusually being synchronous event, is the result that some specific instruction is carried out, and zero is removed, calculates and overflow etc. as main memory access mistake, floating number.Generally, anomaly ratio interrupts much frequent.Along with the product systems design becomes increasingly complex, the number and the frequency of interruption increase significantly, and these interruptions are necessary, because they support the processing of the execution of a plurality of processing procedures, a plurality of peripheral hardwares and the performance monitoring of each assembly.
Be illustrated in figure 1 as a kind of interruption application principle schematic in the prior art, fewer in interrupt source, and Interrupt Process part also can provide under the situation of enough circuit pin, and directly each interrupt source is linked to each other with the design circuit pin, when central broken hair was given birth to, each pin oneself went Interrupt Process partly to do to interrupt application.The advantage of this way is that interrupt control is fairly simple, and weak point is the interrupt pin that each interrupt source of requirement all has oneself, for the complex circuit design that a lot of interruptions are arranged now, needs a lot of pins, is unfavorable for circuit design.
Be illustrated in figure 2 as the another kind of application principle schematic of interrupting in the prior art, all interrupt source all is connected on the MUX in the interrupt generating unit, pick out an interruption by MUX, allow Interrupt Process partly handle in conjunction with OIER.When interrupt source was sent interruption, system can select to handle to look-at-me after receiving application according to priority of interrupt.Yet under a lot of situation of interrupt source, formed like this circuit will generate a very big MUX, takies very big register.And, if system is because the needs of function upgrading and will expand the time, all circuit all must design again, so its extensibility is very poor.
Summary of the invention
In view of this, the object of the present invention is to provide the interruption application device in a kind of circuit system, when solving in the prior art underway disconnected application, many pins problem on the circuit design that a lot of interrupt sources cause and the MUX capacity that causes when MUX is arranged are excessive, and extendability is very poor.
Another object of the present invention is to provide the interruption application method in a kind of circuit system, make that interrupting the application processing has good circuit characteristic and good extensibility.
For addressing the above problem, the invention provides following technical scheme:
A kind of device of multistage interruption application is characterized in that comprising:
OIER of each original interrupt source configuration, total marker register that interrupts links to each other with the Interrupt Process unit, the interrupt flag register basis level at place is separately transmitted interrupting information step by step, and all disposes an OIER at each interrupt flag register of every grade;
Interrupt flag register is used to deposit the interrupt identification in corresponding original interrupt source;
OIER is used for to enable bit of corresponding original interrupt source configuration, guarantee each interrupt source enable not disturbed each other;
The level interrupt flag register is used to preserve the interrupt identification of one-level; The level OIER is used for enabling control in the interrupt source of each grade interrupt flag register correspondence;
Total interrupt flag register is used to preserve the interrupt identification of afterbody;
Whether total OIER is carried out for last interruption and is made control.Further, described level interrupt flag register is non-original interrupt source;
Further, when described original interrupt source is a plurality of, divided into groups in the original interrupt source.
Further, when divided into groups in the original interrupt source, the combination in the original interrupt source in the group is set up according to each original interrupt source different qualities.
Further, when original interrupt source group makes up according to the type of original interrupt, the frequency that original interrupt takes place, and the original interrupt handling procedure takies each interrupt source of processing unit time uniform distribution.
Further, described total interrupt flag register and being connected of Interrupt Process unit are the lead-in wires more than one or, up to the requirement of satisfying system's output lead.
Whether further, described device is equipped with a total OIER, is connected with the Interrupt Process unit, control interruption and allow processed.
Further, increase the processing power that interrupt flag register and OIER can be expanded multistage interruption application device.
Further, increase the processing power that level interrupt flag register and level OIER can be expanded multistage interruption application device.
A kind of interruption processing method is characterized in that: may further comprise the steps:
After original interrupt takes place;
A is provided with interrupt flag register, and each position in the interrupt flag register is provided with;
B makes up interrupt flag register and corresponding OIER; Obtain at the corresponding levels the interruption, then the interrupt source of this interruption as the upper level interruption, non-original interrupt source, repeating step A, to the last one-level;
C unites total OIER, interrupts application;
The D Interrupt Process.
Further, in described step B, the original interrupt source combination in the interrupt source group can be set up according to each interrupt source different qualities.
Further, when making up, the interrupt source group, interrupt the frequency of generation, and interrupt handling routine takies processing unit time uniform distribution interrupt source according to the type of interrupting.
Description of drawings
Interrupt the application synoptic diagram in Fig. 1 prior art;
The interruption application synoptic diagram of band MUX and OIER in Fig. 2 prior art;
The generation synoptic diagram of three grades of interrupt flag registers at different levels of Fig. 3;
The connection diagram of the total interrupt flag register of Fig. 4, total OIER and Interrupt Process unit;
Fig. 5 adds the synoptic diagram of new interrupt source;
Fig. 6 improves the multistage interruption procedure to apply process flow diagram in back.
Embodiment
Below in conjunction with the description of drawings best mode for carrying out the invention.
As shown in Figure 3, in the bottom circuit, each interrupt source all has OIER 301,311,321 and the interrupt flag register 300,310 of oneself, 320, several and interrupt flag register 300,310, the interrupt source of 320 correspondences writes interrupt flag register 300,310,320 with interruption.The interrupt flag register of each interrupt source is united their OIER separately, the OIER and the interrupt flag register that are same interrupt source are with afterwards, the result is write grade interrupt flag register 330, level interrupt flag register 330 is united its level OIER 331 again, carry out according to top same step, until the afterbody interrupt flag register, total interrupt flag register 340 forms;
As shown in Figure 4, link to each other with Interrupt Process unit 204 at top total interrupt flag register 340, always OIER 341 links to each other with Interrupt Process unit 204 with the back with total interrupt flag register 340, finishes the processing of once interrupting with Interrupt Process unit 204 under total OIER 341 controls.Subordinate's interrupt flag register 0 (400) and subordinate's OIER 0 (401) both can be that the interrupt flag register and the OIER of bottom also can be grade interrupt flag register and level OIER.
If systematic comparison is huge, the interrupt source that relates to is also very many, and the group that is divided into is also a lot, also can be with in groups interrupt source, and whole as one " interrupt source ".Allow these " interrupt sources " to divide into groups once more.To them grade OIER 331 is set simultaneously.
Through after the above-mentioned continuous grouping, total interrupt flag register 340 has formed satisfying under the situation of system requirements.That is to say that we can handle all look-at-mes that interrupt source produced step by step, obtain the requisite number purpose at the top layer circuit at last and interrupt output (the output pin number by system decides), send to the Interrupt Process unit 204 of system.
Further, change,, need to increase interrupt source such as the systemic-function expansion if design has taken place in circuit design.Only need very simple processing just can increase, and need not design again.
As shown in Figure 5, system has increased two interruptions newly: new interrupt source a and new interrupt source b, corresponding new interrupt flag register a and new interrupt flag register b, if there is the position in the unnecessary idle interrupt flag register to utilize in the system in other groups, in just these two new interrupt distribution being organized to other; If there is not the position in the idle interrupt flag register to utilize in the system, reset new interrupt flag register and OIER just for these two new interruptions, and the design that need not change other; New interrupt source a530 make new interrupt flag register a and its new OIER a with after, the result is filled out in the interrupt flag register 320, equally, new interrupt source b540 make new interrupt flag register and its new OIER b with after, the result is filled out in the interrupt flag register 320.New interrupt source is just added recent, then, they just proposed to interrupt application according to former mode.Not as a lot of must the improvement, two new interruptions just join in the system like this.Certainly, perhaps two new interruptions can belong to different groups, and way also is the same.If because having increased this group has caused the not enough situation of upper level interrupt flag register, can reset new level interrupt flag register and level OIER to upper level more equally.So, obtain requisite number purpose interruption output up to satisfying the top layer circuit.
As shown in Figure 6, when dividing into groups, at first according to the generation of interrupting, interrupt flag register setting with bottom, the bottom OIER is set again, so after setting completed, allow each interrupt source interrupt flag register and OIER with, form new level interrupt flag register; The level OIER of utilizing it with obtain more senior interrupt flag register, and the like, can obtain total interrupt flag register at last; Utilize this total interrupt flag register to mention then and interrupt application, the processing that request is interrupted to the Interrupt Process device.
The above, only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, so protection domain of the present invention is as the criterion with the protection domain of claims.
Claims (12)
1. the device of a multistage interruption application is characterized in that comprising:
OIER of each original interrupt source configuration, total marker register that interrupts links to each other with the Interrupt Process unit, the interrupt flag register basis level at place is separately transmitted interrupting information step by step, and all disposes an OIER at each interrupt flag register of every grade;
Interrupt flag register is used to deposit the interrupt identification in corresponding original interrupt source;
OIER is used for to enable bit of corresponding original interrupt source configuration, guarantee each interrupt source enable not disturbed each other;
The level interrupt flag register is used to preserve the interrupt identification of one-level; The level OIER is used for enabling control in the interrupt source of each grade interrupt flag register correspondence;
Total interrupt flag register is used to preserve the interrupt identification of afterbody;
Whether total OIER is carried out for last interruption and is made control.
2. multistage interruption application device according to claim 1 is characterized in that: described level interrupt flag register is non-original interrupt source;
3. according to the described multistage interruption application device of claim 1, it is characterized in that: when described original interrupt source is a plurality of, divided into groups in the original interrupt source.
4. according to the described multistage interruption application device of claim 3, it is characterized in that: when divided into groups in the original interrupt source, the combination in the original interrupt source in the group is set up according to each original interrupt source different qualities.
5. according to the described multistage interruption application device of claim 4, it is characterized in that: when original interrupt source group makes up according to the type of original interrupt, the frequency that original interrupt takes place, and the original interrupt handling procedure takies each interrupt source of processing unit time uniform distribution.
6. according to the described multistage interruption application device of claim 1, it is characterized in that: described total interrupt flag register and being connected of Interrupt Process unit are the lead-in wires more than one or, up to the requirement of satisfying system's output lead.
7. according to the described multistage interruption application device of claim 1, whether it is characterized in that: described device is equipped with a total OIER, is connected with the Interrupt Process unit, control interruption and allow processed.
8. according to the described multistage interruption application device of claim 1, it is characterized in that: increase the processing power that interrupt flag register and OIER can be expanded multistage interruption application device.
9. according to the described multistage interruption application device of claim 1, it is characterized in that: increase the processing power that level interrupt flag register and level OIER can be expanded multistage interruption application device.
10. interruption processing method is characterized in that: may further comprise the steps:
After original interrupt takes place;
A is provided with interrupt flag register, and each position in the interrupt flag register is provided with;
B makes up interrupt flag register and corresponding OIER; Obtain at the corresponding levels the interruption, then the interrupt source of this interruption as the upper level interruption, non-original interrupt source, repeating step A, to the last one-level;
C unites total OIER, interrupts application;
The D Interrupt Process.
11. according to the described method of claim 10, it is characterized in that: in described step B, the original interrupt source combination in the interrupt source group can be set up according to each interrupt source different qualities.
12., it is characterized in that: according to the type of interrupting, interrupt the frequency of generation, and interrupt handling routine takies processing unit time uniform distribution interrupt source when the interrupt source group makes up according to the described method of claim 11.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005101256603A CN100365605C (en) | 2005-12-02 | 2005-12-02 | Apparatus and method of multi-grade interrupt applicant |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005101256603A CN100365605C (en) | 2005-12-02 | 2005-12-02 | Apparatus and method of multi-grade interrupt applicant |
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| CN1786933A CN1786933A (en) | 2006-06-14 |
| CN100365605C true CN100365605C (en) | 2008-01-30 |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101901165B (en) * | 2010-07-26 | 2013-04-10 | 清华大学 | Circuit structure of interruption controller |
| CN102495816B (en) * | 2011-11-16 | 2014-12-24 | 武汉日电光通信工业有限公司 | Quick interrupt graded processing device and method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1030311A (en) * | 1987-07-01 | 1989-01-11 | 数字设备公司 | The equipment and the method for control asynchronous routine interrupt event in the data handling system |
| US5530875A (en) * | 1993-04-29 | 1996-06-25 | Fujitsu Limited | Grouping of interrupt sources for efficiency on the fly |
| CN1309350A (en) * | 2000-01-24 | 2001-08-22 | 摩托罗拉公司 | Flexible interruption controller comprising one interuption forced register |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1030311A (en) * | 1987-07-01 | 1989-01-11 | 数字设备公司 | The equipment and the method for control asynchronous routine interrupt event in the data handling system |
| US5530875A (en) * | 1993-04-29 | 1996-06-25 | Fujitsu Limited | Grouping of interrupt sources for efficiency on the fly |
| CN1309350A (en) * | 2000-01-24 | 2001-08-22 | 摩托罗拉公司 | Flexible interruption controller comprising one interuption forced register |
| JP2001229031A (en) * | 2000-01-24 | 2001-08-24 | Motorola Inc | Flexible interruption controller including interruption forcing register |
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