CN109800510A - A kind of method, system and the equipment of FPGA placement-and-routing - Google Patents
A kind of method, system and the equipment of FPGA placement-and-routing Download PDFInfo
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Abstract
This application discloses a kind of methods of FPGA placement-and-routing, comprising: receives placement-and-routing's request of input；It executes placement-and-routing's request and wiring is laid out to each module, obtain placement-and-routing's result；Judge whether the timing of placement-and-routing's result restrains；If not converged, placement-and-routing's result is adjusted according to placement-and-routing's adjustable strategies are preset, until the timing closure of placement-and-routing's result；If convergence, terminates this placement-and-routing.When being unsatisfactory for timing closure in face of placement-and-routing's result, the application does not need user and goes to manually adjust, but voluntarily placement-and-routing's result is adjusted according to default placement-and-routing's adjustable strategies, the waste of human resources is avoided, while improving the efficiency of placement-and-routing.The application additionally provides system, equipment and the computer readable storage medium of a kind of FPGA placement-and-routing simultaneously, has above-mentioned beneficial effect.
Description
Technical field
This application involves FPGA placement-and-routing field, in particular to a kind of method of FPGA placement-and-routing, system, equipment and
Computer readable storage medium.
Background technique
In recent years, machine learning is constantly risen, and FPGA is wide due to the power consumption with concurrency structure and relative reduction
General use, wherein CNN convolutional neural networks algorithm etc. is implemented as research hotspot in FPGA.The acceleration of algorithm is in FPGA
Realize that the framework usually utilized is as shown in Figure 1.The one end FPGA is connected by PCIE interface with HOST host, and outside hangs multi-disc
The memory devices such as DDR.The wherein realization that CNN scheduling algorithm accelerates, the logical gate based on FPGA generally comprise the part PCIE and (include
The part DMA), DDR part, Kernel part and board other function control section.Wherein the part Kernel is primarily used to
Realize the function of CNN algorithm.How logic is laid out to wiring to map to meet timing closure and fill in FPGA
Dividing becomes key subject using FPGA resource.
The shortcomings that present solution, is largely automatic placement and routing, this method is, when logic is larger
When, the result of placement-and-routing is unsatisfactory for timing closure sometimes, needs manually to adjust, greatly wastes human resources, make
The efficiency for obtaining placement-and-routing is lower.
Therefore, how to improve the efficiency of placement-and-routing in FPGA is that the technology that those skilled in the art need to solve at present is asked
Topic.
Summary of the invention
The purpose of the application is to provide method, system, equipment and the computer-readable storage medium of a kind of FPGA placement-and-routing
Matter, for improving the efficiency of placement-and-routing in FPGA.
In order to solve the above technical problems, the application provides a kind of method of FPGA placement-and-routing, this method comprises:
Receive placement-and-routing's request of input；
It executes placement-and-routing's request and wiring is laid out to each module, obtain placement-and-routing's result；
Judge whether the timing of placement-and-routing's result restrains；
If not converged, placement-and-routing's result is adjusted according to placement-and-routing's adjustable strategies are preset, until institute
State the timing closure of placement-and-routing's result；
If convergence, terminates this placement-and-routing.
Optionally, it executes placement-and-routing's request and wiring is laid out to each module, obtain placement-and-routing as a result, packet
It includes:
The placement position region of PCIE module and DDR module is divided according to FPGA Pin locations, and determines the PCIE mould
The placement position of block and the DDR module, obtains initial layout；
Judge whether the timing of the initial layout restrains；
If it is not, being then adjusted to the placement position of the PCIE module and the DDR module, until the initial layout
Timing closure；
If so, being that the module interacted in Kernel with DDR storage divides placement position area around the DDR module
Domain, and determine the placement position of the module interacted with DDR storage, obtain quadratic assignment；
The wiring for completing each module in the quadratic assignment obtains placement-and-routing's result.
Optionally, the placement position region that PCIE module and DDR module are divided according to FPGA Pin locations, comprising:
The placement-and-routing's tool for calling Xilinx or Altera is the PCIE module and described according to FPGA Pin locations
DDR module sets corresponding physical location restrictions.
Optionally, after described this placement-and-routing of end, further includes:
It records current arrangements and is routed number, and generate placement-and-routing's report.
The application also provides a kind of system of FPGA placement-and-routing, which includes:
Receiving module, placement-and-routing's request for receiving input；
Placement-and-routing's module is laid out wiring to each module for executing placement-and-routing's request, obtains layout cloth
Knot fruit；
Judgment module, for judging whether the timing of placement-and-routing's result restrains；
Placement-and-routing adjusts module, for when the timing of placement-and-routing's result is not converged, according to default layout cloth
Line adjustable strategies are adjusted placement-and-routing's result, until the timing closure of placement-and-routing's result；
Ending module, for terminating this placement-and-routing when the timing closure of placement-and-routing's result.
Optionally, placement-and-routing's module includes:
First layout submodule, for dividing the placement position area of PCIE module and DDR module according to FPGA Pin locations
Domain, and determine the placement position of the PCIE module and the DDR module, obtain initial layout；
First judging submodule, for judging whether the timing of the initial layout restrains；
Adjusting submodule, for when the timing of the initial layout does not restrain, to the PCIE module and the DDR mould
The placement position of block is adjusted, until the timing closure of the initial layout；
Second layout submodule, for being around the DDR module when the timing closure of the initial layout
The module interacted in Kernel with DDR storage divides placement position region, and determines the cloth of the module interacted with DDR storage
Office position, obtains quadratic assignment；
It is routed submodule, for completing the wiring of each module in the quadratic assignment, obtains placement-and-routing's knot
Fruit.
Optionally, the first layout submodule includes:
Call unit is described according to FPGA Pin locations for calling placement-and-routing's tool of Xilinx or Altera
PCIE module and the DDR module set corresponding physical location restrictions.
Optionally, the system also includes:
Logging modle for recording current arrangements' wiring number, and generates placement-and-routing's report.
The application also provides a kind of FPGA placement-and-routing equipment, which includes:
Memory, for storing computer program；
Processor realizes the method for the FPGA placement-and-routing as described in any of the above-described when for executing the computer program
The step of.
The application also provides a kind of computer readable storage medium, and calculating is stored on the computer readable storage medium
Machine program realizes the step of the method for FPGA placement-and-routing as described in any of the above-described when the computer program is executed by processor
Suddenly.
The method of FPGA placement-and-routing provided herein, comprising: receive placement-and-routing's request of input；Execute layout cloth
Line request is laid out wiring to each module, obtains placement-and-routing's result；Judge whether the timing of placement-and-routing's result restrains；If
It is not converged, then according to preset placement-and-routing's adjustable strategies placement-and-routing's result is adjusted, until placement-and-routing's result when
Sequence convergence；If convergence, terminates this placement-and-routing.
Technical solution provided herein first carries out the placement-and-routing's request received and is laid out cloth to each module
Line obtains placement-and-routing's result；Then judge whether the timing of placement-and-routing's result restrains；If not converged, according to default cloth
Office's wiring adjustable strategies are adjusted placement-and-routing's result, until the timing closure of placement-and-routing's result；If convergence, terminates
This time placement-and-routing；When being unsatisfactory for timing closure in face of placement-and-routing's result, the application does not need user and goes to manually adjust, and
It is voluntarily to be adjusted according to default placement-and-routing's adjustable strategies to placement-and-routing's result, avoids the waste of human resources, together
When improve the efficiency of placement-and-routing.The application additionally provides system, equipment and the computer of a kind of FPGA placement-and-routing simultaneously
Readable storage medium storing program for executing has above-mentioned beneficial effect, and details are not described herein.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of application for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of structural schematic diagram of FPGA in the prior art；
Fig. 2 is a kind of flow chart of the method for FPGA placement-and-routing provided by the embodiment of the present application；
Fig. 3 is a kind of process of practical manifestation mode of S202 in a kind of method of FPGA placement-and-routing provided by Fig. 2
Figure；
Fig. 4 is a kind of schematic diagram of FPGA placement-and-routing result provided by the embodiments of the present application；
Fig. 5 is a kind of structure chart of the system of FPGA placement-and-routing provided by the embodiment of the present application；
Fig. 6 is the structure chart of the system of another kind FPGA placement-and-routing provided by the embodiment of the present application；
Fig. 7 is a kind of structure chart of FPGA placement-and-routing equipment provided by the embodiment of the present application.
Specific embodiment
The core of the application is to provide method, system, equipment and the computer-readable storage medium of a kind of FPGA placement-and-routing
Matter, for improving the efficiency of placement-and-routing in FPGA.
To keep the purposes, technical schemes and advantages of the embodiment of the present application clearer, below in conjunction with the embodiment of the present application
In attached drawing, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described embodiment is
Some embodiments of the present application, instead of all the embodiments.Based on the embodiment in the application, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall in the protection scope of this application.
Referring to FIG. 2, Fig. 2 is a kind of flow chart of the method for FPGA placement-and-routing provided by the embodiment of the present application.
It specifically comprises the following steps:
S201: placement-and-routing's request of input is received；
FPGA is widely used programming device currently on the market, has many advantages, such as that the development cycle is short and at low cost.
Various applications may be implemented in FPGA, and in the CAD software process of FPGA design, placement-and-routing is vital one
Step.Layout method has determined position of each logic unit block for realizing circuit function needs in FPGA, its optimization aim is
Connected logic unit block close to placement to reduce required interconnection resource to the maximum extent, but FPGA is also balanced sometimes
In required wiring density or improve circuit speed to greatest extent.Once it is determined that in circuit all logic unit blocks position
It sets, wiring unit can get through suitable programmable switch to connect all outputting and inputting for logic unit block of circuit needs and draw
Foot.
Method based on existing FPGA placement-and-routing is largely automatic placement and routing, and the result of placement-and-routing is unsatisfactory for
When timing closure, needs manually to adjust, greatly waste human resources, so that the efficiency of placement-and-routing is lower, this Shen
A kind of method of FPGA placement-and-routing please be provide, for solving the above problems.
S202: it executes placement-and-routing's request and wiring is laid out to each module, obtain placement-and-routing's result；
Optionally, when receiving placement-and-routing request, the layout of each module can be divided according to FPGA Pin locations
The band of position, and wiring is laid out to each module, obtain placement-and-routing's result；
Specifically, placement-and-routing's tool of Xilinx or Altera can be called, according to each module in FPGA pin
Position draws the placement position region of each module, sets corresponding constraint, then randomly chooses each mould in the placement position region
Layout is completed in the position of block, is then routed.
S203: judge whether the timing of placement-and-routing's result restrains；
If it is not, then entering step S204；If so, entering step S205；
After having carried out placement-and-routing, judge whether the timing of placement-and-routing's result restrains, if convergence, shows
Placement-and-routing's result has been met the requirements, and entering step S205 at this time terminates this placement-and-routing.
S204: being adjusted placement-and-routing's result according to default placement-and-routing's adjustable strategies, until placement-and-routing's result
Timing closure；
When the timing of placement-and-routing's result does not restrain, then placement-and-routing is tied according to default placement-and-routing's adjustable strategies
Fruit is adjusted, until the timing closure of placement-and-routing's result；
Default placement-and-routing's adjustable strategies mentioned herein are specifically as follows one kind specified by user or manufacturer
Placement-and-routing's adjustable strategies, such as: when this layout not to be laid out for the first time, selectes one or more module and carry out position shifting
It is dynamic, including translate or rotate, mobile x distance or clockwise or counterclockwise a angle every time；
Optionally, which can be imported or be manually entered by user, or be
System is connected to what designated position downloaded to, and the application is not specifically limited the acquisition modes of default placement-and-routing's adjustable strategies；
It optionally, can also be according to the default layout cloth when receiving default placement-and-routing's adjustable strategies modification order
The modification order of line adjustable strategies modifies to default placement-and-routing's adjustable strategies.
S205: terminate this placement-and-routing；
Optionally, when terminating this placement-and-routing, can with output layout be routed as a result, placement-and-routing's result it is defeated
Mode can specifically be sent by specified path out, allow the user to get placement-and-routing in time as a result, then completing whole
The production of a FPGA；
Optionally, after terminating this placement-and-routing, current arrangements' wiring number can also be recorded, and generate layout cloth
Report from a liner is accused.
Based on the above-mentioned technical proposal, the method for a kind of FPGA placement-and-routing provided herein is first carried out and is received
Placement-and-routing's request is laid out wiring to each module, obtains placement-and-routing's result；Then judge the timing of placement-and-routing's result
Whether restrain；If not converged, placement-and-routing's result is adjusted according to placement-and-routing's adjustable strategies are preset, until layout cloth
The timing closure of knot fruit；If convergence, terminates this placement-and-routing；Timing closure is being unsatisfactory in face of placement-and-routing's result
When, the application does not need user and goes to manually adjust, but voluntarily according to default placement-and-routing's adjustable strategies to placement-and-routing's result
It is adjusted, avoids the waste of human resources, while improving the efficiency of placement-and-routing.
It is directed to the step S202 of an embodiment, wherein described execute placement-and-routing's request to each module progress cloth
Office's wiring, obtains placement-and-routing as a result, it specifically may be step as shown in Figure 3, is illustrated below with reference to Fig. 3.
Referring to FIG. 3, a kind of practical manifestation of the Fig. 3 for S203 in a kind of method of FPGA placement-and-routing provided by Fig. 2
The flow chart of mode.
Itself specifically includes the following steps:
S301: the placement position region of PCIE module and DDR module is divided according to FPGA Pin locations, and determines PCIE mould
The placement position of block and DDR module, obtains initial layout；
The placement position region mentioned herein that PCIE module and DDR module are divided according to FPGA Pin locations, it is specific
It can be with are as follows:
The placement-and-routing's tool for calling Xilinx or Altera is PCIE module and DDR module according to FPGA Pin locations
Set corresponding physical location restrictions.
S302: judge whether the timing of initial layout restrains；
If it is not, then entering step S303；If so, entering step S304；
S303: being adjusted the placement position of PCIE module and DDR module, until the timing closure of initial layout；
S304: being the module division placement position region interacted in Kernel with DDR storage around DDR module, and
The placement position for determining the module interacted with DDR storage, obtains quadratic assignment；
S305: the wiring of each module in quadratic assignment is completed, placement-and-routing's result is obtained.
For example, referring to FIG. 4, Fig. 4 is a kind of schematic diagram of FPGA placement-and-routing result provided by the embodiments of the present application, originally
Apply for that embodiment determines first and be laid out biggish PCIE module and DDR module, then according to PCIE the position of FPGA pin just
The placement position for closely drawing PCIE module carries out physical location restrictions, draws DDR mould nearby in the position of FPGA pin according to DDR
The placement position of block carries out physical location restrictions, and is laid out to PCIE module and DDR module, obtains initial layout；Then
Judge whether the timing of initial layout restrains；If it is not, being then adjusted to the position of PCIE module and DDR module, until initial
The timing closure of layout；If so, according to default placement-and-routing's adjustable strategies to the module interacted in Kernel with DDR storage
(such as two-dimensional convolution part has the request of many and DDR storage interaction) divides placement position region around DDR module,
Other parts can break up automatically, not do position constraint, and be laid out wiring again, obtain placement-and-routing's result.
Referring to FIG. 5, Fig. 5 is a kind of structure chart of the system of FPGA placement-and-routing provided by the embodiment of the present application.
The system may include:
Receiving module 100, placement-and-routing's request for receiving input；
Placement-and-routing's module 200 is laid out wiring to each module for executing placement-and-routing's request, obtains placement-and-routing
As a result；
Judgment module 300, for judging whether the timing of placement-and-routing's result restrains；
Placement-and-routing adjusts module 400, for when the timing of placement-and-routing's result is not converged, according to default placement-and-routing
Adjustable strategies are adjusted placement-and-routing's result, until the timing closure of placement-and-routing's result；
Ending module 500, for terminating this placement-and-routing when the timing closure of placement-and-routing's result.
Referring to FIG. 6, Fig. 6 is the structure chart of the system of another kind FPGA placement-and-routing provided by the embodiment of the present application.
Placement-and-routing's module 200 may include:
First layout submodule, for dividing the placement position area of PCIE module and DDR module according to FPGA Pin locations
Domain, and determine the placement position of PCIE module and DDR module, obtain initial layout；
First judging submodule, for judging whether the timing of initial layout restrains；
Adjusting submodule, for when the timing of initial layout does not restrain, to the placement position of PCIE module and DDR module
It is adjusted, until the timing closure of initial layout；
Second layout submodule, for when the timing closure of initial layout, around the DDR module in Kernel with
The module of DDR storage interaction divides placement position region, and determines the placement position of the module interacted with DDR storage, obtains two
Secondary layout；
It is routed submodule and obtains placement-and-routing's result for completing the wiring of each module in quadratic assignment.
This first layout submodule may include:
Call unit is PCIE according to FPGA Pin locations for calling placement-and-routing's tool of Xilinx or Altera
Module and DDR module set corresponding physical location restrictions.
The system can also include:
Logging modle for recording current arrangements' wiring number, and generates placement-and-routing's report.
Since the embodiment of components of system as directed is corresponded to each other with the embodiment of method part, the embodiment of components of system as directed is asked
Referring to the description of the embodiment of method part, wouldn't repeat here.
Referring to FIG. 7, Fig. 7 is a kind of structure chart of FPGA placement-and-routing equipment provided by the embodiment of the present application.
The FPGA placement-and-routing equipment 700 can generate bigger difference because configuration or performance are different, may include one
A or more than one processor (central processing units, CPU) 722 is (for example, one or more are handled
Device) and memory 732, one or more storage application programs 742 or data 744 storage medium 730 (such as one or
More than one mass memory unit).Wherein, memory 732 and storage medium 730 can be of short duration storage or persistent storage.It deposits
Storage may include one or more modules (diagram does not mark) in the program of storage medium 730, and each module may include
To the series of instructions operation in device.Further, central processing unit 722 can be set to communicate with storage medium 730,
The series of instructions operation in storage medium 730 is executed in FPGA placement-and-routing equipment 700.
FPGA placement-and-routing equipment 700 can also include one or more power supplys 727, one or more are wired
Or radio network interface 750, one or more input/output interfaces 758, and/or, one or more operating systems
741, such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM etc..
Step in the method for FPGA placement-and-routing described in above-mentioned Fig. 2 to Fig. 4 is based on by FPGA placement-and-routing equipment
The structure shown in Fig. 7 is realized.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description,
The specific work process of device and module, can refer to corresponding processes in the foregoing method embodiment, and details are not described herein.
In several embodiments provided herein, it should be understood that disclosed device, device and method, it can be with
It realizes by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the division of module,
Only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple module or components can be with
In conjunction with or be desirably integrated into another system, or some features can be ignored or not executed.Another point, it is shown or discussed
Mutual coupling, direct-coupling or communication connection can be through some interfaces, the INDIRECT COUPLING of device or module or
Communication connection can be electrical property, mechanical or other forms.
Module may or may not be physically separated as illustrated by the separation member, show as module
Component may or may not be physical module, it can and it is in one place, or may be distributed over multiple networks
In module.Some or all of the modules therein can be selected to achieve the purpose of the solution of this embodiment according to the actual needs.
It, can also be in addition, can integrate in a processing module in each functional module in each embodiment of the application
It is that modules physically exist alone, can also be integrated in two or more modules in a module.Above-mentioned integrated mould
Block both can take the form of hardware realization, can also be realized in the form of software function module.
If integrated module is realized and when sold or used as an independent product in the form of software function module, can
To be stored in a computer readable storage medium.Based on this understanding, the technical solution of the application substantially or
Say that all or part of the part that contributes to existing technology or the technical solution can embody in the form of software products
Out, which is stored in a storage medium, including some instructions are used so that a computer equipment
The whole of (can be personal computer, funcall device or the network equipment etc.) execution each embodiment method of the application
Or part steps.And storage medium above-mentioned include: USB flash disk, mobile hard disk, read-only memory (Read-Only Memory,
ROM), random access memory (Random Access Memory, RAM), magnetic or disk etc. are various can store program
The medium of code.
Above to method, system, equipment and the computer-readable storage of a kind of FPGA placement-and-routing provided herein
Medium is described in detail.Specific examples are used herein to illustrate the principle and implementation manner of the present application, with
The explanation of upper embodiment is merely used to help understand the present processes and its core concept.It should be pointed out that being led for this technology
For the those of ordinary skill in domain, under the premise of not departing from the application principle, can also to the application carry out it is several improvement and
Modification, these improvement and modification are also fallen into the protection scope of the claim of this application.
It should also be noted that, in the present specification, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that the process, method, article or equipment for including a series of elements not only includes that
A little elements, but also including other elements that are not explicitly listed, or further include for this process, method, article or
The intrinsic element of equipment.In the absence of more restrictions, the element limited by sentence "including a ...", is not arranged
Except there is also other identical elements in the process, method, article or equipment for including element.
Claims (10)
1. a kind of method of FPGA placement-and-routing characterized by comprising
Receive placement-and-routing's request of input；
It executes placement-and-routing's request and wiring is laid out to each module, obtain placement-and-routing's result；
Judge whether the timing of placement-and-routing's result restrains；
If not converged, placement-and-routing's result is adjusted according to placement-and-routing's adjustable strategies are preset, until the cloth
The timing closure of office's wiring result；
If convergence, terminates this placement-and-routing.
2. being laid out the method according to claim 1, wherein executing placement-and-routing's request to each module
Wiring, obtains placement-and-routing's result, comprising:
The placement position region of PCIE module and DDR module is divided according to FPGA Pin locations, and determine the PCIE module and
The placement position of the DDR module, obtains initial layout；
Judge whether the timing of the initial layout restrains；
If it is not, be then adjusted to the placement position of the PCIE module and the DDR module, until the initial layout when
Sequence convergence；
If so, be that the module interacted in Kernel with DDR storage divides placement position region around the DDR module,
And determine the placement position of the module interacted with DDR storage, obtain quadratic assignment；
The wiring for completing each module in the quadratic assignment obtains placement-and-routing's result.
3. according to the method described in claim 2, it is characterized in that, it is described according to FPGA Pin locations divide PCIE module and
The placement position region of DDR module, comprising:
The placement-and-routing's tool for calling Xilinx or Altera is the PCIE module and the DDR according to FPGA Pin locations
Module sets corresponding physical location restrictions.
4. the method according to claim 1, wherein after described this placement-and-routing of end, further includes:
It records current arrangements and is routed number, and generate placement-and-routing's report.
5. a kind of system of FPGA placement-and-routing characterized by comprising
Receiving module, placement-and-routing's request for receiving input；
Placement-and-routing's module is laid out wiring to each module for executing placement-and-routing's request, obtains placement-and-routing's knot
Fruit；
Judgment module, for judging whether the timing of placement-and-routing's result restrains；
Placement-and-routing adjusts module, for when the timing of placement-and-routing's result is not converged, according to default placement-and-routing's tune
Whole strategy is adjusted placement-and-routing's result, until the timing closure of placement-and-routing's result；
Ending module, for terminating this placement-and-routing when the timing closure of placement-and-routing's result.
6. system according to claim 5, which is characterized in that placement-and-routing's module includes:
First layout submodule, for dividing the placement position region of PCIE module and DDR module according to FPGA Pin locations, and
The placement position for determining the PCIE module and the DDR module, obtains initial layout；
First judging submodule, for judging whether the timing of the initial layout restrains；
Adjusting submodule, for when the timing of the initial layout does not restrain, to the PCIE module and the DDR module
Placement position is adjusted, until the timing closure of the initial layout；
Second layout submodule, for when the timing closure of the initial layout, being Kernel around the DDR module
In the module that is interacted with DDR storage divide placement position region, and determine the layout position of the module interacted with DDR storage
It sets, obtains quadratic assignment；
It is routed submodule and obtains placement-and-routing's result for completing the wiring of each module in the quadratic assignment.
7. system according to claim 6, which is characterized in that described first, which is laid out submodule, includes:
Call unit is the PCIE according to FPGA Pin locations for calling placement-and-routing's tool of Xilinx or Altera
Module and the DDR module set corresponding physical location restrictions.
8. system according to claim 7, which is characterized in that further include:
Logging modle for recording current arrangements' wiring number, and generates placement-and-routing's report.
9. a kind of FPGA placement-and-routing equipment characterized by comprising
Memory, for storing computer program；
Processor, realizing the FPGA placement-and-routing as described in any one of Claims 1-4 when for executing the computer program
The step of method.
10. a kind of computer readable storage medium, which is characterized in that be stored with computer on the computer readable storage medium
Program realizes the side of the FPGA placement-and-routing as described in any one of Claims 1-4 when the computer program is executed by processor
The step of method.
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| CN201910063583.5A CN109800510A (en) | 2019-01-23 | 2019-01-23 | A kind of method, system and the equipment of FPGA placement-and-routing |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111177989A (en) * | 2019-12-27 | 2020-05-19 | 广东高云半导体科技股份有限公司 | Method, device and system for controlling layout and wiring by taking wiring result as guide |
| CN112087471A (en) * | 2020-09-27 | 2020-12-15 | 山东云海国创云计算装备产业创新中心有限公司 | Data transmission method and FPGA cloud platform |
| CN112800702A (en) * | 2021-02-03 | 2021-05-14 | 北京华大九天科技股份有限公司 | R-corner automatic layout and wiring method and device and storage medium |
-
2019
- 2019-01-23 CN CN201910063583.5A patent/CN109800510A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111177989A (en) * | 2019-12-27 | 2020-05-19 | 广东高云半导体科技股份有限公司 | Method, device and system for controlling layout and wiring by taking wiring result as guide |
| CN111177989B (en) * | 2019-12-27 | 2023-03-24 | 广东高云半导体科技股份有限公司 | Method, device and system for controlling layout and wiring by taking wiring result as guide |
| CN112087471A (en) * | 2020-09-27 | 2020-12-15 | 山东云海国创云计算装备产业创新中心有限公司 | Data transmission method and FPGA cloud platform |
| CN112800702A (en) * | 2021-02-03 | 2021-05-14 | 北京华大九天科技股份有限公司 | R-corner automatic layout and wiring method and device and storage medium |
| CN112800702B (en) * | 2021-02-03 | 2022-04-15 | 北京华大九天科技股份有限公司 | R-corner automatic layout and wiring method and device and storage medium |
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Application publication date: 20190524 |