CN1786933A - Apparatus and method of multi-grade interrupt applicant - Google Patents
Apparatus and method of multi-grade interrupt applicant Download PDFInfo
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- CN1786933A CN1786933A CN 200510125660 CN200510125660A CN1786933A CN 1786933 A CN1786933 A CN 1786933A CN 200510125660 CN200510125660 CN 200510125660 CN 200510125660 A CN200510125660 A CN 200510125660A CN 1786933 A CN1786933 A CN 1786933A
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Abstract
The invention discloses a multilevel interrupt applying device and method, and the device comprises interrupt flag register, level interrupt flag register, total interrupt flag register, interrupt enable register, level interrupt enable register, and total interrupt enable register. And the method comprises the follow steps of: setting the interrupt flag register, i.e. setting each bit in the interrupt flag register; simultaneously the corresponding interrupt enable register; combining the interrupt flag register with the corresponding interrupt enable register; if obtaining a local level interrupt application, taking this interrupt application as an interrupt source for the previous-level interrupt application, and repeating the previous step until the last level; combining with the total interrupt enable register to make interrupt application. The invention can reduce chip pins, avoiding the occurrence of a multi-channel selector and having very good extensibility.
Description
Technical field
The present invention relates to the circuit system design field, relate in particular to a kind of interruption application apparatus and method.
Background technology
In the circuit system design, the processor in the circuit system is when carrying out processing instruction, and central processing unit can asynchronous or synchronous event interruptions by some continually.
Above-mentioned asynchronous or synchronous event is called as and interrupts or unusual.
Interruption is an asynchronous event, mainly by hardware, as I/O (I/O) equipment, processor call, clock or timer cause, is the incident of the interrupt processor that takes place at random; Unusually being synchronous event, is the result that some specific instruction is carried out, and zero is removed, calculates and overflow etc. as main memory access mistake, floating number.Generally, anomaly ratio interrupts much frequent.Along with the product systems design becomes increasingly complex, the number and the frequency of interruption increase significantly, and these interruptions are necessary, because they support the processing of the execution of a plurality of processing procedures, a plurality of peripheral hardwares and the performance monitoring of each assembly.
Be illustrated in figure 1 as a kind of interruption application principle schematic in the prior art, fewer in interrupt source, and Interrupt Process part also can provide under the situation of enough circuit pin, and directly each interrupt source is linked to each other with the design circuit pin, when central broken hair was given birth to, each pin oneself went Interrupt Process partly to do to interrupt application.The advantage of this way is that interrupt control is fairly simple, and weak point is the interrupt pin that each interrupt source of requirement all has oneself, for the complex circuit design that a lot of interruptions are arranged now, needs a lot of pins, is unfavorable for circuit design.
Be illustrated in figure 2 as the another kind of application principle schematic of interrupting in the prior art, all interrupt source all is connected on the MUX in the interrupt generating unit, pick out an interruption by MUX, allow Interrupt Process partly handle in conjunction with OIER.When interrupt source was sent interruption, system can select to handle to look-at-me after receiving application according to priority of interrupt.Yet under a lot of situation of interrupt source, formed like this circuit will generate a very big MUX, takies very big register.And, if system is because the needs of function upgrading and will expand the time, all circuit all must design again, so its extensibility is very poor.
Summary of the invention
In view of this, the object of the present invention is to provide the interruption application device in a kind of circuit system, when solving in the prior art underway disconnected application, many pins problem on the circuit design that a lot of interrupt sources cause and the MUX capacity that causes when MUX is arranged are excessive, and extendability is very poor.
Another object of the present invention is to provide the interruption application method in a kind of circuit system, make that interrupting the application processing has good circuit characteristic and good extensibility.
For addressing the above problem, the invention provides following technical scheme:
A kind of device of multistage interruption application is characterized in that, comprising:
Interrupt flag register is preserved the interrupt identification in original interrupt source;
The level interrupt flag register is used to preserve the interrupt identification of one-level;
Total interrupt flag register is used to preserve the interrupt identification of afterbody;
OIER is used for to enable bit of corresponding interrupt source configuration, guarantee each interrupt source enable not disturbed each other;
The level OIER is used for enabling control in the interrupt source of each grade interrupt flag register correspondence;
Whether total OIER is carried out for last interruption and is made control.
Further, when the interrupt source of multistage interruption application device is a plurality of, can divide into groups; When the interrupt source group makes up according to but be not limited to the type of interruption, interrupt the frequency that takes place, and interrupt handling routine takies processing unit time uniform distribution interrupt source; Part original interrupt source can be regarded as non-original interrupt source during grouping, and then divide into groups, rationally utilize various interrupt flag registers and OIER.
Further, total interrupt flag register of multistage interruption application device is to link to each other with the Interrupt Process unit.Being connected of total interrupt flag register and Interrupt Process unit can be a lead-in wire or the lead-in wire more than, up to the requirement of satisfying system's output lead.
Whether further, multistage interruption application device is equipped with a total OIER, is connected with the Interrupt Process unit, control interruption and can handle; Each interrupt source all disposes an OIER; Described each grade interrupt flag register all disposes a level OIER.
Further, multistage interruption application device increases the processing power that interrupt flag register and OIER or increase level interrupt flag register and level OIER can be expanded multistage interruption application device.
A kind of interruption processing method is characterized in that: may further comprise the steps:
After interrupting taking place;
A is provided with interrupt flag register, and each position in the interrupt flag register is provided with;
B makes up interrupt flag register and corresponding OIER; Obtain the application of interrupting at the corresponding levels, then this is applied for the interrupt source that upper level interrupts application, repeating step A, to the last one-level interrupt flag register;
C unites total enable bit, interrupts application;
The D Interrupt Process.
Further, multistage interruption application method can be according to the type of interrupt source when interrupt source is divided into groups in described step B, the frequency of generation, and take the uniform distribution of processor time.
The present invention is well arranged, and circuit does not influence mutually between each interrupt source in good order, has avoided the appearance of big selector switch, and favorable expansibility is arranged.
Description of drawings
Interrupt the application synoptic diagram in Fig. 1 prior art;
The interruption application synoptic diagram of band MUX and OIER in Fig. 2 prior art;
The generation synoptic diagram of three grades of interrupt flag registers at different levels of Fig. 3;
The connection diagram of the total interrupt flag register of Fig. 4, total OIER and Interrupt Process unit;
Fig. 5 adds the synoptic diagram of new interrupt source;
Fig. 6 improves the multistage interruption procedure to apply process flow diagram in back.
Embodiment
Below in conjunction with the description of drawings best mode for carrying out the invention.
As shown in Figure 3, in the bottom circuit, each interrupt source all has OIER 301,311,321 and the interrupt flag register 300,310 of oneself, 320, several and interrupt flag register 300,310, the interrupt source of 320 correspondences writes interrupt flag register 300,310,320 with interruption.The interrupt flag register of each interrupt source is united their OIER separately, the OIER and the interrupt flag register that are same interrupt source are with afterwards, the result is write grade interrupt flag register 330, level interrupt flag register 330 is united its level OIER 331 again, carry out according to top same step, until the afterbody interrupt flag register, total interrupt flag register 340 forms;
As shown in Figure 4, link to each other with Interrupt Process unit 204 at top total interrupt flag register 340, always OIER 341 links to each other with Interrupt Process unit 204 with the back with total interrupt flag register 340, finishes the processing of once interrupting with Interrupt Process unit 204 under total OIER 341 controls.Subordinate's interrupt flag register 0 (400) and subordinate's OIER 0 (401) both can be that the interrupt flag register and the OIER of bottom also can be grade interrupt flag register and level OIER.
If systematic comparison is huge, the interrupt source that relates to is also very many, and the group that is divided into is also a lot, also can be with in groups interrupt source, and whole as one " interrupt source ".Allow these " interrupt sources " to divide into groups once more.To them grade OIER 331 is set simultaneously.
Through after the above-mentioned continuous grouping, total interrupt flag register 340 has formed satisfying under the situation of system requirements.That is to say that we can handle all look-at-mes that interrupt source produced step by step, obtain the requisite number purpose at the top layer circuit at last and interrupt output (the output pin number by system decides), send to the Interrupt Process unit 204 of system.
Further, change,, need to increase interrupt source such as the systemic-function expansion if design has taken place in circuit design.Only need very simple processing just can increase, and need not design again.
As shown in Figure 5, system has increased two interruptions newly: new interrupt source a and new interrupt source b, corresponding new interrupt flag register a and new interrupt flag register b, if there is the position in the unnecessary idle interrupt flag register to utilize in the system in other groups, in just these two new interrupt distribution being organized to other; If there is not the position in the idle interrupt flag register to utilize in the system, reset new interrupt flag register and OIER just for these two new interruptions, and the design that need not change other; New interrupt source a530 make new interrupt flag register a and its new OIER a with after, the result is filled out in the interrupt flag register 320, equally, new interrupt source b540 make new interrupt flag register and its new OIER b with after, the result is filled out in the interrupt flag register 320.New interrupt source is just added recent, then, they just proposed to interrupt application according to former mode.Not as a lot of must the improvement, two new interruptions just join in the system like this.Certainly, perhaps two new interruptions can belong to different groups, and way also is the same.If because having increased this group has caused the not enough situation of upper level interrupt flag register, can reset new level interrupt flag register and level OIER to upper level more equally.So, obtain requisite number purpose interruption output up to satisfying the top layer circuit.
As shown in Figure 6, when dividing into groups, at first according to the generation of interrupting, interrupt flag register setting with bottom, the bottom OIER is set again, so after setting completed, allow each interrupt source interrupt flag register and OIER with, form new level interrupt flag register; The level OIER of utilizing it with obtain more senior interrupt flag register, and the like, can obtain total interrupt flag register at last; Utilize this total interrupt flag register to mention then and interrupt application, the processing that request is interrupted to the Interrupt Process device.
The above, only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, so protection domain of the present invention is as the criterion with the protection domain of claims.
Claims (14)
1, a kind of device of multistage interruption application is characterized in that comprising:
Interrupt flag register is used to deposit the interrupt identification of corresponding interrupt source;
The level interrupt flag register is used to preserve the interrupt identification of one-level; This grade interrupt flag register also can be used as non-original interrupt source;
Total interrupt flag register is used to preserve the interrupt identification of afterbody;
OIER is used for to enable bit of corresponding interrupt source configuration, guarantee each interrupt source enable not disturbed each other;
The level OIER is used for enabling control in the interrupt source of each grade interrupt flag register correspondence;
Whether total OIER is carried out for last interruption and is made control.
2, according to the described multistage interruption application device of claim 1, it is characterized in that: when described interrupt source is a plurality of, can divide into groups.
3, according to the described multistage interruption application device of claim 2, it is characterized in that: during the interrupt source grouping, the combination of the interrupt source in the group can be set up according to each interrupt source different qualities.
4, according to the described multistage interruption application device of claim 3, it is characterized in that: when the interrupt source group makes up according to but be not limited to the type of interruption, interrupt the frequency that takes place, and interrupt handling routine takies each interrupt source of processing unit time uniform distribution.
5, according to the described multistage interruption application device of claim 1, it is characterized in that: total interrupt flag register links to each other with the Interrupt Process unit, all the other interrupt flag registers, according to place separately grade, transmit interrupting information step by step.
6, according to the described multistage interruption application device of claim 5, it is characterized in that: being connected of described total interrupt flag register and Interrupt Process unit can be a lead-in wire or the lead-in wire more than, up to the requirement of satisfying system's output lead.
7, according to the described multistage interruption application device of claim 1, whether it is characterized in that: described device is equipped with a total OIER, is connected with the Interrupt Process unit, control interruption and can handle.
8, according to the described multistage interruption application device of claim 1, it is characterized in that: described each original interrupt source all disposes an OIER.
9, according to the described multistage interruption application device of claim 1, it is characterized in that: described each grade interrupt flag register, all dispose a level OIER.
10, according to the described multistage interruption application device of claim 1, it is characterized in that: increase the processing power that interrupt flag register and OIER can be expanded multistage interruption application device.
11, according to the described multistage interruption application device of claim 1, it is characterized in that: increase the processing power that level interrupt flag register and level OIER can be expanded multistage interruption application device.
12, a kind of interruption processing method is characterized in that: may further comprise the steps:
After interrupting taking place;
A is provided with interrupt flag register, and each position in the interrupt flag register is provided with;
B makes up interrupt flag register and corresponding OIER; Obtain at the corresponding levels the interruption, then the interrupt source of this interruption as the upper level interruption, non-original interrupt source, repeating step A, to the last one-level;
C unites total OIER, please in interrupting;
The D Interrupt Process.
13, according to the described method of claim 12, it is characterized in that: in described step B, the combination of the interrupt source in the interrupt source group can be set up according to each interrupt source different qualities.
14, according to the described method of claim 13, it is characterized in that: when the interrupt source group makes up according to but be not limited to the type of interruption, interrupt the frequency that takes place, and interrupt handling routine takies processing unit time uniform distribution interrupt source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101256603A CN100365605C (en) | 2005-12-02 | 2005-12-02 | Apparatus and method of multi-grade interrupt applicant |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101256603A CN100365605C (en) | 2005-12-02 | 2005-12-02 | Apparatus and method of multi-grade interrupt applicant |
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| CN1786933A true CN1786933A (en) | 2006-06-14 |
| CN100365605C CN100365605C (en) | 2008-01-30 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101901165A (en) * | 2010-07-26 | 2010-12-01 | 清华大学 | Circuit structure of interruption controller |
| CN102495816A (en) * | 2011-11-16 | 2012-06-13 | 武汉日电光通信工业有限公司 | Quick interrupt graded processing device and method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IN171220B (en) * | 1987-07-01 | 1992-08-15 | Digital Equipment Corp | |
| US5530875A (en) * | 1993-04-29 | 1996-06-25 | Fujitsu Limited | Grouping of interrupt sources for efficiency on the fly |
| US6845419B1 (en) * | 2000-01-24 | 2005-01-18 | Freescale Semiconductor, Inc. | Flexible interrupt controller that includes an interrupt force register |
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2005
- 2005-12-02 CN CNB2005101256603A patent/CN100365605C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101901165A (en) * | 2010-07-26 | 2010-12-01 | 清华大学 | Circuit structure of interruption controller |
| CN101901165B (en) * | 2010-07-26 | 2013-04-10 | 清华大学 | Circuit structure of interruption controller |
| CN102495816A (en) * | 2011-11-16 | 2012-06-13 | 武汉日电光通信工业有限公司 | Quick interrupt graded processing device and method |
| CN102495816B (en) * | 2011-11-16 | 2014-12-24 | 武汉日电光通信工业有限公司 | Quick interrupt graded processing device and method |
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| Publication number | Publication date |
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| CN100365605C (en) | 2008-01-30 |
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