CN100363916C - ARM-PC/104 bus bridge circuit - Google Patents

Abstract

The present invention relates to a bridge circuit from an ARM embedded microprocessor system to a PC/104 bus. An ARM-PC/104 bus bridge circuit comprises an address and data connection circuit, a bus timing circuit, a bus control circuit, and an interruption and DMA auxiliary circuit; pins are divided into two groups; one group is connected with an ARM CPU bus, and the other group is connected with the PC/104 bus; one group of signal pins can be directly connected with corresponding signal pins of the ARM CPU external bus; two groups of bridge signals can be directly connected to the socket of the PC/104 bus. When the present invention is used, the ARM embedded microprocessor system has the capacity of accessing the PC/104 bus.

Description

ARM-PC/104 bus bridge circuit

Technical field

The present invention relates to the bridgt circuit of a kind of ARM embedded microprocessor system to the PC/104 bus.

Background technology

The system that the ARM embedded microprocessor system is based on Britain ARM company micro-processor kernel generally partly is made up of CPU, storer, network interface, USB interface or the like, as shown in Figure 2.At present, the ARM embedded microprocessor system does not possess direct visit PC/104 bus ability, does not possess direct visit isa bus ability yet.List of references:

[1]PC/104 Embedded Consortium.PC/104Specification Version 2.5，November 2003；

[2]AVPRO Computers，Incorporated.ISA Bus Timing Diagrams，P/N 5001321 RevsionA，June 98；

[3]DDI0100E_ARM_ARM.ARM Limited 2000；

[4]Jagger(ed.).ARM Architectural Reference Manual.Prentice Hall.ISBN0-13-736299-4；

[5]Samsung Electronics Co.，Ltd.S3c2410X 32-bit Risc Microprocessor User’s Manual，Revision 1.2.21.2-s3-c2410x-052003；

[6]Samsung Electronics Co.，Ltd.S3c44BOX 32-bit Risc Microprocessor User’s Manual，Revision 1.2.21.2-s3-c2410x-052003；

[7]Altera Corporation.Introduction to Quartus II Version 4.0.January 2004-11-28。

Summary of the invention

The object of the present invention is to provide a kind of ARM of making embedded microprocessor system to possess visit PC/104 bus or/and the ARM-PC/104 bus bridge circuit of isa bus ability.

To achieve these goals, technical scheme of the present invention is: ARM-PC/104 bus bridge circuit (hereinafter to be referred as the ARM-PC/104 bridge) comprises address and data connecting circuit, the bus timing circuit, bus control circuit, interrupt and the DMA auxiliary circuit, address and data connecting circuit latch impact damper and decoding scheme constitutes by two-way, decoding scheme the I/O address space of PC/104 bus and reservoir spatial mappings in the reservoir space of ARM, signal Dir controls the two-way direction that latchs impact damper, signal oe control is two-way, and to latch the output terminal of impact damper effective, signal csn select two-way latch which byte of impact damper in the read-write cycle effectively;

The bus timing circuit comprises clock generator, address generator, three parts of address timing sequencer, leg signal clock is the clock input signal with ARM embedded microprocessor system clock synchronization in the clock generator, leg signal nBE[3:0], leg signal Addr[26:0], leg signal nIOCS16, leg signal nMEMCS16 and code translator output enable signal e are through generating bus address signal SA[23:0 behind the address generator] and the high byte useful signal nBHE of system, the address timing sequencer resetted when enable signal e rising edge was effective, and begin to count, enable the BALE pulse through output bus address latch behind k the leg signal clock, be I/O address scope or memory address range according to current period simultaneously, insertion IOn or MEMn leg signal clock cycle form waiting signal nWAIT, bus cycles after the reduction can be satisfied the regularly requirement of PC/104 sequential, and slower I/O equipment is further applied for more latent period with IOCHKRDY;

When expansion card bus request signal nMASTER16 is effective, bus control circuit is asked bus with output pin signal nXBREQ to ARMCPU, ARM CPU responds with bus request answer signal nXBACK, after this bus control circuit output signal e n makes the memory read signal nMEMR of decoding scheme, memory write signals nMEMW, system storage read signal nSMEMR, system storage write signal nSMEMW, I/O read signal nIOR, I/O write signal nIOW end output high-impedance state, and signal oe is low, make and two-wayly latch impact damper output and be in high-impedance state, the address bus SA of the circuit of bus timing simultaneously, bus address latch enable BALE, the high byte useful signal nBHE of system also is high-impedance state, and bus control circuit output signal e nl also makes leg signal DACK[3:0 simultaneously], leg signal DACK[7:5], leg signal AEN, leg signal TC is output as high-impedance state; External unit carried out refresh operation to the dynamic storage on the PC/104 when memory refress signal nREFRESH was effective, bus control circuit is given ARM CPU request bus with output pin signal nXBREQ, ARM CPU responds with bus request answer signal nXBACK, after this bus control circuit output signal e n makes the memory read signal nMEMR of decoding scheme, memory write signals nMEMW, system storage read signal nSMEMR, system storage write signal nSMEMW, I/O read signal nIOR, I/O write signal nIOW end output high-impedance state, and signal oe is low, make and two-wayly latch impact damper output and be in high-impedance state, the address bus SA of the circuit of bus timing simultaneously, bus address latch enable BALE, the high byte useful signal nBHE of system also is high-impedance state, and bus control circuit output signal e nl also makes leg signal DACK[3:0 simultaneously], leg signal DACK[7:5], leg signal AEN, leg signal TC is output as high-impedance state; Leg signal RESET output high level when reset signal nRESET is effective, the inner individual count device of the ARM-PC/104 bridge that resets simultaneously;

I/O channel check signal nIOCHK causes a look-at-me when effective, look-at-me can be distributed on any one idle external interrupt;

Interrupt and direct memory access (DMA) auxiliary circuit: interrupt application signal IRQX and after oppositely, output to leg signal nIRQX, ARM CPU has only two outside DMA passages, leg signal DRQ[3:0] export to leg signal nXDREQO, leg signal DRQ[7:5 mutually or after non-] export to leg signal nXDREQl mutually or after non-, export to leg signal DACK[3:O after leg signal nXDACKO is reverse], export to leg signal DACK[7:5 after leg signal nXDACK0 is reverse]; AEN is under an embargo during DMA; During leg signal nMASTER16 and the leg signal nREFRESH, leg signal IRQX, leg signal DRQ[3:0], leg signal DRQ[7:5] signal will not be output to ARM CPU;

Pin is divided into two groups, one group is the coupling part with the ARM cpu bus, two groups are and PC/104 bus coupling part, and first group of signal pins can be directly connected to ARM CPU external bus corresponding signal pin, and second group of bridge signal can be directly connected on the socket of PC/104 bus.

Effect of the present invention is exactly to be the signal that meets the PC/104 bus specification ARM cpu data bus signal, address bus signal, control bus signal or through data bus B signal, address bus B signal, the control bus B conversion of signals of bus buffer, thereby makes the also correct equipment on the reading and writing PC/104 bus of ARM CPU.Isa bus and PC/104 bus compatible, the ARM embedded microprocessor system also possesses direct visit isa bus ability simultaneously.The present invention makes the ARM embedded microprocessor system possess visit PC/104 bus or/and the isa bus ability.

The present invention be mainly used in based on the ARM embedded microprocessor system comprise the PC/104 bus interface or/and the system of isa bus, as shown in Figure 1.

Description of drawings

Fig. 1 is an application synoptic diagram of the present invention

Fig. 2 is existing ARM embedded microprocessor system figure

Fig. 3 is an electric principle frame structure synoptic diagram of the present invention

Fig. 4 a, Fig. 4 b are electric theory structure synoptic diagram of the present invention

Embodiment

One, ARM-PC/104 bus bridge circuit engineering standard

1 pinout

ARM-PC/104 bridge pinout is divided into two groups, and one group is and the coupling part of ARM cpu bus, and two groups are and PC/104 bus coupling part.Table 1 is the function declaration of these signals.

Table 1ARM-PC/104 bridge leg signal

Sequence number	Signal	Explanation
			First group		Coupling part with the ARM cpu bus
1	Data[31:16]	Two-way, ternary.Data bus D31 ~ D16
			2	Data[15:0]	Two-way, ternary.Data bus D15 ~ D0
3	NGCS[5:1]	Input, low level is effective, general choosing.When ARM during in the interval addressing of corresponding memory BANK this signal effective
			4	Addr[26:0]	Input.Address bus A26 ~ A0
5	NWE	Input, low level is effective, and memory write enables, and represents that current is write cycle time
			6	NOE	Input, low level is effective, and memory read enables, and represents that current is the read cycle
7	Clock	System clock, the bus operation clock
			8	NWAIT	Output, low level is effective, the bus operation waiting signal.Make current bus operation cycle stretch-out
9	NBE[3:0]	Input, low level is effective, byte enable
			10	NIRQX	Output, interrupt request
11	NXBREQ	Output, low level is effective, bus request.Another bus main control equipment request local bus control
			12	NXBACK	Input, low level is effective, and bus request is replied.Allow another bus main control equipment to keep local bus control
13	NRESET	Input, low level is effective, resets
			14	NXDREQ[1:0]	Output, low level is effective, 0,1 request of DMA passage
15	NXDACK[1:0]	Input, low level is effective, DMA passage 0,1 request-reply
Second group		With PC/104 bus coupling part
			1	SD[15:8]	Two-way, ternary.Data bus most-significant byte D15 ~ D8
2	SD[7:0]	Two-way, ternary.Data bus least-significant byte D7 ~ D0
			3	SA[23:0]	Output, address bus, A23 ~ A0

4	NMEMR	Output, low level is effective, memory read.Represent that current is the memory read operation cycle
			5	NMEMW	Output, low level is effective, memory write.Represent that current is the memory write operation cycle
6	NSMEMR	Output, low level is effective, and system storage is read.During read operation, nSMEMR is effective in storage address A23 ~ A0 is first 1M address
			7	NSMEMW	Output, low level is effective, and system storage is write.During write operation, nSMEMW is effective in storage address A23 ~ A0 is first 1M address
8	NIOR	Output, low level is effective, and I/O reads.Represent that current is the I/O read operation cycle
			9	NIOW	Output, low level is effective, and I/O writes.Represent that current is the I/O write cycles
10	BCLK	Output, system clock
			11	OSC	Output/or input, the 14.31818Hz clock
12	IOCHKRDY	Input, high level is effective, and the I/O passage is prepared.The request additional busses cycle
			13	NSRDY	Input, low level is effective, prepares synchronously.Request finishes current period in advance
14	NIOCS16	Input, low level is effective, 16 I/O passage addressing chip selection signals
			15	NMEMCS16	Input, low level is effective, 16 bit memory addressing chip selection signals
16	BALE	Output, effectively high.The bus address latch enable
			17	NBHE	Output, low level is effective, and system's high byte is effective
18	NREFRESH	Memory refress
			19	NMASTER16	Input, low level is effective, expansion card Request System bus
20	NIOCHK	Input, low level is effective, the I/O channel check.Represent the I/O channel failure in the time of effectively
			21	RESET	Output, effectively high, system reset
22	IRQX	Interrupt request
			23	DRQ[3:0] DRQ[7:5]	Input, the DMA request
24	DACK[3:0] DACK[7:5]	Output, DMA asks response
			25	TC	Output, DMA counts termination
26	AEN	Output, bus address enables
Power supply
			1	Vcc	Power supply just, 5V for example, 3.3V etc.
2	GND	Ground

2 basic electrical specifications

(1) ARM CPU external bus standard is satisfied in the coupling part of ARM-PC/104 bridge signal and ARM cpu bus, referring to list of references [3] ~ [6].Each signal pins can be directly connected to ARM CPU external bus corresponding signal pin.

(2) the PC/104 bus specification is satisfied in the coupling part of ARM-PC/104 bridge signal and PC/104 bus, referring to list of references [1] [2].The ARM-PC/104 bridge signal can be directly connected on the socket of PC/104 bus, the relation such as the table 2 of each signal and PC/104 bus hub pin.

The relation of table 2ARM-PC/104 bridge signal and PC/104 bus hub pin

P1
			Pin	RowA	RowB
1	nIOCHK	GND
			2	SD7	RESET
3	SD6	+5V
			4	SD5	IRQ9
5	SD4	-5V
			6	SD3	DRQ2
7	SD2	-12V
			8	SD1	nSRDY
9	SD0	+12V
			10	IOCHRDY	KEY
11	AEN	nSMEMW
			12	SA19	nSMEMR
13	SA18	nIOW
			14	SA17	nIOR
15	SA16	nDACK3
			16	SA15	DRQ3
17	SA14	nDACK1
			18	SA13	DRQ1
19	SA12	nREFRESH
			20	SA11	BCLK
21	SA10	IRQ7
			22	SA9	IRQ6
23	SA8	IRQ5
			24	SA7	IRQ4
25	SA6	IRQ3
			26	SA5	nDACK2
27	SA4	TC
			28	SA3	BALE
29	SA2	+5V
			30	SA1	OSC
31	SA0	GND
			32	GND	GND

P2
			Pin	RowD	RowC
0	GND	GND
			1	nMEMCS16	nSBHE
2	nIOCS16	SA23
			3	IRQ10	SA22
4	IRQ11	SA21
			5	IRQ12	SA20
6	IRQ15	SA19
			7	IRQ14	SA18
8	nDACK0	SA17
			9	DRQ0	nMEMR
10	nDACK5	nMEMW
			11	DRQ5	SD8
12	nDACK6	SD9
			13	DRQ6	SD10
14	nDACK7	SD11
			15	DRQ7	SD12
16	+5V	SD13
			17	nMASTER	SD14
18	GND	SD15
			19	GND	KEY

3 other performances

(1) PC/104 address

ARM CPU particularly uses the System on Chip/SoC of ARM7, ARM9, ARM10 kernel, generally all has the addressing capability in 4GB space.PC/104 is based on the STD bus of X86, and he only takies the sub-fraction in 4G space, concerns as shown in table 3 each other.ARM-PC/104 bridge memory sequential and I/O sequential are when satisfying the PC/104 standard, under the situation that does not change hardware circuit on the PC/104 expansion board, as long as circuit condition allows, can improve bus access speed, the highest ARM external bus operation speed that can reach zero-waiting, promptly the invention provides a mechanism of using quick input/output space, possess than Standard PC/104 bus operation speed faster, to improve the I/O ability.The address of ARM-PC/104 bridge is one of the present invention and realizes special case in the table 3, takies the situation of address according to concrete system existing device, can allow the ARM-PC/104 bridge use other address realms, to avoid address conflict.

Table 3PC/104 address reference

ARM-PC/104 bridge address	The PC104 definition	Corresponding x86 address	The space size
				2920 FFFFH 2920 0000H	The quick input/output space of ARM-PC/104 bridge expansion	FFFFH x86 I/O addressing range 0000H	64KB
2900 FFFFH 2900 0000H	Input/output space	FFFFH x86 I/O addressing range 0000H	64KB
				28FF FFFFH 2800 0000H	Storage space	FFFFFFH x86 memory addressing scope 000000H	16MB

(2) interrupt

ARM CPU particularly uses the System on Chip/SoC of ARM7TDMI, ARM9TDMI kernel, generally all has abundant external interrupt, offers the ARM-PC/104 bridge and shines upon interrupt source on the PC/104 bus.And generally can trigger on the ARM System on Chip/SoC, thereby provide the more interruption of the triggering of manying type than PC/104 interrupting being programmed for rising edge, negative edge, high level, low level or two edge.Table 4 is realization special cases that a PC/104 bus interrupts being mapped to by the ARM-PC/104 bridge ARM system respective interrupt, and its circuit theory diagrams are in Fig. 4.

(3)DMA

ARM CPU particularly uses the System on Chip/SoC of ARM7TDMI, ARM9TDMI kernel, general 8/16/32 dma controllers able to programme that all have two support PC/104 buses, provide bus ← → bus, bus ← → peripheral hardware, peripheral hardware ← → the peripheral hardware transmission mode, DMA passage DRQ0, DRQ1, DRQ2, DRQ3 uses the DMAO controller, DMA passage DRQ5, DRQ6, DRQ7 use the DMA1 controller.

Two, principle of work of the present invention, as shown in Figure 3, address and data connecting circuit, bus timing circuit, bus control circuit, interruption and DMA auxiliary circuit:

(1) address and data connecting circuit

Decoding scheme of the present invention the I/O address space of PC/104 bus and reservoir spatial mappings in the reservoir space of ARM.Table 3 is concrete examples, nGCS[5:1], Addr[26:0], nEW, nOE be through decoding scheme decoding back formation nMEMR, nMEMW, nSMEMR, nSMEMW, nIOR, nIOW, dir, oe, csn and e signal.Signal Dir controls the two-way direction that latchs impact damper, and signal oe control is two-way, and to latch the output terminal of impact damper effective, signal csn select two-way latch which byte of impact damper in the read-write cycle effectively.

ARM CPU external bus width generally can be programmed for byte wide (8Bit), half-word width (16Bit) or word width (32Bit), the PC/104 bus then nIOCS16 or nMEMCS16 when low by 16 visit I/O equipment or reservoir, otherwise conduct interviews by 8.The bus timing circuit produces the two-way one group of Port Multiplier that latchs impact damper inside of csm signal controlling, the two-way impact damper that latchs of multibyte is connected for low high and low bit byte with SD at nIOCS16 or nMEMCS16, and other situations only is connected to the low byte of SD.

The two-way impact damper that latchs of multibyte is when ARM CPU external bus width is byte and half-word width, the minimum two-way impact damper that latchs that comprises two byte wides, the two-way impact damper that latchs of four byte wides of minimum needs when ARM CPU external bus width is word width.

(2) bus timing circuit

The bus timing circuit comprises clock generator, address generator, three parts of address timing sequencer, leg signal clock is the clock input signal with ARM embedded microprocessor system clock synchronization in the clock generator, leg signal nBE[3:0], leg signal Addr[26:0], leg signal nIOCS16, leg signal nMEMCS16 and code translator output enable signal e are through generating bus address signal SA[23:0 behind the address generator] and the high byte useful signal nBHE of system, the address timing sequencer resetted when enable signal e rising edge was effective, and begin to count, enable the BALE pulse through output bus address latch behind k the leg signal clock, be I/O address scope or memory address range according to current period simultaneously, insertion IOn or MEMn leg signal clock cycle form waiting signal nWAIT, bus cycles after the reduction can be satisfied the regularly requirement of PC/104 sequential, and slower I/O equipment is further applied for more latent period with IOCHKRDY.

K is relevant with clock clock frequency Fc, Fc when 100MHz, k=4, Fc when 50MHz, k=2.

IOn and MEMn are determined by ARM CPU memory read/write clock period and PC/104 bus I/O or the difference of memory read/write clock period.

IOn=(PC/104 bus I/O read/write time-ARM CPU memory read/write time) * Fc

MEMn=(PC/104 bus driver read/write time-ARM CPU memory read/write time) * Fc

(3) bus control circuit

When expansion card bus request signal nMASTER16 is effective, bus control circuit is asked bus with output pin signal nXBREQ to ARMCPU, ARM CPU responds with bus request answer signal nXBACK, after this bus control circuit output signal e n makes the memory read signal nMEMR of decoding scheme, memory write signals nMEMW, system storage read signal nSMEMR, system storage write signal nSMEMW, I/O read signal nIOR, I/O write signal nIOW end output high-impedance state, and signal oe is low, make and two-wayly latch impact damper output and be in high-impedance state, the address bus SA of the circuit of bus timing simultaneously, bus address latch enable BALE, the high byte useful signal nBHE of system also is high-impedance state, and bus control circuit output signal e nl also makes leg signal BACK[3:0 simultaneously], leg signal BACK[7:5], leg signal AEN, leg signal TC is output as high-impedance state;

External unit carried out refresh operation to the dynamic storage on the PC/104 when memory refress signal nREFRESH was effective, bus control circuit is given ARM CPU request bus with output pin signal nXBREQ, ARM CPU responds with bus request answer signal nXBACK, after this bus control circuit output signal e n makes the memory read signal nMEMR of decoding scheme, memory write signals nMEMW, system storage read signal nSMEMR, system storage write signal nSMEMW, I/O read signal nIOR, I/O write signal nIOW end output high-impedance state, and signal oe is low, make and two-wayly latch impact damper output and be in high-impedance state, the address bus SA of the circuit of bus timing simultaneously, bus address latch enable BALE, the high byte useful signal nBHE of system also is high-impedance state, and bus control circuit output signal e nl also makes leg signal DACK[3:0 simultaneously], leg signal DACK[7:5], leg signal AEN, leg signal TC is output as high-impedance state;

Leg signal RESET output high level when reset signal nRESET is effective, the inner individual count device of the ARM-PC/104 bridge that resets simultaneously;

I/O channel check signal nIOCHK causes a look-at-me when effective, look-at-me can be distributed on any one idle external interrupt, and for example external interrupt 7.

(4) interruption and direct memory access (DMA) auxiliary circuit:

Interrupt application signal IRQX and after oppositely, output to leg signal nIRQX, ARM CPU has only two outside DMA passages, leg signal DRQ[3:0] export to leg signal nXDREQ0, leg signal DRQ[7:5 mutually or after non-] export to leg signal nXDREQ1 mutually or after non-, export to leg signal DACK[3:0 after leg signal nXDACK0 is reverse], export to leg signal DACK[7:5 after leg signal nXDACK0 is reverse];

AEN is under an embargo during DMA;

During leg signal nMASTER16 and the leg signal nREFRESH, leg signal IRQX, leg signal DRQ[3:0], leg signal DRQ[7:5] signal will not be output to ARM CPU.

(5) hardware element of realizing the ARM-PC/104 bridge is given an example

The ARM-PC/104 bridge can be used 74LV373,74LV138, medium scale integration (MSI) chips such as 74LV16373 are realized, also can realize with CPLD or FPGA circuit chip (for example ALTERA MAX and MAX II etc.), perhaps use the combination of these circuit components to realize, perhaps use special IC to realize.

The present invention has many useful purposes, and for example constituting with ARM is the 90mm that satisfies the PC/104 standard, 3.5 of CPU ", 5 " system of specification etc., also can constitute the various systems of the band isa bus slot that is CPU with ARM.The structure ARM-PC/104 bridge of Fig. 4 can be used for the S3C2410 ARM9 of Samsung, constitutes a system applies; Make S3C2410 possess the ability of visit PCI04 bus by the ARM-PC/104 bridge; EPM1 is ALTERA EPM3256 among Fig. 4, and U1, U2 are 74LV162245, and S3C2410 is initialized to 16 external memory interface.

Claims (1)

1.ARM-PC/104 bus bridge circuit, it is characterized in that it comprises address and data connecting circuit, bus timing circuit, bus control circuit, interruption and DMA auxiliary circuit, address and data connecting circuit latch impact damper and decoding scheme constitutes by two-way, decoding scheme the I/O address space of PC/104 bus and reservoir spatial mappings in the reservoir space of ARM CPU;

The bus timing circuit comprises clock generator, address generator, three parts of address timing sequencer, leg signal clock is the clock input signal synchronous with the ARM cpu clock in the clock generator, leg signal nBE[3:0], leg signal Addr[26:0], leg signal nIOCS16, leg signal nMEMCS16 and code translator output enable signal e be through generating bus address signal SA[23:0 behind the address generator] and the high byte useful signal nBHE of system;

Bus control circuit is given ARM CPU request bus with output pin signal nXBREQ, and ARM CPU responds with bus request answer signal nXBACK;

Interrupt and the DMA auxiliary circuit: interrupt application signal IRQX and after oppositely, output to leg signal nIRQX, ARM CPU has only two outside DMA passages, leg signal DRQ[3:0] export to leg signal nXDREQ0, leg signal DRQ[7:5 mutually or after non-] export to leg signal nXDREQ1 mutually or after non-, export to leg signal DACK[3:0 after leg signal nXDACK0 is reverse], export to leg signal DACK[7:5 after leg signal nXDACK0 is reverse];

Pin is divided into two groups, one group is the coupling part with the ARM cpu bus, two groups are and PC/104 bus coupling part, and first group of signal pins can be directly connected to ARM CPU external bus corresponding signal pin, and second group of bridge signal can be directly connected on the socket of PC/104 bus.

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