CN100354634C - Instantaneous voltage detection circuit to multiple power source supply end - Google Patents
Instantaneous voltage detection circuit to multiple power source supply end Download PDFInfo
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- CN100354634C CN100354634C CNB2004100748856A CN200410074885A CN100354634C CN 100354634 C CN100354634 C CN 100354634C CN B2004100748856 A CNB2004100748856 A CN B2004100748856A CN 200410074885 A CN200410074885 A CN 200410074885A CN 100354634 C CN100354634 C CN 100354634C
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Abstract
The present invention provides an instantaneous voltage detection circuit aiming at multiple power supply ends, which is used for detection aiming at an electronic system. The electronic system is provided with a first power supply end, a second power supply end, a third power supply end, a fourth power supply end, a first grounding end and a second grounding end. The circuit comprises a first device, a second device and a reset device, wherein the first device and the second device are respectively provided with a plurality of MOS transistors. When the electronic system is in normal operation, the voltage of the first power supply end is almost equal to the voltage of the second power supply end, the voltage of the third power supply end is almost equal to the voltage of the fourth power supply end, and the voltage of the first grounding end is almost equal to the voltage of the second grounding end. According to the instantaneous voltage detection circuit of the present invention, a positive or negative instantaneous voltage which occurs at the first power supply end, the second power supply end, the third power providing end and the fourth power supply end can be detected.
Description
Technical field
The present invention relates to a kind of instantaneous voltage detetion circuit (Transient voltage detecting circuit), in order to do detection at an electronic system (Electronic system), and especially, the present invention relates to a kind of like this instantaneous voltage detetion circuit, wherein this electronic system has multiple power source supply end (Powersupplies), according to instantaneous voltage detetion circuit of the present invention, betide the positive or negative instantaneous voltage (Transient voltage) in each power source supply end place in case can detect.
Background technology
General electronic system; especially integrated circuit; all can be ... wait and do not want the instantaneous voltage that takes place at surging (Surge), impulse disturbances (Glitch), superpotential (Overvoltage); take the self-protection measure; to avoid system to cause operating mistake because of above-mentioned instantaneous voltage; or even crash, or problem such as component wear.
The self-protection measure that electronic system is carried out at instantaneous voltage is at first valued in detecting instantaneous voltage rapidly, exactly.Known technology about instantaneous voltage detects please refer to United States Patent (USP) the 5th, 999, No. 392 patents.United States Patent (USP) the 5th, 999, No. 392 patent discloses a kind of automatic reset circuit (Resetting circuit) that detects transient potential variation function that has, in order to the ANOMALOUS VARIATIONS of current potential between power source supply end and the earth terminal (Ground) in the detected electrons system, with the homing action of executed in real time electronic system.
Along with electronic system is complicated day by day in design, existing electronic system possesses multiple power supply more, for system's domestic demand otherwise with the supply voltage element used.Yet, about detecting the known technology of instantaneous voltage, only be, or earth terminal, or the instantaneous voltage that takes place between single group of power end and the earth terminal is done detection at the single power supply feed end.Testing circuit for the instantaneous voltage that detects the generation of multiple power source supply end place simultaneously still is short of so far.
Therefore, need provide a kind of instantaneous voltage detetion circuit, can do detection at the multiple power source supply end in the same electronic system according to this instantaneous voltage detetion circuit.
In addition, must quote or with reference to the element of the power supply of this electronic system about detecting the known technology of instantaneous voltage, using mostly, for example, Sheffer stroke gate (NAND gate), rejection gate (NOR gate), not gate (NOT gate) ... etc.Cause, in case when instantaneous voltage takes place, must quote or, can't guarantee still to possess original electrical specification with reference to the element of the power supply of this electronic system.Also cause, use and to quote or with reference to the instantaneous voltage detetion circuit of the element of the power supply of this electronic system, its accuracy that detects instantaneous voltage quite makes us causing anxiety.
Therefore, be necessary to provide a kind of instantaneous voltage detetion circuit, according to each element in this instantaneous voltage detetion circuit, directly induction power supply changes, need not system held one stabilized power source.
Summary of the invention
The present invention is the defective in the above-mentioned known technology of solution and proposes a kind of instantaneous voltage detetion circuit, it can do detection at the multiple power source supply end in the same electronic system, and according to each element in this instantaneous voltage detetion circuit, directly induction power supply changes, need not system held one stabilized power source.
A fundamental purpose purport of the present invention is in providing a kind of instantaneous voltage detetion circuit, and in order to doing detection at an electronic system, and especially, this electronic system has multiple power source supply end.According to instantaneous voltage detetion circuit of the present invention, betide the positive or negative instantaneous voltage in each power source supply end place in case can detect.
The another object of the present invention purport is in a kind of instantaneous voltage detetion circuit that can monitor a plurality of power source supply ends simultaneously is provided, and especially, according to each element in the instantaneous voltage detetion circuit of the present invention, all need not quote or with reference to monitored power supply, thus, in case when instantaneous voltage takes place, according to each element in the instantaneous voltage detetion circuit of the present invention, still keep original electrical specification, and then detect this instantaneous voltage rapidly, exactly.
The instantaneous voltage detetion circuit of one preferred embodiment according to the present invention is in order to do detection at an electronic system.Especially, this electronic system has one first power source supply end, a second source feed end, one the 3rd power source supply end, one the 4th power source supply end, one the 5th power source supply end and one the 6th power source supply end.This instantaneous voltage detetion circuit comprises one first device, one second device and a resetting means.This first device comprises one the one the first kenel metal-oxide semiconductor (MOS) (MOS) transistor and one the one the second kenel MOS transistor.The one the first kenel MOS transistor are coupled to this first power source supply end.The one the second kenel MOS transistor are coupled between the one the first kenel MOS transistor and the 5th power source supply end, and with a gate coupled itself to the 3rd power source supply end.This first device and between the one the first kenel MOS transistor and the one the second kenel MOS transistor, provide one first output terminal.This second device comprises one the two the first kenel MOS transistor, one the three the first kenel MOS transistor and one the two the second kenel MOS transistor.The two the first kenel MOS transistor are coupled to this second source feed end, and with a gate coupled itself to this first output terminal.The three the first kenel MOS transistor are in parallel with the two the first kenel MOS transistor.The two the second kenel MOS transistor are coupled between the two the first kenel MOS transistor and the 6th power source supply end, and with a gate coupled itself to the 4th power source supply end.The one the first kenel MOS transistor are with gate coupled to a first node of itself.This first node places between the two the first kenel MOS transistor and the two the second kenel MOS transistor.This resetting means has an output that is coupled to a grid of the three the first kenel MOS transistor.This resetting means is in order to export a reset signal, and then the conducting the three the first kenel MOS transistor, to reset this instantaneous voltage detetion circuit, causing the voltage at this first node place is first logic state, and is locked in second logic state at the voltage of this first output.In case a negative instantaneous voltage betides the 3rd power source supply end place, the voltage of this first output is this first logic state with transition, and makes the voltage at this first node place that transition is this second logic state.In case a positive instantaneous voltage betides the 4th power source supply end place, the voltage at this first node place is this second logic state with transition, causes the voltage at this first output that transition is this first logic state.In case this positive instantaneous voltage betides this first power source supply end place, the one the first kenel MOS transistor will be switched on, and cause this first output terminal that transition is this first logic state.In case should betide this second source feed end place by negative instantaneous voltage, the one the first kenel MOS transistor will be switched on, and cause this first output terminal that transition is this first logic state.
The instantaneous voltage detetion circuit of one preferred embodiment according to the present invention further comprises one the 3rd device and one the 4th device.The 3rd device comprises one the four the first kenel MOS transistor, one the five the first kenel MOS transistor and one the three the second kenel MOS electricity is brilliant.The four the first kenel MOS transistor are coupled to this first power source supply end.The five the first kenel MOS transistor are in parallel with the four the first kenel MOS transistor.The three the second kenel MOS transistor are coupled between the four the first kenel MOS transistor and the 5th power source supply end, and with a gate coupled itself to the 3rd power source supply end.The 4th device comprises one the six the first kenel MOS transistor and one the four the second kenel MOS transistor.The six the first kenel MOS transistor are coupled to this second source feed end, and with itself gate coupled to a Section Point.This Section Point places between the four the first kenel MOS transistor and the three the second kenel MOS transistor.The four the second kenel MOS transistor are coupled between the six the first kenel MOS transistor and the 6th power source supply end, and with itself a gate coupled to the 4th power source supply end.The 4th device and between the six the first kenel MOS transistor and the four the second kenel MOS transistor, provide one second output terminal.The six the first kenel MOS transistor with itself a gate coupled to this second output terminal.This resetting means and be coupled to a grid of the four the first kenel MOS transistor with itself output, and export this reset signal, and then the conducting the four the first kenel MOS transistor, cause voltage to be this first logic state, and be locked in this second logic state at the voltage of this second output at this Section Point place.In case this positive instantaneous voltage betides the 3rd power source supply end place, the voltage at this Section Point place is this second logic state with transition, causes the voltage at this second output that transition is this first logic state.In case should betide the 4th power source supply end place by negative instantaneous voltage, the voltage of this second output is this first logic state with transition, and make the voltage at this Section Point place that transition is this second logic state.In case should betide this first power source supply end place by negative instantaneous voltage, the six the first kenel MOS transistor will be switched on, and cause the voltage at this second output that transition is this first logic state.In case this positive instantaneous voltage betides this second source feed end place, the six the first kenel MOS transistor will be switched on, and cause the voltage transition at this second output to be this first logic state.
Can be further understood by the following detailed description and accompanying drawings about the advantages and spirit of the present invention.
Description of drawings
Fig. 1 illustrates the instantaneous voltage detetion circuit 1 of one preferred embodiment according to the present invention.
Fig. 2 illustrates instantaneous voltage detetion circuit 2 according to yet another preferred embodiment of the present invention.
The main element label declaration:
1,2: 12: the first devices of instantaneous voltage detetion circuit
16: the three devices of 14: the second devices
18: the four devices 20: resetting means
VDD1: the first power source supply end VDD2: second source feed end
VDD3: the 3rd power source supply end VDD4: the 4th power source supply end
GND1: the 5th power source supply end GND2: the 6th power source supply end
F1, F2, F3, F4, F5, F6: the first kenel MOS transistor
S1, S2, S3, S4: the second kenel MOS transistor
Embodiment
The invention provides a kind of instantaneous voltage detetion circuit, the positive instantaneous voltage that takes place in order to the power source supply end place of detecting the electronic system (integrated circuit) that generally has multiple power supply, negative instantaneous voltage.Below will clearly point out spirit of the present invention and feature by preferred embodiment of the present invention is described in detail in detail.
See also Fig. 1, disclosed according to the present invention the basic framework of the instantaneous voltage detetion circuit 1 of one preferred embodiment.This instantaneous voltage detetion circuit 1 is in order to do detection at an electronic system (not being illustrated among the figure).Especially, this electronic system has one first power source supply end VDD1, a second source feed end VDD2, one the 3rd power source supply end VDD3, one the 4th power source supply end VDD4, one the 5th power source supply end GND1 and one the 6th power source supply end GND2.
What need statement is, during this electronic system normal operation, the voltage of this first power source supply end VDD1 equals the voltage of this second source feed end VDD2 haply, and for example, above-mentioned both are 3.3 volts (Volt).The voltage of the 3rd power source supply end VDD3 equals the voltage of the 4th power source supply end VDD4 haply, and for example, above-mentioned both are 1.8 volts.And the voltage of the 5th power source supply end GND1 equals the voltage of the 6th power source supply end GND2 haply, and the 5th power source supply end and the 6th power source supply end can be respectively an earth terminal.That is the power supply of this electronic system is symmetric arrangement.
As shown in Figure 1, this instantaneous voltage detetion circuit comprises one first device, 12,1 second device 14 and one resetting means (Resetting device) 20.
This first device comprises one the one the first kenel metal-oxide semiconductor (MOS) (Metal-oxidesemiconductor, MOS) transistor (transistor) F1 and one the one the second kenel MOS transistor S1.The one the first kenel MOS transistor F1 are coupled to this first power source supply end VDD1.The one the second kenel MOS transistor S1 are coupled between the one the first kenel MOS transistor F1 and the 5th power source supply end GND1, and are coupled to the 3rd power source supply end VDD3 with a grid (Gate) itself.This first device 12 and between the one the first kenel MOS transistor F1 and the one the second kenel MOS transistor S1, provide one first output terminal (Output terminal) OUT1.
This second device 14 comprises one the two the first kenel MOS transistor F2, one the three the first kenel MOS transistor F3 and one the two the second kenel MOS transistor S2.The two the first kenel MOS transistor F2 are coupled to this second source feed end VDD2, and with a gate coupled itself to this first output terminal OUT1.The three the first kenel MOS transistor F3 are in parallel with the two the first kenel MOS transistor F2.The two the second kenel MOS transistor S2 are coupled between the two the first kenel MOS transistor F2 and the 6th power source supply end GND2, and with a gate coupled to the four power source supply end VDD4 itself.As shown in Figure 1, this first node A places between the two the first kenel MOS transistor F2 and the two the second kenel MOS transistor S2.First node A also is coupled to the grid (Gate) of the one the first kenel MOS transistor F1.
As shown in Figure 1, this resetting means 20 has an output that is coupled to the grid of the three the first kenel MOS transistor F3.This resetting means 20 is in order to export a reset signal (Reset signal), and then the conducting the three the first kenel MOS transistor F3, to reset this instantaneous voltage detetion circuit 1, causing the voltage at this first node A place is first logic state, and is locked in second logic state at the voltage at this first output terminal OUT1 place.
In one embodiment, as shown in Figure 1, the described first kenel MOS transistor (F1, F2 and F3) is a P kenel MOS transistor, and the described second kenel MOS transistor (S1, S2) is a N kenel MOS transistor.At this moment, the reset signal exported of this resetting means 20 is a drop-down signal (Pull-down signal).This first logic state is high logic (Logic HIGH), and this second logic state is low logic (Logic LOW).
With the described first kenel MOS transistor (F1, F2 and F3) is P kenel MOS transistor, and the described second kenel MOS transistor (S1, S2) is a N kenel MOS transistor, and this reset signal is that pulldown signal is an example.The pulldown signal that this resetting means 20 is exported will conducting the 3rd P-MOS transistor F3, to reset this instantaneous voltage detetion circuit 1.At this moment, the voltage at this first node A place is high logic, and described MOS transistor (F1, F2, S1 and S2) formation one lock-in circuit, causes being low logic at the voltage of this first output terminal OUT1.If will change voltage state of living at this first output terminal OUT1, then the voltage of the 3rd power source supply end VDD3 must be starkly lower than the voltage of the 4th power source supply end VDD4, or the voltage of the 4th power source supply end VDD4 must be apparently higher than the voltage of the 3rd power source supply end VDD3, or the voltage of this first power source supply end VDD1 must be apparently higher than the voltage of this second source feed end VDD2, or the voltage of this second source feed end VDD2 must be starkly lower than the voltage of this second source feed end VDD2.
In case a negative instantaneous voltage occurs in the 3rd power source supply end VDD3 place, a N kenel MOS transistor S1 will be cut off, and the voltage at this first output terminal OUT1 place is high logic with transition, and make the voltage at this first node A place that transition is low logic.Immediately, after the voltage at the 3rd power source supply end VDD3 place recovers normal level, voltage at this first output terminal OUT1 place also can't revert to low logic, that is to say that the abnormal voltage (negative instantaneous voltage) that this instantaneous voltage detetion circuit 1 can will betide the 3rd power source supply end VDD3 place is noted.
In case a positive instantaneous voltage betides the 4th power source supply end VDD4 place, the voltage at this first node A place is low logic with transition, and causing the voltage at this first output terminal OUT1 place is high logic with transition.Immediately, after the voltage at the 4th power source supply end VDD4 place recovers normal level, voltage at this first output terminal OUT1 place also can't revert to low logic, that is to say that the abnormal voltage (positive instantaneous voltage) that this instantaneous voltage detetion circuit 1 can will betide the 4th power source supply end VDD4 place is noted.(the same VDD3 of describing method, just about opposite)
In case this positive instantaneous voltage betides this first power source supply end VDD1 place, a P kenel MOS transistor F1 will be switched on, and causing the voltage at this second output terminal OUT2 place is high logic with transition.Immediately, after the voltage at this first power source supply end VDD1 place recovers normal level, voltage at this second output terminal OUT2 place also can't revert to low logic, that is to say that the abnormal voltage (positive instantaneous voltage) that this instantaneous voltage detetion circuit 1 can will betide this first power source supply end VDD1 place is noted.
In case should betide this second source feed end VDD2 place by negative instantaneous voltage, the one P kenel MOS transistor F2 will be cut off, this first node A is low logic with transition, then a P kenel MOS transistor F1 will be switched on, and causing the voltage transition at this second output terminal OUT2 place is high logic.Immediately, after the voltage at this second source feed end VDD2 place recovers normal level, voltage at this second output terminal OUT2 place also can't revert to low logic, that is to say that the abnormal voltage (negative instantaneous voltage) that this instantaneous voltage detetion circuit 1 can will betide this second source feed end VDD2 place is noted.
In order to detect positive instantaneous voltage, the negative instantaneous voltage that betides the 4th power source supply end VDD4 place, the negative instantaneous voltage that betides this first power source supply end VDD1 place that betides the 3rd power source supply end VDD3 place, the positive instantaneous voltage that betides this second source feed end VDD2 place, consult Fig. 1 equally, instantaneous voltage detetion circuit 1 according to the present invention further comprises one the 3rd device, 16 and 1 the 4th device 18.
The 3rd device 16 comprises one the four the first kenel MOS transistor F4, one the five the first kenel MOS transistor F5 and the one the three the second brilliant S3 of kenel MOS electricity.The four the first kenel MOS transistor F4 are coupled to this first power source supply end VDD1.The five the first kenel MOS transistor F5 are in parallel with the four the first kenel MOS transistor F4.The three the second kenel MOS transistor S3 are coupled between the four the first kenel MOS transistor F4 and the 5th power source supply end GND1, and with a gate coupled itself to the 3rd power source supply end VDD3.
The 4th device 18 comprises one the six the first kenel MOS transistor F6 and one the four the second kenel MOS transistor S4.The six the first kenel MOS transistor F6 are coupled to this second source feed end VDD2, and with itself gate coupled to a Section Point B.This Section Point B places between the four the first kenel MOS transistor F4 and the three the second kenel MOS transistor S3.The four the second kenel MOS transistor S4 are coupled between the six the first kenel MOS transistor F6 and the 6th power source supply end GND2, and with itself a gate coupled to the 4th power source supply end VDD4.The 4th device 18 and between the six the first kenel MOS transistor F6 and the four the second kenel MOS transistor S4, provide one second output terminal OUT2.
This resetting means 20 and be coupled to the grid of the four the first kenel MOS transistor F4 with itself output, and export this reset signal, and then the conducting the four the first kenel MOS transistor F4, cause voltage to be this first logic state, and be locked in this second logic state at the voltage of this second output at this Section Point B place.
In one embodiment, as shown in Figure 1, the described first kenel MOS transistor (F4, F5 and F6) is a P kenel MOS transistor, and the described second kenel MOS transistor (S3, S4) is a N kenel MOS transistor.At this moment, the reset signal exported of this resetting means 20 is a drop-down signal.This first logic state is high logic, and this second logic state is low logic.
With the described first kenel MOS transistor (F4, F5 and F6) is P kenel MOS transistor, and the described second kenel MOS transistor (S3, S4) is a N kenel MOS transistor, and this reset signal is that pulldown signal is an example.The pulldown signal that this resetting means 20 is exported will conducting the 4th P-MOS transistor F4, to reset this instantaneous voltage detetion circuit 1.At this moment, the voltage at this Section Point B place is high logic, and described MOS transistor (F5, F6, S3 and S4) formation one lock-in circuit, causes being low logic at the voltage of this second output terminal OUT2.If will change voltage state of living at this second output terminal OUT2, then the voltage of the 3rd power source supply end VDD3 must be apparently higher than the voltage of the 4th power source supply end VDD4, or the voltage of the 4th power source supply end VDD4 must be starkly lower than the voltage of the 3rd power source supply end VDD3, or the voltage of this first power source supply end VDD1 must be starkly lower than the voltage of this second source feed end VDD2, or the voltage of this second source feed end VDD2 must be apparently higher than the voltage of this second source feed end VDD2.
In case a positive instantaneous voltage betides the 3rd power source supply end VDD3 place, the 3rd N kenel MOS transistor S3 will force this Section Point B transition to be low logic, and then the voltage transition that changes this second output terminal OUT2 place is high logic (first node A, first go out to hold the state of OUT1 constant) at this moment.Immediately, after the voltage at the 3rd power source supply end VDD3 place recovers normal level, voltage at this second output terminal OUT2 place also can't revert to low logic, that is to say that the abnormal voltage (negative instantaneous voltage) that this instantaneous voltage detetion circuit 1 can will betide the 3rd power source supply end VDD3 place is noted.
In case should betide the 4th power source supply end VDD4 place by negative instantaneous voltage, the voltage at this second output terminal OUT2 place is high logic with transition, and make the voltage at this Section Point B place that transition is low logic.Immediately, after the voltage at the 4th power source supply end VDD4 place recovers normal level, voltage at this second output terminal OUT2 place also can't revert to low logic, that is to say that the abnormal voltage (negative instantaneous voltage) that this instantaneous voltage detetion circuit 1 can will betide the 4th power source supply end VDD4 place is noted.
In case should betide this first power source supply end VDD1 place by negative instantaneous voltage, the 5th P kenel MOS transistor F5 will be cut off, cause Node B that transition is low logic, and impel the 6th P kenel MOS transistor F6 conducting, making the second output terminal OUT2 transition is high logic.Immediately, after the voltage at this first power source supply end VDD1 place recovers normal level, voltage at this second output terminal OUT2 place also can't revert to low logic, that is to say that the abnormal voltage (negative instantaneous voltage) that this instantaneous voltage detetion circuit 1 can will betide this first power source supply end VDD1 place is noted.
In case this positive instantaneous voltage betides this second source feed end VDD2 place, the 6th P kenel MOS transistor F6 will be switched on, causing this second output terminal OUT1 is high logic with transition, and by the 5th P kenel MOS transistor F5, makes this Section Point B transition be low logic.Immediately, after the voltage at this second source feed end VDD2 place recovers normal level, voltage at this second output terminal OUT2 place also can't revert to low logic, that is to say that the abnormal voltage (positive instantaneous voltage) that this instantaneous voltage detetion circuit 1 can will betide this second source feed end VDD2 place is noted.
It should be noted that when abnormal voltage takes place, because testing circuit adopts symmetric design, so all can detect no matter generating positive and negative voltage changes.
In another specific embodiment, instantaneous voltage detetion circuit 2 as shown in Figure 2, the principle of operation of its circuit framework and each element is close with above-mentioned explanation to instantaneous voltage detetion circuit 1.Different is that in this instantaneous voltage detetion circuit 2, the described first kenel MOS transistor is a N kenel MOS transistor, and the described second kenel MOS transistor is a P kenel MOS transistor.And this first power source supply end VDD1 replaces mutually with the position of the 5th power source supply end GND1.This second source feed end VDD2 replaces mutually with the position of the 6th power source supply end GND2.At this moment, the reset signal exported of this resetting means 20 is to draw signal (Pull-up signal) on one.In another specific embodiment.The 3rd power source supply end VDD3 among Fig. 2 also can be replaced by another earth terminal, and the 4th power source supply end VDD4 among Fig. 2 also can be replaced by another earth terminal.
Significantly, can do monitoring at a plurality of power source supply ends simultaneously according to instantaneous voltage detetion circuit of the present invention.Basically use latched comparator (Latchcomparator) as detecting unit according to instantaneous voltage detetion circuit of the present invention, can reduce the size of whole detection circuit effectively.As indicated above, this first device 12 is identity element, the size that also can reduce the whole detection circuit effectively with these second device, 14 required resetting means that use 20 and the 3rd device the 16, the 4th device 18 required resetting means that use 20.
What need statement is, each element according to instantaneous voltage detetion circuit of the present invention comprises this resetting means, all need not quote or with reference to the power supply of this electronic system.Therefore, in case when instantaneous voltage took place, each element according in the instantaneous voltage detetion circuit of the present invention still kept original electrical specification, and then detects this instantaneous voltage rapidly, exactly.In addition, if will further reduce size according to instantaneous voltage detetion circuit of the present invention, need not use electrostatic discharge specifications (ESD rule), the resistance of the little resistance value of only need connecting respectively at each power source supply end place gets final product, and resistance value is about 25～100 ohm (Ω).
By the above detailed description of preferred embodiments, can know more and describe feature of the present invention and spirit, and be not to come category of the present invention is limited with the above-mentioned preferred embodiment that is disclosed.On the contrary, its objective is that hope can contain in the category that is arranged in the claim that the present invention will apply for of various changes and tool equivalence.
Claims (6)
1. instantaneous voltage detetion circuit, this circuit is done detection at an electronic system, this electronic system has one first power source supply end, one second source feed end, one the 3rd power source supply end, one the 4th power source supply end, one the 5th power source supply end and one the 6th power source supply end, this circuit comprises: one first device, this first device comprises one the one the first kenel metal oxide semiconductor transistor and one the one the second kenel metal oxide semiconductor transistor, the one the first kenel metal oxide semiconductor transistors are coupled to this first power source supply end, the one the second kenel metal oxide semiconductor transistors be coupled between the one the first kenel metal oxide semiconductor transistors and the 5th power source supply end and with a gate coupled itself to the 3rd power source supply end, this first device and between the one the first kenel metal oxide semiconductor transistors and the one the second kenel metal oxide semiconductor transistors, provide one first output terminal;
One second device, this second device comprises one the two the first kenel metal oxide semiconductor transistor, one the three the first kenel metal oxide semiconductor transistor and one the two the second kenel metal oxide semiconductor transistor, the two the first kenel metal oxide semiconductor transistors be coupled to this second source feed end and with a gate coupled itself to this first output terminal, the three the first kenel metal oxide semiconductor transistors are in parallel with the two the first kenel metal oxide semiconductor transistors, the two the second kenel metal oxide semiconductor transistors be coupled between the two the first kenel metal oxide semiconductor transistors and the 6th power source supply end and with a gate coupled itself to the 4th power source supply end, the one the first kenel metal oxide semiconductor transistors are with gate coupled to a first node of itself, and this first node places between the two the first kenel metal oxide semiconductor transistors and the two the second kenel metal oxide semiconductor transistors; And
One resetting means, this resetting means has an output that is coupled to a grid of the three the first kenel metal oxide semiconductor transistors, this resetting means is in order to export a reset signal, and then the conducting the three the first kenel metal oxide semiconductor transistors, causing the voltage at this first node place is one first logic state, and is locked in one second logic state at the voltage of this first output;
Wherein, in case a negative instantaneous voltage betides the 3rd power source supply end place, the voltage at this first node place is this second logic state with transition, causes the voltage at this first output that transition is this first logic state;
Wherein, in case a positive instantaneous voltage betides the 4th power source supply end place, the voltage at this first node place is this second logic state with transition, causes the voltage at this first output that transition is this first logic state;
Wherein, in case this positive instantaneous voltage betides this first power source supply end place, the one the first kenel metal oxide semiconductor transistors will be switched on, and cause this first output terminal that transition is this first logic state; And
Wherein, in case should betide this second source feed end place by negative instantaneous voltage, the one the first kenel metal oxide semiconductor transistors will be switched on, and cause this first output terminal that transition is this first logic state.
2. instantaneous voltage detetion circuit as claimed in claim 1 further comprises:
One the 3rd device, the 3rd device comprises one the four the first kenel metal oxide semiconductor transistor, one the five the first kenel metal oxide semiconductor transistor and one the three the second kenel metal oxide semiconductor transistor, the four the first kenel metal oxide semiconductor transistors are coupled to this first power source supply end, the five the first kenel metal oxide semiconductor transistors are in parallel with the four the first kenel metal oxide semiconductor transistors, the three the second kenel metal oxide semiconductor transistors be coupled between the four the first kenel MOS transistor and the 5th power source supply end and with a gate coupled itself to the 3rd power source supply end; And
One the 4th device, the 4th device comprises one the six the first kenel metal oxide semiconductor transistor and one the four the second kenel metal oxide semiconductor transistor, the six the first kenel metal oxide semiconductor transistors are coupled to this second source feed end and with itself gate coupled to a Section Point, this Section Point places between the four the first kenel metal oxide semiconductor transistors and the three the second kenel metal oxide semiconductor transistors, the four the second kenel metal oxide semiconductor transistors be coupled between the six the first kenel metal oxide semiconductor transistors and the 6th power source supply end and with itself a gate coupled to the 4th power source supply end, the 4th device and between the six the first kenel metal oxide semiconductor transistors and the four the second kenel metal oxide semiconductor transistors, provide one second output terminal, the six the first kenel metal oxide semiconductor transistors with itself a gate coupled to this second output terminal, wherein, this resetting means and be coupled to a grid of the four the first kenel MOS transistor with itself output, and export this reset signal and then the conducting the four the first kenel MOS transistor, cause voltage to be this first logic state, and be locked in this second logic state at the voltage of this second output at this Section Point place; And
Wherein, in case this positive instantaneous voltage betides the 3rd power source supply end place, the voltage at this Section Point place is this second logic state with transition, causes the voltage at this second output that transition is this first logic state;
Wherein, in case should betide the 4th power source supply end place by negative instantaneous voltage, the voltage at this Section Point place is this second logic state with transition, causes the voltage at this second output that transition is this first logic state;
Wherein, in case should betide this first power source supply end place by negative instantaneous voltage, the six the first kenel metal oxide semiconductor transistors will be switched on, and cause the voltage at this second output that transition is this first logic state; And
Wherein, in case this positive instantaneous voltage betides this second source feed end, the six the first kenel metal oxide semiconductor transistors will be switched on, and cause the voltage transition at this second output to be this first logic state.
3. instantaneous voltage detetion circuit as claimed in claim 2, wherein during this electronic system normal operation, the voltage of this first power source supply end equals the voltage of this second source feed end haply, the voltage of the 3rd power source supply end equals the voltage of the 4th power source supply end haply, and the voltage of the 5th power source supply end equals the voltage of the 6th power source supply end haply.
4. instantaneous voltage detetion circuit as claimed in claim 3, wherein this reset signal is a drop-down signal, the described first kenel metal oxide semiconductor transistor is a P kenel metal oxide semiconductor transistor, the described second kenel metal oxide semiconductor transistor is a N kenel metal oxide semiconductor transistor, this first logic state is high logic, this second logic state is low logic, and the 5th power source supply end and the 6th power source supply end are respectively an earth terminal.
5. instantaneous voltage detetion circuit as claimed in claim 3, wherein this reset signal is to draw signal on one, the described first kenel metal oxide semiconductor transistor is a N kenel metal oxide semiconductor transistor, the described second kenel metal oxide semiconductor transistor is a P kenel metal oxide semiconductor transistor, this first logic state is low logic, this second logic state is high logic, and this first power source supply end and this second source feed end are respectively an earth terminal.
6. instantaneous voltage detetion circuit as claimed in claim 5, wherein the 3rd power source supply end and the 4th power source supply end are respectively an earth terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100748856A CN100354634C (en) | 2004-08-30 | 2004-08-30 | Instantaneous voltage detection circuit to multiple power source supply end |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100748856A CN100354634C (en) | 2004-08-30 | 2004-08-30 | Instantaneous voltage detection circuit to multiple power source supply end |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1743853A CN1743853A (en) | 2006-03-08 |
| CN100354634C true CN100354634C (en) | 2007-12-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100748856A Expired - Fee Related CN100354634C (en) | 2004-08-30 | 2004-08-30 | Instantaneous voltage detection circuit to multiple power source supply end |
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| Country | Link |
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| CN (1) | CN100354634C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI706621B (en) * | 2019-03-18 | 2020-10-01 | 智原科技股份有限公司 | Circuit system with plural power domains |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3987393A (en) * | 1971-06-17 | 1976-10-19 | Litton Industrial Products, Inc. | Line voltage monitor |
| CN2031172U (en) * | 1987-10-14 | 1989-01-18 | 金小团 | Over-voltage protector |
| US5465190A (en) * | 1992-07-16 | 1995-11-07 | Sgs-Thomson Microelectronics S.A. | Circuit and method for protecting power components against forward overvoltages |
| US5999392A (en) * | 1998-06-26 | 1999-12-07 | Industrial Technology Research Institute | Reset circuit with transient detection function |
| US6538866B1 (en) * | 1999-05-25 | 2003-03-25 | Hitachi, Ltd. | Circuit for protecting a load from an overvoltage |
-
2004
- 2004-08-30 CN CNB2004100748856A patent/CN100354634C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3987393A (en) * | 1971-06-17 | 1976-10-19 | Litton Industrial Products, Inc. | Line voltage monitor |
| CN2031172U (en) * | 1987-10-14 | 1989-01-18 | 金小团 | Over-voltage protector |
| US5465190A (en) * | 1992-07-16 | 1995-11-07 | Sgs-Thomson Microelectronics S.A. | Circuit and method for protecting power components against forward overvoltages |
| US5999392A (en) * | 1998-06-26 | 1999-12-07 | Industrial Technology Research Institute | Reset circuit with transient detection function |
| US6538866B1 (en) * | 1999-05-25 | 2003-03-25 | Hitachi, Ltd. | Circuit for protecting a load from an overvoltage |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1743853A (en) | 2006-03-08 |
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