CN100353290C - Power saving method employing scan chain and boundary scan - Google Patents

Abstract

The present invention provides a power saving method and a power saving circuit in a synchronizing logic ASIC for reducing a management layout of the power saving circuit. Scanning chains and a boundary scanning mechanism in the synchronizing logic ASIC is used and modified, the current state of an internal memory element in the synchronizing logic ASIC is moved to an external memory body, a main output value in a powering-off block is kept in a memory element in a boundary scanning circuit. The powering-off design is effective in a synchronizing logic circuit with a positive-negative device as a main and largely reduces the circuit management layout.

Description

Use the electricity saving method of scan chain and boundary scan

Technical field

The method of electric leakage falls in the relevant what of the present invention in synchronous logic ASIC (Application Specific IC, special integrated circuit), refer in particular to use scan chain (Scan Chain) and boundary scan technology such as (IEEE 1149.1) and the method for power saving.

Background technology

The portable equipment all for what (as PDA, portable computer, mobile phone etc.), the power saving of integrated circuit is more and more important.The power consumption of these equipments can be divided into two big categories: dynamic power consumption (electric power that consumes during switch, P=CV ²F) and static power consumption (i.e. electric leakage).

To the what dynamic power consumption, used two kinds of technology mats reduction C, V or f (integral capacitor, institute's voltage supplied or frequency of operation) and minimizing power consumption:

1. improvement process technique makes institute's voltage supplied and circuit size/electric capacity etc. all reduce (promptly reducing C and V).

2. shutoff clock signal is to reduce switching frequency f.

To what static power consumption (i.e. electric leakage), used following method:

3. the improvement of element/circuit, in inferior micron and portable circuit design, electric leakage becomes the principal element of power consumption, and the circuit designer uses cut-in voltage V _T(cut-in voltage) higher element and reduce electric leakage improves static power consumption.

4. power cutoff turn-offs its power supply to the obsolete circuit of what.

To above-mentioned the third method of what, high cut-in voltage V _TMay increase short-circuit current, thereby consume more dynamic power.And first method and the third method must change process technique, cost is high and progress is slower, major part does not have the IC design corporation of wafer factory can't bear its expense and development time, therefore can only use prior art to reach saving electric power, so second method and the 4th kind of method do not have the IC design corporation of wafer factory than controlling budget to what.Second method is the preferred approach of dynamic electricity-saving, and the 4th kind of method then is to reduce the best approach of electric leakage.

Second method is known method, and is extensive use of, and (for example Synopsys ' PowerCompiler) to have many cad tools that the designing technique of turn-offing clock signal can be provided.

The working time of portable apparatus 95% all is to be equipped with just (standby) pattern, and therefore electric leakage is one of principal element of power consumption, but electric leakage can't mat be turn-offed clock signal (second method) and stopped.The 4th kind of method power cutoff then is the preferred plan of the static power saving of portable apparatus.But the power cutoff of the 4th kind of method is not extensive use of as yet, reason such as following 2 points:

1. power cutoff needs extra storer, control circuit and wiring to store the content of turn-offing square, and this involves too many hardware management design.

2. the program of power cutoff/energized is very trifling.

By the above-mentioned two kinds of shortcomings of what, though power cutoff is well-known, seldom use, therefore have the space of improvement.

Summary of the invention

Therefore the present invention's purpose is providing a kind of method and circuit, utilizes existing scan chain (Scan Chains) and boundary scan (Boundary Scan, IEEE 1149.1) technology with power cutoff, reduces the hardware design of power saving among the synchronous logic ASIC.

A kind of electricity saving method that uses scan chain and boundary scan of the present invention, have among the synchronous logic ASIC of scan chain circuits and boundary scan chain one, the controller of packing into, allow the org_s_mode of scan chain circuits and boundary scan chain, org_s_enable, org_bs_mode, org_bs_enable, power_off, clock and reset signal are imported this controller and are produced one group of new control signal s_mode, s_enable, bs_mode, bs_enable, pw_switch, scan_clock, bs_clock, mem_if, with following process control sweep circuit and boundary scan chain:

A) when synchronous logic ASIC power cutoff:

1) clock signal of synchronous logic ASIC is turn-offed by elder generation;

2) output with the main output terminal of synchronous logic ASIC is stored in the memory element of boundary scan chain, then the input end of an external circuit is switched to the memory element of boundary scan chain from this main output terminal;

3) with scan chain circuits the current state of the internal memory element of synchronous logic ASIC is moved out to an external memory storage;

4) power supply of shutoff synchronous logic ASIC;

B) when synchronous logic ASIC energized:

1) energized and initialization are turned off circuit;

2) numerical value that external memory storage is stored is moved back into the internal memory element of synchronous logic ASIC via scan chain circuits;

3) input end of external circuit is switched to this main output terminal from the memory element of boundary scan chain;

4) start clock signal.

Description of drawings

Fig. 1 is the synoptic diagram of one scan chain circuit.

Fig. 2 is the synoptic diagram of border scanning (IEEE 1149.1) circuit.

Fig. 3 is the synoptic diagram that merges scan chain circuits and boundary scan (IEEE1149.1) circuit in synchronous logic ASIC.

Fig. 4 illustrates the process flow diagram of power cutoff/energized program that the present invention plans.

Fig. 5 illustrates the calcspar of control circuit of the present invention.

Embodiment

Please refer to Fig. 1, a scan chain of producing test is shown represents circuit.In a synchronous logic ASIC, scan chain circuits will dispose along main circuit, and main circuit comprises many combinational logic circuits 1 and many memory elements 2 (for example flip-flop, displacement working storage).Scan chain circuits comprises multiplexer 3 and multiplexer 4, and multiplexer 3 has two inputs " test 31 " reach " work 32 ", multiplexer 4 has two inputs " scan clock signal 41 " reach " mainly clock signal 42 ".When the control signal s_enable 33 of multiplexer 3 and multiplexer 4 is electronegative potential with s_mode43, " work 32 " with " main clock signal 42 " will input to synchronous logic ASIC and do normal operation; When the control signal s_enable 33 of multiplexer 3 and multiplexer 4 is noble potential with s_mode 43, circuit enters scan pattern and does production test, " scan clock signal 41 " will replace " main clock signal 42 " and import among the synchronous logic ASIC, the data of " test 31 " will move into memory element 2 (for example flip-flop, displacement working storage), walk around combinational logic circuit 1, right Hou is shifted out the production test that output port 20 is made synchronous logic ASIC through each memory element 2 step by step.

With reference to figure 2, when the Test Design function, a to-be-measured cell 5 with border scanning (IEEE1149.1) mechanism (shadow region) around and store/observe the signal that main output terminal 52 is exported.Use bs_clock 59 and bs_enable 54 signals that test data 58 is imported main input end 51 via multiplexer 55, the signal that the main output terminal 52 of to-be-measured cell 5 is exported is then stored by memory element 57, and right Hou sees through boundary scan mechanism and shifts out.Boundary scan mechanism is the design in order to test to-be-measured cell 5.

Fig. 3 illustrates one embodiment of the invention, with the combination of existing scan chain and boundary scan (IEEE1149.1) and around a square 8 of desiring power cutoff.Scan chain circuits and boundary scan chain are circuit built-in in the integrated circuit of all portable applications, and the present invention just utilizes scan chain circuits and boundary scan chain to make the usefulness of power saving.The present invention uses scan chain circuits to deposit the content of memory element in the square 8 of a desire power cutoff in an external memory storage 6, the s_enable 33 and s_mode 43 of multiplexer 3 and multiplexer 4 are pulled into noble potential, and the square 8 of desiring power cutoff just enters scan pattern.The boundary condition that the present invention uses boundary scan chain will desire the square 8 of power cutoff deposits an external circuit 7 in.

Fig. 4 (a) illustrates the power cutoff program that the present invention plans.

The first step is that the clock signal of desiring the square 8 of power cutoff is turn-offed (step 91); Next is mainly to export the memory element (flip-flop) 57 that 52 signals of being exported deposit IEEE.1149.1 (boundary scan) in, and right Hou switches to boundary scan memory element (flip-flop) 57 (steps 92) with the input end of external circuit 7 from main output 52 (promptly from desiring the square 8 of power cutoff); And the current state of internal memory element (flip-flop) 2 is seen through scan chain be moved out to external memory storage 6 (step 93); One step of Hou then is the power supply (step 94) that turn-offs square 8.

What is returned to normal mode of operation with the circuit of power cutoff, and Fig. 4 (b) illustrates the program of energized.At first be that energized and initialization are turned off circuit (step 95); Next is to see through scan chain the value of the external memory storage 6 that stores is moved back into inner flip-flop 2 (step 96); The signal that the 3rd step then will switch to external circuit 7 rotates back into main output terminal 52 (step 97) from boundary scan memory element (flip-flop) 57; Hou is connected clock enabling signal square 8 and is got back to normal operation (step 98).

The method of power cutoff must be carried out following two kinds of tasks: the content replication that at first will desire all memory elements in the square 8 of power cutoff is to an external memory storage 6 (another group flip-flop, RAM or any other memory element), and duty can be recovered in Hou is come the program of energized.Secondly, the method for power cutoff will make the output of the main output terminal 52 of the square 8 of desiring power cutoff float, because these inputs of floating do not allow in the IC design, so need extra hardware to keep original signal, please consult Fig. 3 once more.

In order to reach two kinds of tasks of power cutoff, Fig. 5 illustrates the design of a controller 9, and this controller 9 will be collected the original signal of scan chain and boundary scan and produce one group of new control signal to reach the application of power saving.

The original signal of scan chain and boundary scan is to be used for production test and design test respectively, but pass through test Hou at product, the original signal of scan chain and boundary scan all is fixed as noble potential or fixing what electronegative potential, in the life cycle of product, do not re-use, therefore must produce the usefulness of one group of new control signal according to the original signal of scan chain and boundary scan for power saving.The original signal of scan chain and boundary scan comprises org_s_mode, org_s_enable, and org_bs_mode, org_bs_enable is shown in Fig. 5 controller 9 left sides.Power_off, clock and reset signal also are arranged in Fig. 5 controller left side with indicating control 9.

The output connecting pin s_mode 43 on controller 9 the right switches the internal memory element 2 of desiring the square 8 of power cutoff between three kinds of work patterns: normal operation pattern, the low power mode that turn-offs clock signal and immigration/shift out pattern.S_mode 43 is bus-bar formulas, as long as memory element 2 numbers of scan chain change, just must adjust controller 9, makes its output signal can meet time requirement.

S_enable 33 switches the inside information paths, make memory element 2 can from " test 31 " or " work 32 " obtain different inputs.

Bs_mode 53 determines pinning clock signal or the main battery saving mode of exporting when handoff boundary scans.Bs_enable 54 is except that keeping with org_bs_enable is identical, because this signal is when power saving, the output of square 8 need switch to memory element 57, so external circuit 7 can be obtained output valve forever.

Pw_switch 61 control power switches.

Scan_clock 41 provides the usefulness of scan clock signal for internal scan chain.

Bs_clock 59 provides the clock signal as boundary scan memory element (flip-flop) 57 by bs_mode 53 controls.

Mem_if 60 is external memory storage 6 control interfaces, and external memory storage 6 forms different to what must change external memory storage 6 interfaces.

Can replace controller 9 shown in Figure 5 with a CPU who includes.

The inventive method utilizes existing circuit/technology to reach purpose of power saving, needn't set up too many circuit.

Spirit of the present invention and scope only by following claim decision, are not subjected to the restriction of the foregoing description.

Claims (1)

1. electricity saving method that uses scan chain and boundary scan, have among the synchronous logic ASIC of scan chain circuits and boundary scan chain one, the controller of packing into, allow the org_s_mode of scan chain circuits and boundary scan chain, org_s_enable, org_bs_mode, org_bs_enable, power_off, clock and reset signal are imported this controller and are produced one group of new control signal s_mode, s_enable, bs_mode, bs_enable, pw_switch, scan_clock, bs_clock, mem_if, with following process control sweep circuit and boundary scan chain:

A) when synchronous logic ASIC power cutoff:

1) clock signal of synchronous logic ASIC is turn-offed by elder generation;

2) output with the main output terminal of synchronous logic ASIC is stored in the memory element of boundary scan chain, then the input end of an external circuit is switched to the memory element of boundary scan chain from this main output terminal;

3) with scan chain circuits the current state of the internal memory element of synchronous logic ASIC is moved out to an external memory storage;

4) power supply of shutoff synchronous logic ASIC;

B) when synchronous logic ASIC energized:

1) energized and initialization are turned off circuit;

2) numerical value that external memory storage is stored is moved back into the internal memory element of synchronous logic ASIC via scan chain circuits;

3) input end of external circuit is switched to this main output terminal from the memory element of boundary scan chain;

4) start clock signal.

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