JP4384970B2 - Power saving method using scan chain and boundary scan - Google Patents

Description

  The present invention relates to a method for reducing leakage in an application specific integrated circuit (ASIC) (hereinafter referred to as “ASIC”), and more particularly to a scan chain and a boundary scan (referred to as “scan chain” and “boundary scan”). The present invention relates to a power saving method using a technique such as IEEE 1149.1).

For portable PDAs, notebook computers, mobile phones, etc., power saving in integrated circuits is becoming increasingly important. The power consumption of these portable devices can be divided into two types: dynamic power consumption and static power consumption (leakage). Here, the dynamic power consumption P is power consumed during opening and closing, and is defined as P = CV ² f using the entire capacitance C, supply voltage V, and working frequency f.

The dynamic power consumption applies the technology represented by the following two (1) and (2) to reduce the power consumption by reducing the above C, V, or f.
(1) Reduce supply voltage, circuit area / capacitance, etc. (ie, reduce C and V) by improving manufacturing technology.
(2) The clock is closed to reduce the working frequency f.

On the other hand, the following methods (3) and (4) are typically used for reducing static power consumption (that is, leakage).
(3) Due to improvements in equipment / circuits, since leakage is a major factor in power consumption in deep submicron and portable circuit designs, use elements with high cut-in voltage (V _T ). Reduce leakage and improve static power consumption.
(4) Turn off power to unused circuits.

In the method (3), the high cut-in voltage (V _T ) increases the short circuit current and requires more dynamic power consumption. Moreover, since (1) and (3) must improve process technology, cost is high and improvement requires time. Therefore, in order to achieve power saving using the existing technology, it is preferable to improve the points (2) and (4). Note that (2) is an optimum method for reducing dynamic power consumption, and (4) is an optimum method for reducing static power consumption.

  Here, it is generally considered that 95% of the working time of the portable electronic device device is in the standby mode, and thus leakage is one of the main causes of power consumption. Since the electric leakage cannot be terminated by the method (2) relating to the closed clock signal, the method (4) by closing the power supply is the optimum method for reducing the static power consumption of the portable electronic device.

As for the prior art that enables power saving of an integrated circuit by turning on and off the power supply, for example, in prior art document 1 (Patent Document 1: Japanese Patent Application Laid-Open No. 08-054954), an input detection circuit and a timer are provided and an operation flag is turned on and off. An invention related to an integrated circuit having a power function is disclosed in Prior Art Document 2 (Patent Document 2: Japanese Patent Application Laid-Open No. 2002-312073) in which the recovery period is shortened while a counter for outputting a reset signal can be used for general purposes. Thus, inventions relating to power-saving integrated circuits that can also reduce power consumption are described.
Japanese Patent Application Laid-Open No. 08-054954 JP 2002-312073 A

However, although there is an example like the above-mentioned prior art document, generally the method of closing the power source is not widely used. This is mainly due to the following reasons.
1. In order to shut down the power supply, it is necessary to prepare a memory, a control circuit, and a conductor separately, and to save the contents of the power-off block, so there is too much hardware to be added.
2. The power-off / on process is insignificant.

  The reason for this is that, for example, for the integrated circuit described in the prior art document 1, an input detection circuit or the like is required separately from the main circuit in order to enable fine power consumption control. It can also be seen that it is necessary to prepare a power-saving control block having a time measuring means separately from the CPU or the like.

  Therefore, the present invention provides a completely new power saving method that uses existing scan chain and boundary scan (IEEE 1149.1) technology to shut down the power supply, so that there is minimal or no hardware to add. It is an object of the present invention to provide a method and a circuit that can save power and reduce the need for power saving hardware design that is usually performed separately in an ASIC.

  Based on the above problems, the present inventor, after earnestly examining, inputs scan chain and boundary scan circuit current org_s_mode, org_s_enable, org_bs_mode, org_bs_enable, power_off, clock and reset signals to the power saving controller in the ASIC, By generating a set of new control signals s_mode, s_enable, bs_mode, bs_enable, pw_switch, scan_clock, bs_clock and mem_if in the controller and controlling the scan chain and the boundary scan circuit according to the power on / off of the ASIC Based on the knowledge that the power supply can be closed without adding a new memory or control circuit, the present invention has been completed.

The present invention relates to a power saving method for an ASIC having a scan chain circuit and a boundary scan circuit, the original scan control signal for controlling the scan chain circuit, the original boundary scan control signal for controlling the boundary scan circuit, and power-off. A scan for controlling the scan circuit from the input of the scan control signal, the boundary scan control signal, the power-off control signal, the clock, and the reset signal. A control signal, a boundary scan control signal for controlling the boundary scan circuit, a power switch control signal for controlling the power supply of the ASIC, a scan clock which is a clock of the scan circuit, and a clock of the boundary circuit. A power saving controller for newly generating a boundary scan clock, a reset signal for resetting the ASIC, and a memory interface control signal for controlling an interface with an external memory, and the power saving controller includes the newly generated scan control signal, the boundary scan control signal, and a power switch control signal, scan clock, boundary scan clock, a reset signal, the memory interface control signals, the block to be closed power of the ASIC when the power-off, the said ASIC a first step of closing the clock signal of the block, the primary output of the block of the ASIC, and stored in the memory device of the boundary scan circuit, then, an input end of an external circuit, from said principal output, said bow A second step of switching to the memory element of the Dali scan circuit, a third step of transferring the contents of the internal memory element of the ASIC to the external memory via the scan chain circuit, and turning off the power of the ASIC A first step of turning on the power of the block of the ASIC and resetting an internal block when the power of the block of the ASIC is turned on by performing a power off operation comprising the fourth step, and the external memory A second step of returning the numerical value stored in the internal memory element by the scan chain circuit, and a third step of switching the input terminal of the external circuit from the memory element of the boundary scan circuit to the main output; And a fourth step of turning on the clock signal of the block , and a power-on operation is performed. is there.

  The present invention is characterized in that the power supply of unused circuits can be closed using an existing circuit, power saving can be achieved by reducing leakage, and the number of additional circuits can be minimized.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings. However, the present invention is not limited to the following examples or drawings.

  FIG. 1 shows a scan chain representative circuit of a production test. In the synchronous logic ASIC, the scan chain circuit is arranged along the main circuit. The main circuit is composed of a combination of the logic circuit 1 and the memory type element 2. The type of the memory-type element 2 is not particularly limited, but is typically a flip-flop or a shift register.

  The scan chain circuit includes multiplexers 3 and 4. The multiplexer 3 has two inputs “test 31” and “operation 32”, and the multiplexer 4 has two inputs “scan clock 41” and “main clock 42”. When the control signals s_enable 33 and s_mode 43 of the multiplexers 3 and 4 are at a low potential, “work 32” and “main clock 42” are input to the synchronous logic ASIC to perform normal work. When the control signals s_enable 33 and s_mode 43 of the multiplexers 3 and 4 are at a high potential, the circuit enters a scan mode and performs a production test. The “scan clock 41” is replaced with the “main clock 42”, and the synchronous logic ASIC The data of “test 31” is input to the memory type element 2 and passes through the logic circuit 1 of the combination, then passes through each memory type element 2 and is output from the output port 20 to synchronize logic. Conduct ASIC production test.

  FIG. 2 is a circuit diagram of a boundary scan (IEEE 1149.1). In the design test, the test standby unit 5 for storing / observing the main output signal 52 is surrounded by the boundary scan mechanism 10 (the shaded area in the figure). Specifically, the test material 58 is input to the main input terminal 51 through the multiplexer 55 using the bs_clock 59 and the bs_enable 54 signals. The main output signal 52 of the test standby unit 5 is stored by the memory element 57 and then exported by the boundary scan mechanism 10. The boundary scan mechanism 10 tests the design of the test standby unit 5.

  In order to shut down the power of the unused circuit, the following two must be executed. First, the contents of all the memory elements in the block 8 whose power is to be closed are copied to the external memory 6 so that the working state can be recovered during the process of turning on the power later. Here, the external memory 6 is not particularly limited, but for example, a set of flip-flops, a RAM, or other memory elements are preferably used. Next, while holding the original signal, the main output 52 of the block 8 whose power is to be closed is floated.

  First, as a device for copying the contents of all memory elements in the block 8 to the external memory 6, FIG. 3 shows a state in which the block 8 whose power supply is to be closed is surrounded by combining the above-described scan chain and boundary scan. . Since the scan chain circuit and the boundary scan circuit are circuits generally used in integrated circuits such as portable applications, the present invention uses the scan chain and boundary scan circuit for power saving. .

  The present invention uses a scan chain circuit to store the contents of the memory element in the block 8 whose power supply is to be closed in the external memory 6, and raises the s_enable 33 and s_mode 43 of the multiplexers 3 and 4 to a high potential to close the power supply. The block 8 to be entered enters the scan mode. At the same time, in the present invention, the boundary scan circuit can be saved in the external circuit 7 by using the boundary scan circuit.

FIG. 4A is a flowchart showing the power-off process of the present invention.
First, the clock of the block 8 whose power is to be closed is closed (step 91). Next, the main output 52 is stored in the flop 57 of the boundary scan mechanism 10. Thereafter, the input end of the external circuit 7 is switched from the main output 52 of the block 8 whose power supply is to be closed to the boundary scan flop 57 (step 92). Further, the current state of the internal flip-flop 2 is transferred to the external memory 6 by the scan chain circuit (step 93). Finally, the block 8 is turned off (step 94).

In order to restore the circuit of the power-off circuit to the normal operation mode, the power-on process shown in FIG. 4B is performed.
First, the power is turned on and the block 8 is reset (step 95). Next, the stored flop value is shifted by the scan chain (step 96). Then, the signal switched to the external circuit 7 is returned from the boundary scan flop 57 to the main output 52 (step 97). Finally, the block 8 is opened to return to normal operation (step 98).

  Next, FIG. 5 shows a block diagram of the power-saving controller 9 for accomplishing two kinds of tasks of opening and closing the power supply for a device that floats the main output 52 of the block 8 that wants to close the power supply while holding the original signal. . The controller 9 collects original signals of the scan chain and boundary scan, generates a set of new control signals, and saves power.

  However, the power saving controller 9 can be replaced by a CPU included in the synchronous logic ASIC and does not have to be dedicated hardware. With such an alternative, it is possible to obtain a power saving effect based on power on / off provided by the present invention without adding hardware.

  The scan chain and boundary scan original signals are used for circuit production test and design test, respectively. After the product passes the test, the scan chain and boundary scan original signals are both high potential. Or it is fixed at a low potential and cannot be used again during the life cycle of the product. Therefore, it is possible to save power by generating a set of new control signals based on the scan chain and the original signal of the boundary scan. The original signals of the scan chain and the boundary scan include org_s_mode, org_s_enable, org_bs_mode, and org_bs_enable, which are shown on the left side of the power saving controller 9 in FIG. The power_off, clock and reset signals are also shown on the left side of the power saving controller in FIG.

  The output pin s_mode 43 on the right side of the power saving controller 9 switches the memory element in the block 8 whose power is to be shut down between three kinds of working modes, a normal working mode, a low power clock closing mode, and a shift (in / out) mode. Signal. The s_mode 43 is a bus type, and if the number of flops in the scan chain changes, the controller must be adjusted and the output signal must meet the time requirement.

  The s_enable 33 is a signal for switching the internal data path, and the memory element 2 obtains a different input from the “test 31” or “operation 32”.

  The bs_mode 53 is a signal that determines the switching time of the boundary scan latch clock signal or the main power saving mode. Besides maintaining bs_enable 54 to be homologous to org_bs_enable, this signal needs to switch the output of the block 8 to the memory unit 57 during power saving, so that the external circuit 7 can obtain the output value permanently.

  pw_switch 61 is a signal for controlling the power switch.

  The scan_clock 41 is a signal that provides a scan in / out clock to the internal scan chain.

  bs_clock 59 is a signal that is controlled by bs_mode 53 and provides a clock signal of the boundary scan flop 57.

  mem_if 60 is a memory control interface. Such signals need to be changed according to different memory configurations.

  The present invention can achieve power saving by using existing circuits, and it is not necessary to add many circuits. Therefore, typically, it is possible to obtain a power saving effect that enables long-time driving for all ASICs mounted on portable electronic devices, and in addition to this, application to various devices is possible.

It is the figure which showed the scan chain circuit. It is the figure which showed the boundary scan (IEEE1149.1) circuit. It is the figure which merged the scan chain circuit and the boundary scan (IEEE1149.1) circuit in synchronous logic ASIC. 3 is a flowchart of a power on / off process according to the present invention. It is a block diagram of a control circuit of the present invention.

Explanation of symbols

1 Logic circuit 2 Memory element
3, 4 Multiplexer 5 Test standby unit 6 External memory 7 External circuit 8 Block to shut off power supply 9 Power saving controller
10 Boundary scan mechanism 20 Output port 31 “Test 31”
32 “Work 32”
33 Control signal s_enable
41 “Scan Clock 41”
42 “Main clock 42”
43 s_mode
51 Main input terminal 52 Main output signal 54 bs_enable
55 Multiplexer 57 Memory element 58 Test data 59 bs_clock

Claims (1)

An ASIC power saving method having a scan chain circuit and a boundary scan circuit,
An original scan control signal for controlling the scan chain circuit, an original boundary scan control signal for controlling the boundary scan circuit, a power-off control signal, a clock, and a reset signal are input, and the input scan control signal and the boundary are input. A scan control signal for controlling the scan circuit, a boundary scan control signal for controlling the boundary scan circuit, and the ASIC from a scan control signal, the power-off control signal, the clock, and the reset signal A power switch control signal for controlling the power of the scan circuit, a scan clock that is a clock of the scan circuit, a boundary scan clock that is a clock of the boundary circuit, a reset signal for resetting the ASIC, and an external memory Has a power saving controller for generating a new memory interface control signals for controlling the interface,
The power saving controller includes the newly generated scan control signal, boundary scan control signal, power switch control signal, scan clock, boundary scan clock, reset signal, and memory interface control signal.
When turning off the block that wants to close the power supply of the ASIC,
A first step of closing a clock signal of the block of the ASIC;
A second step of storing a main output of the block of the ASIC in a memory element of the boundary scan circuit, and then switching an input end of an external circuit from the main output to the memory element of the boundary scan circuit;
A third step of exporting the contents of the internal memory element of the ASIC to the external memory via the scan chain circuit;
A fourth step of turning off the power of the ASIC;
The power off operation consisting of
When turning on the block of the ASIC,
A first step of turning on the power of the block of the ASIC and resetting the internal block;
A second step of returning the numerical value stored in the external memory to the internal memory element by the scan chain circuit;
A third step of switching the input end of the external circuit from the memory element of the boundary scan circuit to the main output;
A fourth step of turning on the clock signal of the block ;
A power-saving method for an ASIC characterized by performing a power-on operation comprising: