CN100479327C - Clock generating circuit - Google Patents
Clock generating circuit Download PDFInfo
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- CN100479327C CN100479327C CNB2005100937405A CN200510093740A CN100479327C CN 100479327 C CN100479327 C CN 100479327C CN B2005100937405 A CNB2005100937405 A CN B2005100937405A CN 200510093740 A CN200510093740 A CN 200510093740A CN 100479327 C CN100479327 C CN 100479327C
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Abstract
This invention discloses one clock generation circuit, which comprises the following parts: one first ring oscillation circuit, one second oscillation circuit, one time control circuit and one clock output circuit, wherein, the first and second oscillation circuit to receive order signals and to generate one frequency clock; the control circuit is used to control signal outside chip and to send order signal and to control first and second ring oscillation circuits to control clock output circuit; the said output circuit is used to select and amplify output clock signals.
Description
Technical field
The present invention relates to a kind of integrated circuit (IC) chip clock internal and produce circuit arrangement, in particular a kind of low-power consumption clock generation circuit technology of communication field.
Background technology
Clock has two kinds of producing methods in integrated circuit (IC) chip: a kind of is to be provided by chip exterior; Another kind of for the consideration of factors such as complete machine demand and chip power-consumption, clock is produced by the chip internal circuit.
On chip application, a lot of situations need be carried out work by the clock lower than normal clock frequency.Under test case, need low-frequency clock to carry out chip testing as chip, to reach the purpose of easy test and development; During at holding state, need low-frequency clock work at the chip functions circuit, so that reduce power consumption; In being arranged, the circuit of battery saving mode also needs low-frequency clock work, the chip used of portable equipment particularly, as comprise mobile phone internal logic and drive circuit etc.
It is very important in actual applications the chip low-power consumption being required, and especially the chip low-power consumption index at portable equipment is its topmost index; From the development trend of portable equipment is that power consumption is more and more littler, obvious especially on the development trend of mobile phone and digital camera, so it is extremely important in the chip that has low-power consumption to require to design the clock generation circuit of a low-power consumption.
For the situation that clock is produced by chip internal, the chip internal clock switches to the low-frequency clock circuit from normal clock and mainly contains two kinds: digital divider circuit and simulation Voltage-Controlled oscillation circuit.
Be a kind of chip internal digital divider circuit block diagram as shown in Figure 1, this circuit produces an operate as normal clock CLK by the time speciogenesis device of chip internal, CLK exports to the trigger frequency dividing circuit, produces required clock signal clk 1, CLK2...CLKX through the trigger frequency dividing circuit.The characteristics of digital divider circuit are that operate as normal clock and a plurality of frequency-dividing clock can export simultaneously, and chip is easy to carry out clock selecting according to demand.But chip needs the situation of low-frequency clock, three kinds of situations as above act: in test pattern, standby mode and the battery saving mode, the chip major part does not need a plurality of clocks to work simultaneously, only need a kind of clock work to get final product, the result that provides simultaneously of clock makes chip make useless power consumption so for a long time.And wherein clock generator and the trigger frequency dividing circuit in the digital divider circuit is in running order always, and when especially the trigger frequency dividing circuit carried out frequency division, the power consumption of trigger was relatively large, and the useless power consumption of chip is just very big like this.
Be a kind of chip internal simulation Voltage-Controlled oscillation circuit block diagram as shown in Figure 2.This circuit is made up of numerical control voltage generation circuit and voltage controlled oscillator (VCO), the digital signal VIN that has the required clock frequency information of system is input to the numerical control voltage generation circuit, the numerical control voltage generation circuit produces a voltage VCTL, VCTL and clock frequency have corresponding relation, this voltage outputs to voltage controlled oscillator, and described voltage controlled oscillator produces the clock CLK3 and the output of respective frequencies under voltage VCTL effect.The simulation Voltage-Controlled oscillation circuit is directly exported single clock, thereby avoids situations such as the jagged phenomenon of digital divider circuit output low frequency clock, duty ratio index be bad.But because the numerical control voltage generation circuit generally produces different voltage by resistor voltage divider circuit or charge pump circuit, thereby power consumption is bigger; The power consumption of voltage-controlled oscillator circuit own is also bigger in addition, so simulation Voltage-Controlled oscillation circuit power consumption integral body is all bigger.
From top analysis as can be seen, all there is the big defective of power consumption in this employing simulation of this employing digital divider circuit of Fig. 1 and Fig. 2 Voltage-Controlled oscillation circuit.Not only power consumption is big for chip internal digital divider circuit shown in Figure 1, and the output clock is undesirable.Not only power consumption is big for chip internal simulation Voltage-Controlled oscillation circuit shown in Figure 2, and chip area is big.
Therefore, there is defective in prior art, and awaits improving and development.
Summary of the invention
The object of the present invention is to provide a kind of clock generation circuit, technical problem to be solved is the power problems of clock generation circuit, to reduce the useless power consumption of clock generation circuit.
Technical scheme of the present invention comprises:
A kind of clock generation circuit wherein, comprising: one first loop oscillation circuit, one second loop oscillation circuit, a clock control circuit and a clock output circuit; Described clock control circuit comprises a state assignment logic module, system command detection module, two clock detection modules and two command generation module;
Described first and second loop oscillation circuit is respectively applied for and receives the clock that command signal produces certain frequency;
Described clock control circuit is used for the chip exterior control signal, sends command signal and controls the described first loop oscillation circuit and the second loop oscillation circuit, and control described clock output circuit;
Described clock output circuit is used for selecting and buffering is amplified clock signal;
Described chip exterior control signal is input to described system command detection module, and described system command detection module detects output state of a control signal to described state assignment logic module;
Described state assignment logic module is according to the signal instruction of state of a control signal, export different control signals respectively to two command generation module, described command generation module produces corresponding command signal under the triggering of different control signals, described command signal is input to corresponding loop oscillation circuit;
Described loop oscillation circuit also is input to the clock signal that is produced corresponding clock detection module, and corresponding clock detection module detects whether the clock signal that receives is normal clock, and output status signal is to described state assignment logic module;
Described state assignment logic module is also according to described status signal, and output clock switching signal is controlled described clock output circuit and selected clock signal to described clock output circuit.
Described circuit, wherein, described clock control circuit also comprises internal clocking selection module;
Described state assignment logic module is according to status signal, through judging the state value of status signal, output selects signal to select module to internal clocking, internal clocking selects module to select signal value to go to select clock to output to system clock (SYCK) according to judging, as the clock control circuit internal clocking, internal clocking selects module to export corresponding clock by system clock (SYCK).
Described circuit, wherein, described loop oscillation circuit comprises: inverse delayed unit strings and numerical control MUX are formed in M inverse delayed unit, wherein:
M inverse delayed units in series formed, and wherein M is an odd number and more than or equal to 3;
Described inverse delayed unit strings output has X interface to go out to be connected to the input of numerical control MUX, and wherein X is an odd number and less than M.
A kind of clock generation circuit provided by the present invention owing to adopted the output of loop oscillation circuit control clock, has realized reducing preferably chip power-consumption.
Description of drawings
Fig. 1 is a kind of chip internal digital divider circuit block diagram of prior art;
Fig. 2 is a kind of chip internal simulation Voltage-Controlled oscillation circuit block diagram of prior art;
Fig. 3 is a described clock generation circuit block diagram of the present invention;
Fig. 4 is the internal module block diagram of clock control circuit of the present invention;
Fig. 5 is the schematic diagram of a loop oscillation circuit exemplary of circuit of the present invention;
Fig. 6 is the operating circuit reduced graph of clock generation circuit of the present invention.
Embodiment
To be described in further detail concrete enforcement of the present invention below in conjunction with accompanying drawing.
Clock generation circuit of the present invention as shown in Figure 3, comprises one first loop oscillation circuit A, the second loop oscillation circuit B, clock control circuit and clock output circuit; The described first loop oscillation circuit A is used to receive the clock that command signal produces certain frequency; The described second loop oscillation circuit B is used to receive the clock that command signal produces certain frequency; Described clock control circuit is used for the chip exterior control signal, and send command signal and control the first loop oscillation circuit A and the second loop oscillation circuit B, and the output of control clock; Described clock output circuit is used for selecting and buffering is amplified clock signal.
Be the theory diagram of clock generation circuit of the present invention as shown in Figure 3, in clock generation circuit of the present invention, comprise the first loop oscillation circuit A, the second loop oscillation circuit B, clock control circuit 11 and clock output circuit 12.
Control signal IN is input to clock control circuit 11, and described clock control circuit 11 output instruction signal SC are to the loop oscillation circuit, and wherein SC1 outputs to the second loop oscillation circuit B, and SC0 outputs to the first loop oscillation circuit A.The clock signal C P1 that the clock signal C P0 of the described first loop oscillation circuit A outputs to clock control circuit 11 and clock output circuit 12, the second loop oscillation circuit B also outputs to clock control circuit 11 and clock output circuit 12.Described clock control circuit 11 output clock switching signal BF are to clock output circuit 12, and under BF control, clock output circuit 12 is selected the clock signal C P0 of two inputs, clock signal C P1, and buffering is amplified clock signal CPY.
The course of work of circuit of the present invention is specially:
Suppose that present operating state is that the first loop oscillation circuit A is in running order, clock signal C P0 is output as the clock signal of frequency f 1, this moment, the second loop oscillation circuit B was in holding state, and clock signal C P1 is output as a fixed level signal, rather than the certain frequency clock is arranged.Clock control circuit 11 also is in holding state, and the clock of clock control circuit 11 internal logic work adopts CP0.Clock output circuit 12 is selected CPO to amplify through buffering and is outputed to CPY.
Control signal IN (at this moment IN contains output frequency f2 information) is input to clock control circuit 11, and described clock control circuit 11 enters into operating state from holding state under the IN signal enabling.The command signal SC1 that clock control circuit 11 sends is to the second loop oscillation circuit B, and the instruction of SC1 is command code (command code comprises f2 clock frequency control information).
The described second loop oscillation circuit B receives that SC1 instruction back starts, and enters into operating state from holding state, and it is the clock signal C P1 of f2 that the second loop oscillation circuit B produces frequency, and outputs to clock control circuit 11.
Described clock control circuit 11 receives the clock signal C P1 that the second loop oscillation circuit B produces, and judges that clock signal C P1 is a continuous clock signal, just can think that the second loop oscillation circuit B has been in normal operating conditions.Then the output clock switching signal BF of clock control circuit 11 is to clock output circuit 12, and wherein BF is comprising the control information of change over clock.Simultaneously, the clock of clock control circuit 11 internal logic work switches to CP1 by CP0.After the clock of logic working successfully changes into to CP1, clock control circuit 11 output instruction signal SC0 (the SC0 instruction is standby command) are to the first loop oscillation circuit A, the first loop oscillation circuit A enters holding state, and clock control circuit 11 also enters holding state simultaneously.
After receiving clock switching signal BF, described clock output circuit 12 cushions the clock signal C P1 of input to amplify immediately and outputs to CPY, and stops CP0 simultaneously and cushion and amplify output.Clock output circuit 12 output frequencies are the clock signal C PY of f2.Because clock output circuit 12 directly amplifies output to the buffer clock signal of loop oscillation circuit, so output clock CPY performance is more satisfactory.
More than be that the first loop oscillation circuit A is in working order under (produce f1 clock) situation, the second loop oscillation circuit B enters operating state (producing the f2 clock) under control signal IN effect, and switching clock output, change f2 from clock signal CPY frequency into by f1, and make the first loop oscillation circuit A change holding state over to.
As a same reason, under control signal IN effect, can switch the first loop oscillation circuit A and loop oscillation circuit.
As shown in Figure 4, clock control circuit internal module block diagram of the present invention, clock control circuit is a Digital Logical Circuits.In clock control circuit of the present invention, comprise A clock detection module, B clock detection module, internal clocking selection module, A command generation module, B command generation module, state assignment logic module and system command detection module.
In clock control circuit, control signal IN is input to the system command detection module, and when the system command detection module detects the command information of IN, output state of a control signal XIN is to the state assignment logic module.The state assignment logic module is according to the signal instruction of XIN, and SCA is to the A command generation module for the output control signal, and SCB is to the B command generation module for the output control signal.The A command generation module produces command signal SC0 under SCA triggers; The B command generation module produces command signal SC1 under SCB triggers.CP0 is input to A clock detection module, and A clock detection module detects whether CP0 is normal clock, and output status signal CPA is to the state assignment logic module; CP1 is input to B clock detection module, and whether B clock detection module detects CP1 is normal clock, and output status signal CPA is to the state assignment logic module.
Described state assignment logic module is according to the signal instruction of XIN, through judging the state value of CPA, CPB, output XCP selects signal to select module to internal clocking, CP0 and CP1 are input to internal clocking and select module, and internal clocking selects module to go to select CP0 or CP1 to output to system clock SYCK according to judgement XCP value.SYCK is as the clock control circuit internal clocking, and internal clocking selects module output SYCK to A clock detection module, B clock detection module, A command generation module, B command generation module, state assignment logic module and system command detection module.
As shown in Figure 5, be the schematic diagram of a loop oscillation circuit exemplary, the loop oscillation circuit forms inverse delayed unit strings 21 by M inverse delayed unit and numerical control MUX 22 is formed.Wherein:
Described inverse delayed unit strings 21 is made up of M inverse delayed units in series, and wherein M is an odd number and more than or equal to 3.The input termination clock signal C P of described inverse delayed unit strings 21 first inverse delayed unit, inverse delayed unit strings output has X interface to go out to be connected to the input of numerical control MUX 22.Wherein X is an odd number and less than M.
Described loop oscillation circuit has two kinds of mode of operations: normal mode of operation and standby mode.Below explanation respectively:
One, normal mode of operation
The output of described numerical control MUX 22 connects clock signal C P, and the control signal of input is command signal SC, and SC is the command signal that described clock control circuit 11 sends.SC has different command codes, and the respective input that each command code can be controlled numerical control MUX 22 links to each other with output in circuit inside.For example, when SC was 010 yard, S3 linked to each other with CP.
So, send different SC instructions from described clock control circuit 11, can allow inverse delayed unit strings 21 be connected to form inverse delayed unit loop by the input and output side of numerical control MUX 22.And inverse delayed unit loop forms loop oscillation under the startup situation, just can export the clock signal of concrete certain frequency, by the CP clock signal.
And be td in two adjacent inverse delayed cell delay times of inverse delayed unit strings 21, the clock cycle T=2ntd of loop oscillation, then clock frequency is f=1/T=1/ (2ntd), n is the inverse delayed unit number in the inverse delayed unit loop.
Described clock control circuit 11 sends different SC instructions, and X interface of control inverse delayed unit strings links to each other with CP, has directly controlled the inverse delayed unit number n in the inverse delayed unit loop, thus control output CP clock frequency.For example, when SC was 001 yard, S1 linked to each other with CP, and at this moment n is 3, and the clock frequency of output CP is f=1/ (6td).
Two, standby mode
When the SC instruction that described clock control circuit 11 sends was standby command, the input and output of described numerical control MUX 22 disconnected.CP is output as a fixed level signal, but not the clock of certain frequency is arranged, and described inverse delayed unit loop was disconnected and can't forms loop oscillation this moment.
Be clock generation circuit operating circuit reduced graph of the present invention as shown in Figure 6, comprise loop oscillator 31 and buffer 32, finishing clock when clock generation circuit of the present invention switches, when entering normal operating conditions, one of them loop oscillation circuit is in holding state, substantially do not produce power consumption, the inner numerical control MUX 22 of another loop oscillation circuit does not substantially produce power consumption yet, so the loop oscillation circuit can be reduced to the loop oscillator 31 that the inverse delayed unit strings is formed.In addition, clock output circuit 12 is finished after two clock signals selections, and internal circuit produces power consumption substantially from the buffer 32 with buffering amplification.And clock control circuit 11 is not having external control signal IN to come in to be in holding state under the situation, and the consumption power consumption is very little.Comprehensively above-mentioned, the power consumption of circuit of the present invention is less relatively.
Detailed introduction by above can be clear that, clock generation circuit of the present invention has solved the low-power consumption problem of clock generation circuit effectively.
Should be understood that above-mentioned description at specific embodiment is comparatively detailed, but can not therefore be interpreted as the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.
Claims (3)
1, a kind of clock generation circuit is characterized in that, comprising: one first loop oscillation circuit, one second loop oscillation circuit, a clock control circuit and a clock output circuit; Described clock control circuit comprises a state assignment logic module, system command detection module, two clock detection modules and two command generation module;
Described first and second loop oscillation circuit is respectively applied for and receives the clock that command signal produces certain frequency;
Described clock control circuit is used for the chip exterior control signal, sends command signal and controls the described first loop oscillation circuit and the second loop oscillation circuit, and control described clock output circuit;
Described clock output circuit is used for selecting and buffering is amplified clock signal;
Described chip exterior control signal is input to described system command detection module, and described system command detection module detects output state of a control signal to described state assignment logic module;
Described state assignment logic module is according to the signal instruction of state of a control signal, export different control signals respectively to two command generation module, described command generation module produces corresponding command signal under the triggering of different control signals, described command signal is input to corresponding loop oscillation circuit;
Described loop oscillation circuit also is input to the clock signal that is produced corresponding clock detection module, and corresponding clock detection module detects whether the clock signal that receives is normal clock, and output status signal is to described state assignment logic module;
Described state assignment logic module is also according to described status signal, and output clock switching signal is controlled described clock output circuit and selected clock signal to described clock output circuit.
2, circuit according to claim 1 is characterized in that, described clock control circuit also comprises internal clocking selection module;
Described state assignment logic module is also according to described status signal, through judging the state value of described status signal, output selects signal to select module to described internal clocking, described internal clocking selects module to select signal value to go to select clock signal to output to system clock (SYCK) according to judging, as the clock control circuit internal clocking, internal clocking selects module to export corresponding clock by system clock (SYCK).
3, circuit according to claim 1, it is characterized in that, described loop oscillation circuit comprises: inverse delayed unit strings and numerical control MUX are formed in M inverse delayed unit, wherein: M inverse delayed units in series composition, wherein M is an odd number and more than or equal to 3;
Described inverse delayed unit strings output has X interface to go out to be connected to the input of numerical control MUX, and wherein X is an odd number and less than M.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100937405A CN100479327C (en) | 2005-08-29 | 2005-08-29 | Clock generating circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100937405A CN100479327C (en) | 2005-08-29 | 2005-08-29 | Clock generating circuit |
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| CN1925324A CN1925324A (en) | 2007-03-07 |
| CN100479327C true CN100479327C (en) | 2009-04-15 |
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| CNB2005100937405A Active CN100479327C (en) | 2005-08-29 | 2005-08-29 | Clock generating circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108092648A (en) * | 2017-12-12 | 2018-05-29 | 天津瑞发科半导体技术有限公司 | Reference clock automatic selection circuit in piece |
| CN115269491B (en) * | 2022-07-18 | 2024-03-22 | 北京中科银河芯科技有限公司 | Single-wire communication device and single-wire communication method |
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Application publication date: 20070307 Assignee: SANECHIPS TECHNOLOGY Co.,Ltd. Assignor: ZTE Corp. Contract record no.: 2015440020319 Denomination of invention: Clock generating circuit Granted publication date: 20090415 License type: Common License Record date: 20151123 |
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Effective date of registration: 20221114 Address after: 518055 Zhongxing Industrial Park, Liuxian Avenue, Xili street, Nanshan District, Shenzhen City, Guangdong Province Patentee after: SANECHIPS TECHNOLOGY Co.,Ltd. Address before: 518057 Department of law, Zhongxing building, South hi tech Industrial Park, Nanshan District hi tech Industrial Park, Guangdong, Shenzhen Patentee before: ZTE Corp. |