CN100345126C - Universal serial bus interface quick flash storage integrated circuit - Google Patents
Universal serial bus interface quick flash storage integrated circuit Download PDFInfo
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- CN100345126C CN100345126C CNB011403772A CN01140377A CN100345126C CN 100345126 C CN100345126 C CN 100345126C CN B011403772 A CNB011403772 A CN B011403772A CN 01140377 A CN01140377 A CN 01140377A CN 100345126 C CN100345126 C CN 100345126C
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Abstract
The present invention relates to a universal serial bus interface quick flashing memory integrated circuit and provides a quick flashing memory storing integrated circuit which can be provided with a universal serial bus interface and is connected with a main machine. The universal serial bus interface (USB) becomes an interface with a standard interface, data is quickly stored to an outer memory device, and the data of the outer memory device is quickly read. Consequently, the combination of speeds of a quick flashing memory device and the universal serial bus interface is very important, and besides, when the quick flashing memory device designed through an interface with the universal serial bus interface is used, the quick flashing memory device becomes a storing device with the standard universal serial bus interface. Connection and interaction can be easily established between the main machine and the quick flashing memory storing device. If the present invention is denoted with the pattern of the integrated circuit, the present invention becomes a built-in quick flashing memory integrated circuit with the interface with the universal serial bus interface.
Description
Technical field
The present invention system is relevant for flash memory device, and finger can have the flash memory device that USB (universal serial bus) connects especially, represents with the kenel of integrated circuit, is USB (universal serial bus) interface quick flash storage integrated circuit.
Background technology
The portability of flash memory and the characteristic that can not erase make it become the important media of storage data, for for portable apparatus such as hand-held electronic device, this is a kind of very useful data storing mode, and the convenience that flash memory brought makes its storage device more traditional than major part (as rigid magnetic disc etc.) have bigger advantage, except portability, the advantage of flash memory also has advantages such as low power consumption rate, reliability, light and handy and high speed.
Flash memory is nonvolatile, still possess the data that stored even this expression power supply has been closed it, this random-access memory (ram) than standard is more progressive, and random access memory is volatile, therefore when power supply is closed, will lose the data that stored.
The general bus transfer interface of getting lines crossed is being the standard of PC/NB/IA product, but and above product nationality start (bootable) by general Storage Media of getting lines crossed the bus transfer interface, make rigid magnetic disc be strengthened, also can produce many inconvenience but present general Storage Media of getting lines crossed the bus transfer interface mostly is being plug-in mode by the space that the Storage Media of the general bus transfer interface of getting lines crossed is replacing.
Present miniaturization IA product such as PDA, industrial computer, digital cameras etc. are in response to multi-functional demand, therefore all enclose operating system (Operation System) as Win CE/Linux etc., the Flash Memory that needs a CPU to add a NOR Type on its hardware design framework comes the stored routine sign indicating number, the storage area that data is arranged if desired, then need to add other SRAM or more built-in NANDFlash Memory or external memory card, three kinds of above solutions all not too are the standard interface of Win CE/Linux, the deviser needs to revise voluntarily the driver or the application program of these operating systems usually again, therefore often is many mental and physical efforts and the money of these interface costs in the exploitation of new product.
Therefore, need at present a Storage Media can in be built among the system, have a standard interface and can be common to various operating systems, do not need to revise again the driver or the application program of these operating systems, and have advantages such as low power consumption rate, reliability, light and handy and high speed, to reach the demand of portability.
Summary of the invention
In order to reach these and other advantage, also have for shortcoming that overcomes the traditional flash memory card and the goal of the invention that meets place like this summary narration, so the present invention promptly provides one can store integrated circuit by the flash memory that USB (universal serial bus) is connected with main frame.
USB (universal serial bus) (USB) has become the sequence interface of standard, it allows data be stored in universal serial bus interface quick flash storage integrated circuit and reading of data from universal serial bus interface quick flash storage integrated circuit apace apace, therefore, in conjunction with the speed of the advantage of flash memory and USB (universal serial bus) with highly beneficial, in addition, universal serial bus interface quick flash storage integrated circuit by design collocation USB (universal serial bus) interface, can make flash memory become the USB (universal serial bus) storage device of standard, main frame can be linked to each other easily with flash memory and interactive.
A controller wafer and at least one flash memory die have been comprised in the encapsulation of universal serial bus interface quick flash storage integrated circuit, described controller comprises system buffer, microprocessor and hardware state machine, described microprocessor is connected with system buffer, USB (universal serial bus) interface, I/O control interface and flash memory interface, described flash memory interface connects flash memory, and the pin position of described integrated circuit encapsulation has kept:
USB (universal serial bus) interface pin position (sequence transmission interface);
Storage type flash memory extending interface pin position, make universal serial bus interface quick flash storage integrated circuit can external again storage type flash memory with the increase capacity; And
The I/O interface pin position of controller makes universal serial bus interface quick flash storage integrated circuit can do other application.
Controller is a primary clustering in the device, this controller has been controlled order and the data between universal serial bus interface quick flash storage integrated circuit and the main frame, and the data in the management flash memory array, controller is a single-chip design that does not need external ROM or RAM preferably.
The storage type flash memory extending interface pin position of universal serial bus interface quick flash storage integrated circuit is in order to expand the flash memory capacity, so that utilize flash memory array to extend memory size.
The controling appliance of the universal serial bus interface quick flash storage integrated circuit of the present invention has myriad of functions, there is one to be control USB (universal serial bus) interface in these functions, controller is to abide by the USB (universal serial bus) standard aspect entity and logic agreement, and controller has further comprised a fifo controller buffer zone, make the controller reception carry out package from the order and the parameter of the main frame of tool USB (universal serial bus), this package is with in being stored in a special working storage by the controller definition, and controller also is responsible for the data transmission between control and the main frame simultaneously, in addition, controller also provides status data to main frame.
When main frame sends a write command, will produce and interrupt and send to controller and microprocessor, so that the position of this order of notice microprocessor and order, this microprocessor (for example microprocessor of one 8 or 16-bit) is a primary clustering of controller, and microprocessor reads the order and the parameter of USB (universal serial bus) from working storage, in addition, and microprocessor is also carried out the order of tool parameter, microprocessor is managed on the one hand and is shone upon the USB (universal serial bus) fifo address to the controller buffer zone, receive on the one hand from the data of the main frame of tool USB (universal serial bus) and with data transmission to main frame, in addition, microprocessor also is the flash memory array management, for example wipe off, program or order such as read, in addition, microprocessor is also according to the algorithm executive address method (address arithmetic) of controller.
The director demon code that microprocessor ROM build in the controller in inciting somebody to action is stored, and microprocessor is controller employed RAM of system when carrying out USB (universal serial bus) order or quickflashing algorithm, because it does not need to leave the wafer storer, therefore reduced the cost of system.
In order to the system buffer of buffering USB (universal serial bus) interface and flash memory array interface by as getting use soon, the address of this buffer zone of microprocessor management, if necessary, buffer zone can carry out access by bit group or literal.
Described hardware state machine, read and write sequential in order to what set up system buffer between main frame and the flash memory, quickflashing interface and circuit have been controlled reading of flash memory array and write command, and in the concrete manifestation of the present invention, this is a pure hardware circuit.
In addition, when the data of getting soon when buffer zone write to flash memory array, the ECC circuit ECC code of will encoding, and when the data that read flash memory array when buffer zone is got soon, the ECC circuit is then with the ECC code decoding.If the ECC mistake takes place, literal or the bit group during ECC circuit meeting interpretation buffer zone is got soon also corrected mistake.
The USB (universal serial bus) order is actual have been comprised and has received the order and the parameter control device of main frame, and will order and parameter is stored in the defined working storage of controller, and can produce and send and interrupt to notify microprocessor to receive order.
Controller receives the data of main frame and sends the data to main frame according to USB (universal serial bus) logic and entity standard, and address approach comprised the wiping off of management flash memory, read and the mapping to logic of write command and management entity.
When main frame will be ordered and parameter when writing in the universal serial bus interface quick flash storage integrated circuit, it can be stored in controller in the specific working storage, data can be read as information from main frame by microprocessor subsequently, USB (universal serial bus) standard according to standard, require parameter for having comprised 7 bits, the D6-D5 bit of BmRequest Type has been specified the type of order agreement, kind comprises standard, grade and manufacturer, this three types the agreement of the flash memory device of the present invention is all supported, standard form is the matching requirements of standard, this is common order, as USB (universal serial bus) USB_Get_status or USB_set_Feature etc.
The flash memory device of the present invention has utilized collocation bulk/ to control/interrupt the USB (universal serial bus) mass storage class of transmission on concrete form.
Because the restriction on the flash memory entity, before carrying out write command, must carry out earlier and wipe order off, general flash memory need be through just can normal operation after about 1,000,000 times the wiping off, so, reducing the step of wiping off is very important with the serviceable life that prolongs flash memory, therefore, the present invention provides a logical and physical address mapping table and a mother/sub-framework to reach this target.
It below is the operation instruction of logical and physical address mapping table, when starting flash memory, all blocks all can be searched, and entity that searches and the relation record between the logical blocks will become logical and physical address mapping table, meanwhile, untapped physical blocks is then put into spare blocks allows the FIFO queue use, then, logical blocks in the logical and physical address mapping table can be used to seek corresponding physical blocks address, thus, just can accurately write or the data of acquisition and special entity block associated.
When data are write flash memory, the block (new block) that may need a process to wipe off replaces old block, then data are write in the new block, the data that will more not correct one's mistakes move to new block from old block at last, and this step has been finished the action that writes a page data.
If several page datas words to be written are arranged, will be heavily coated with last step, yet, if data write in the same block with constantly heavily covering, will produce many unnecessary actions of wiping off and move, this measure is not only lost time, also can shorten simultaneously the serviceable life of quickflashing, therefore, in the flash memory device of the present invention, when data write same block with heavily covering, it can avoid the action of wiping off, and the migration action also only just can be carried out when changing block, uses this kind method not only to prolong the life-span of quickflashing, has also improved the efficient of installing simultaneously.
Below be one and write data example, need the data of 32 block of cells (sector) are write in female block of logical address with 0/0 block/page or leaf beginning.Each block has 32 pages, total physical blocks/logical blocks is 1024/992, total spare blocks of FIFO is 32, none block is defective, obtain spare blocks from the FIFO spare area, the sub-block (physical address: 03E0h) take from the FIFO spare area, then of promptly initial index (Head pointer) indication, initial index can increase (pointing to next spare blocks), and 32 pages data are then write sub-block (physical address: 03E0h).Then female block of logical address 0000h indication is wiped off, and the tail end index of FIFO spare area is increased, then, the physical address of female block is then inserted in the address of the tail end index indication in the spare area, address 03E0h with sub-block inserts among the logical and physical address mapping table 0000h then, make logical address 0000h point to physical address 03E0h, promptly finish writing.
It below is write-in program narration according to the present invention concrete form.
In the write command and address parameter write store storage device of main frame with correspondence, memorizer memory devices begins executive routine quickflashing algorithm subsequently, then, the logical address of main frame can be converted into flash memory physical blocks and page or leaf block, and controller can check whether sub-block exists.
If the non-existent words of sub-block, it can take out a clean block from the FIFO queue be that the existing block that writes is set up a sub-block, then, check the existing flash memory logical page number, see whether the page number to be written equals " 0 ", if equal " 0 ", data from main frame to flash memory will write buffer zone, and the counting of block of cells can reduce, this program can heavily be covered till the block of cells counting equals " 0 " always, when if the page number to be written is not equal to " 0 ", the data of female block will move on the sub-block between " write in one page " and " existing write page ", and then, the data from main frame to flash memory can write the buffer zone, and the counting of block of cells can reduce, and this program can heavily be covered till the block of cells counting equals " 0 " always.
If sub-block exists, will check the logical blocks of existing flash memory, see to be written whether equaling in a flash memory logical block that writes, if it is unequal, the data of female block will move to the sub-block between " write in one page " and " this block in one page ", and then female block wiped off, logical and physical address mapping table in the update controller, replace original female block address with the sub-block address, then, the female block that to be wiped off is put back to becomes clean block in the FIFO queue, if the feature block of going into equals in the words of a flash memory logical block that writes, will check the existing flash memory logical page number, see to be written whether greater than in a flash memory page or leaf that writes, if greater than, to check the existing page number that writes, see whether it equaled to be write to add 1 in one page, if, data from main frame to flash memory will write buffer zone, and the counting of block of cells can reduce, this program can heavily be covered till the block of cells counting equals " 0 " always, if the existing page number that writes is not equal to the last page of being write and adds at 1 o'clock, the data of female block will move on the sub-block between " last page that writes " and " existing write page ".
If to be written being not more than when a flash memory logical page or leaf that writes, the data of female block will be moved to the sub-block between " write in one page " and " this block in one page ", and then female block wiped off, logical and physical address mapping table in the update controller, replace original female block address with the sub-block address, then, the female block that will be wiped off is put back to becomes clean block in the FIFO queue.
If it is to be written greater than when the flash memory logical page or leaf that writes, the data of female block will be moved to the sub-block between " write in one page " and " existing write page ", data from main frame to flash memory will write buffer zone, and the counting of block of cells can reduce, and data can write till the block of cells counting equals " 0 ".
Flash memory device fetch program aspect as for foundation the present invention concrete form, the logical address of main frame can be converted into flash memory physical blocks and page address, then, check existing flash memory logical block, see to be read whether equaling in a flash memory logical block that is read, if not words, the data of flash memory physical blocks and page or leaf will be read, and the counting of block of cells will reduce, this program can heavily be covered till the block of cells counting equals " 0 " always, if to be read equaling in the words of a flash memory logical block that is read, it can check existing flash memory logical page or leaf, see to be read whether greater than in a flash memory logical page or leaf that writes.
If, the data of flash memory physical blocks and page or leaf will be read, and the block of cells counting will reduce, this program can heavily be covered till the block of cells counting equals " 0 " always, if to be read being not more than in the words of a flash memory logical page or leaf that writes, the data of sub-block physical blocks and page or leaf will be read, and the block of cells counting will reduce, and this program can heavily be covered till the block of cells counting equals " 0 " always.
When microprocessor begins fill order, universal serial bus interface quick flash storage integrated circuit can be downloaded its parameter from main frame, for example read or write manufacturer order package, address pattern can be judged by the 6th bit that installs/open beginning bit group by system, the flash memory device of the present invention supports logical block addresses (LBA) and right cylinder to open beginning block of cells (CHS) pattern simultaneously, if host computer using LBA pattern provides the words of address, device can convert it to the CHS pattern, makes the CHS pattern into physical address then.
When universal serial bus interface quick flash storage integrated circuit is carried out reading order, controller at first can the buffer zone that reads controller (512 bit group) with the block of cells of a block of cells of data of flash memory in, the USB (universal serial bus) engine can be delivered to main frame with block of cells then, when the block of cells quantity of delivering to main frame equaled block of cells number that main frame desires to read, whole order had just been finished.
When universal serial bus interface quick flash storage integrated circuit is carried out write command, controller can be by the buffer zone that read controller (512 bit group) of USB (universal serial bus) engine with a block of cells of a block of cells of data of main frame, this block of cells will be stored in the flash memory then, when the block of cells quantity of delivering to flash memory equaled block of cells number that main frame desires to write, whole order had just been finished.
Universal serial bus interface quick flash storage integrated circuit can be supported more than one flash memory, provide a plurality of wafers to choose pin in the present invention, when starter gear, it can check connect the flash type (capacity) and the system that use what wafers arranged, universal serial bus interface quick flash storage integrated circuit can be added up all memory chips, find out total volume, when main frame needs the data of this class, universal serial bus interface quick flash storage integrated circuit will provide total volume to main frame, rather than the capacity of single wafer.
When main frame sends a certain address (logic) to universal serial bus interface quick flash storage integrated circuit, universal serial bus interface quick flash storage integrated circuit can be carried out calculating, find out access that main frame wants pellet and corresponding address really, then, universal serial bus interface quick flash storage integrated circuit can use the address of calculating, and the startup wafer is chosen pin.
Description of drawings
Fig. 1 is the universal serial bus interface quick flash storage integrated circuit schematic layout pattern that shows according to the present invention concrete form.
Fig. 2 is the universal serial bus interface quick flash storage integrated circuit controller synoptic diagram that shows according to the present invention concrete form.
Fig. 3 is the system architecture block synoptic diagram of the universal serial bus interface quick flash storage integrated circuit that shows according to the present invention concrete form.
Fig. 4 is the USB (universal serial bus) agreement application flow synoptic diagram of the operating system of all kinds that shows according to the present invention concrete form.
Fig. 5 shows the tabular parameter that is implemented into USB (universal serial bus) agreement in the universal serial bus interface quick flash storage integrated circuit according to the present invention concrete form.
Fig. 6 is the write-in program flow process that shows universal serial bus interface quick flash storage integrated circuit according to the present invention concrete form.
Fig. 7 is the fetch program flow process that shows universal serial bus interface quick flash storage integrated circuit according to the present invention concrete form.
Fig. 8 shows the block synoptic diagram that data is write new block according to the present invention concrete form.
Fig. 9 is the block synoptic diagram that shows the data that write extra page number according to the present invention concrete form.
Figure 10 is the block synoptic diagram that shows female and sub-technology according to the present invention concrete form.
Figure 11 is the synoptic diagram according to the present invention concrete form display logic and physical address mapping table.
Figure 12 shows the synoptic diagram that opens beginning index and the operation of tail end index according to the present invention concrete form.
Figure 13 shows according to the present invention concrete form not write logical and physical address mapping table synoptic diagram before.
Figure 14 shows the synoptic diagram that opens beginning index and the operation of tail end index according to the present invention concrete form.
Figure 15 is the order package configuration diagram that shows according to the present invention concrete form.
Embodiment
Explanation hereby, the general narration and following being described in detail of preamble are all example, and are intended to further explain described invention.
Accompanying drawing is in order to allow people can understand the present invention more, and enrolls and become the part of standard for this reason, the picture concrete manifestation the present invention, cooperate character narrate and then explained the principle of invention, in picture, the narration of preferential concrete manifestation:
Present stage will be made the reference details of the preferential concrete manifestation of the present invention, illustrate these examples in the accompanying drawing, all adopt identical Ref. No. at identical or similar part as much as possible in picture and the narration.
See also shown in Figure 1, the universal serial bus interface quick flash storage kind body circuit layout synoptic diagram that system shows according to the present invention concrete form, in figure, disclose universal serial bus interface quick flash storage integrated circuit 5 for having comprised a controller 40 and at least one flash memory die 50, and universal serial bus interface connector 10 is for to be connected between the main frame of universal serial bus interface quick flash storage integrated circuit 5 and tool USB (universal serial bus), and comprised a flash memory die 50 on the universal serial bus interface quick flash storage integrated circuit 5 at least, universal serial bus interface quick flash storage integrated circuit 5 has then comprised a storage type flash memory extending interface pin position 20 further, flash memory 120 quantity are extended, and storage type flash memory extending interface pin position 20 is for can butt up against on the flash memory 120, connect to utilize storage type flash memory extending interface pin position 20 that the controller 40 of universal serial bus interface quick flash storage integrated circuit 5 is formed, thus, the memory span of universal serial bus interface quick flash storage integrated circuit 5 just can be looked actual needs and expanded easily.
Moreover, its controller 40 is the primary clustering of this device, this controller 40 is order and data between the main frame of control USB (universal serial bus) and tool USB (universal serial bus), and the data in management flash memory die 50 and the flash memory 120, and preferably single-chip design that does not need external ROM or RAM of controller 40.
The storage type flash memory extending interface pin position 20 of universal serial bus interface quick flash storage integrated circuit 5, in order to connect flash memory 120 and universal serial bus interface quick flash storage integrated circuit 5, so that utilize extra flash memory 120 to extend memory size according to actual needs, and universal serial bus interface quick flash storage integrated circuit 5 comprises an extra flash memory die 50 at least, and it also can connect a plurality of flash memories 120 so that look actual needs extended memory quantity.
The I/O control interface 30 of universal serial bus interface quick flash storage integrated circuit 5, the input and output control that provides system need carry out other.
See also shown in Figure 2, the universal serial bus interface quick flash storage integrated circuit controller synoptic diagram that system shows according to the present invention concrete form, the controller 200 of the flash memory device of the present invention has myriad of functions, has a top to be control USB (universal serial bus) interface 210 in these functions.
Above-mentioned controller 200 is to abide by the USB (universal serial bus) standard aspect entity and logic agreement, and controller 200 has further comprised a system buffer 250 or fifo controller buffer zone.
Order and parameter package that controller 200 receives from main frame, this package is stored in the system buffer 250 by controller 200 definition subsequently, and controller 200 also is responsible for the data transmission between control and the USB (universal serial bus) main frame simultaneously, in addition, controller 200 also provides status data to main frame.
When main frame sends a write command, will produce the microprocessor 220 that interrupts and send in the controller, so that the position of 220 these orders of notice microprocessor and order.
Microprocessor 220 (for example microprocessor of one 8 or 16-bit) is a primary clustering in the controller 200, this microprocessor 220 reads the order and the parameter of USB (universal serial bus) from system buffer 250, in addition, microprocessor 220 is also carried out the order of tool parameter.
In addition, microprocessor 220 also is flash memory array management (for example wipe off, program or order such as read), and in addition, microprocessor 220 is also according to the algorithm executive address method of controller 200.
In order to the system buffer 250 of buffering USB (universal serial bus) interface 210 and flash memory array interface 260 for by as getting use soon, and the address of microprocessor 220 these buffer zones of management, if necessary, buffer zone can be by bit group or literal access.
The flash memory device of the present invention has comprised a hardware state machine further, reads and write sequential with what set up system buffer 250 between main frame and the flash memory.
Flash memory array interface 260 reads and write command for the control flash memory array, and in the concrete manifestation of the present invention, this is a pure hardware circuit.
When the data of getting soon when system buffer 250 write to flash memory array interface 260, the ECC circuit 270 ECC code of will encoding, and when the data that read flash memory array to the system buffer 250 when getting soon, 270 in ECC circuit is with the ECC code decoding, if the ECC mistake takes place, literal or the bit group during ECC circuit 270 meeting interpreting system buffer zones 250 are got soon also corrected mistake.
The I/O control that provides system need carry out other is provided I/O control interface 280.
See also shown in Figure 3, the system architecture block synoptic diagram of the universal serial bus interface quick flash storage integrated circuit that system shows according to the present invention concrete form, in the operating system (as Windows ME and Windows2000 etc.) of the main frame 300 of some tool USB (universal serial bus) for having comprised default USB interface device driver, other operating system may be installed a USB interface device driver at main frame, and the real work 320 of USB (universal serial bus) order has comprised the order that receives main frame 300 and parameter controller 305 by USB (universal serial bus) interface 310, and will order and parameter be stored in the controller 305 defined working storages, and can produce and send interrupt with the notice microprocessor received order.
See also shown in Figure 4 again, the USB (universal serial bus) agreement application flow synoptic diagram of the operating system of all kinds that system shows according to the present invention concrete form, when main frame during in step 410, system will order when writing in the universal serial bus interface quick flash storage integrated circuit with parameter, controller can be stored in it in specific working storage, and when step 420, produce one and interrupt to microprocessor, data subsequently can be when step 430 be read information from main frame by microprocessor.
In step 440, microprocessor begins fill order according to parameter, if order for write command, buffer zone get the data that will receive the main frame of tool USB (universal serial bus) in step 450 soon.
Microprocessor is converted to logical address the physical address of flash memory subsequently in step 460, in step 470, microprocessor will read the data of flash memory or data will be write in the flash memory, if order is reading order, data can transfer to the main frame of tool USB (universal serial bus) in step 480.
USB (universal serial bus) standard according to standard, require parameter to comprise 7 bits, see also shown in Figure 5, the D6-D5 bit of BmRequestType has been specified the type of order agreement, its kind comprises standard, grade and manufacturer, and this three types the agreement of the flash memory device of the present invention supports that all standard form is the matching requirements of standard, this is common order, as USB_Get_status orUSB_set_Feature etc.
The flash memory device of the present invention has utilized collocation bulk/ to control/interrupt the USB (universal serial bus) mass storage class of transmission on concrete form.
Because the physical constraints of quickflashing RAM, before finishing write command, must carry out earlier and wipe order off, general flash memory need be through just can normal operation after about 1,000,000 times the wiping off, so, reducing the step of wiping off is very important with the serviceable life that prolongs flash memory, and therefore, the present invention provides a logical and physical address mapping table and a mother/sub-framework to reach this target.
It below is the operation instruction of logical and physical address mapping table, when starting quickflashing, all blocks all can be searched, and entity that searches and the relation record between the logical blocks will become logical and physical address mapping table, in this while, untapped physical blocks is then put into spare blocks allows the FIFO queue use.
Then, the logical blocks in the logical and physical address mapping table can be used to seek corresponding physical blocks address, thus, just can accurately write or the data of acquisition and special entity block associated.
See also shown in Figure 8, system shows the block synoptic diagram that data is write new block according to the present invention concrete form, when data are write flash memory, the block (new block) 810 that may need a process to wipe off replaces old block 800, data are write in the new block 810 then, the data that to more not correct one's mistakes move to new block 810 from old block 800 at last, and this step has been finished the action that writes a page data.
If several page datas words to be written are arranged, will be heavily coated with last step, see also shown in Figure 9, system shows the block synoptic diagram of the data that write extra page number according to the present invention concrete form, this is the block synoptic diagram that shows the data that write extra page number according to the present invention concrete form, data are write in the new block 910, and the data of more not corrected one's mistakes move to new block 910 from old block 900.
Yet, if data write in the same block with constantly heavily covering, will produce many unnecessary actions of wiping off and move, this measure is not only lost time, and also can shorten the serviceable life of flash memory simultaneously.
See also shown in Figure 10, system shows the block synoptic diagram of female and sub-technology according to the present invention concrete form, this is the block synoptic diagram that shows female and sub-technology according to the present invention concrete form, therefore, in the flash memory device of the present invention, when data write same block with heavily covering, it can avoid the action of wiping off, just can carry out when changing block and move to move also to have only, all data all write earlier in the new block (sub-block) 1010, the data of more not corrected one's mistakes then then write the new block 1010 from old block (female block) 1000, use this kind method not only to prolong the life-span of flash memory, have also improved the efficient of installing simultaneously.
See also shown in Figure 11, system is according to the synoptic diagram of the present invention concrete form display logic and physical address mapping table, below be one and write data example, its logical and physical address mapping table has chained a physical blocks address 1100 and a logical block addresses 1110, need the data of 32 block of cells (sector) are write in the flash memory that begins with 0/0 block/page or leaf, total physical blocks/logical blocks is 1024/992, total spare blocks of FIFO is 32, none block is defective, and each block has 32 pages.
See also shown in Figure 12,13,14, system shows that according to the present invention concrete form synoptic diagram, the demonstration of opening beginning index and the operation of tail end index do not write logical and physical address mapping table synoptic diagram before, in this example, the address 03E0h of the sub-block 1300 of initial bid 1210 indications takes from FIFO spare area 1200, then, the address of initial index 1210 can increase, and the data that become 1410,32 pages of initial indexs then write in the sub-block 1300.
Again sub-block 1300 address 03E0h are inserted among the logical block addresses 0000h of female block 1310 in the logical and physical address mapping table, female block 1310 address 0000h are wiped off and 1220 increases of tail end index, then, female block address 0000h then inserts in the address of tail end index 1420 indications in the spare area.
To make the narration reference of write-in program according to the concrete manifestation of the present invention now.
Main frame writes corresponding write command and address parameter in the universal serial bus interface quick flash storage integrated circuit, and this device begins executive routine quickflashing algorithm subsequently.
See also shown in Figure 6, system shows the write-in program flow process of universal serial bus interface quick flash storage integrated circuit according to the present invention concrete form, at first, in step 601, the logical address that main frame is sent converts flash memory physical blocks and page address to.
Then in step 602, controller can be checked and see whether sub-block exists, if the non-existent words of sub-block, then skip to step 605, if sub-block exists, in step 603, can check the logical blocks of existing flash memory, see to be written whether equaling in a memory logic block that writes, if unequal, then skip to step 611.
If equate, in step 604, can check the existing flash memory logical page number, see write whether greater than in a flash memory logical page or leaf that writes, if, then continue step 610, if not, then skip to step 611.
Step 605 is got a clean block from the FIFO queue be that a sub-block is set up in existing write command.
Check the existing flash memory logical page number in step 606, see whether equal " 0 " to be written,, continue step 608 if equal " 0 ".
If be not equal to " 0 ", in step 607, the data of female block can be moved to the sub-block between " write in one page " and " existing write page ".
In step 608, the data of main frame to flash memory are write in the buffer zone, and the counting of block of cells can reduce.
In step 609, if the counting of block of cells equals " 0 ", then advance to " terminal point ", if not, then continue step 608.
In step 610, if the existing page number that writes equals to add 1 in writing the page number, then continue step 608, then continue step 607 if not.
In step 611, the data of female block can be moved to the sub-block between " write in one page " and " this block in one page ", and wipe female block off, and the logical and physical address mapping table in the update controller, replace female block address with the sub-block address, the female block that will be wiped off is returned in the FIFO queue as clean block simultaneously.
Seeing also shown in Figure 7ly, is the fetch program flow process that shows flash memory device according to the present invention concrete form.
In step 701, for the logical address with the main frame of tool USB (universal serial bus) converts flash memory entity and page address to.
In step 702, check existing flash memory, see to be read whether equaling in a flash memory logical block that reads, if, then skip to step 705, if not, continue step 703.
In step 703, read the flash memory physical blocks and the page or leaf data and the counting of block of cells can reduce.
In step 704, check the block of cells counting, see whether it can equal " 0 ",, then advance to " terminal point ", if not, then get back to step 703 if equal " 0 ".
In step 705, check the existing memory logical page (LPAGE), see to be read whether greater than the flash memory logical page or leaf that writes at last, if, get back to step 703, if not, advance to step 706.
In step 706, read the data of sub-block physical blocks and page or leaf, and the counting of block of cells can reduce.
In step 707, check the block of cells counting, see whether it can equal " 0 ",, then advance to " terminal point ", if not, then get back to step 705 if equal " 0 ".
See also shown in Figure 15, the order package configuration diagram that system shows according to the present invention concrete form, when microprocessor begins fill order, universal serial bus interface quick flash storage integrated circuit can be downloaded its parameter from main frame, for example read or write, shown manufacturer's order package among the figure.
Address pattern can be judged by installing/open beginning bit group by system, and the flash memory device of the present invention supports logical block addresses (LBA) and right cylinder to open beginning block of cells (CHS) pattern simultaneously.
If host computer using LBA pattern provides the address, device can convert it to the CHS pattern, makes the CHS pattern into physical address then.
When universal serial bus interface quick flash storage integrated circuit is carried out reading order, controller at first can the buffer zone that reads controller (512 bit group) with the block of cells of a block of cells of data of flash memory in, the USB (universal serial bus) engine can be delivered to main frame with block of cells then, when the block of cells quantity of delivering to main frame equaled block of cells number that main frame desires to read, whole order had just been finished.
When universal serial bus interface quick flash storage integrated circuit is carried out write command, controller can be by the buffer zone that read controller (512 bit group) of USB (universal serial bus) engine with a block of cells of a block of cells of data of main frame, this block of cells will be stored in the flash memory then, when the block of cells quantity of delivering to flash memory equaled block of cells number that main frame desires to write, whole order had just been finished.
Universal serial bus interface quick flash storage integrated circuit can be supported more than one flash memory, provide a plurality of wafers to choose pin in the present invention, when starter gear, it can check what flash memories flash memory type (capacity) and system that storage type flash memory extending interface pin position is connected have, device can be added up all flash memories, find out total volume, when main frame needs the data of this class, universal serial bus interface quick flash storage integrated circuit will provide total volume to main frame, rather than the capacity of single flash memory.
When main frame sends a certain address (logic) to universal serial bus interface quick flash storage integrated circuit, universal serial bus interface quick flash storage integrated circuit can be carried out calculating, find out access that main frame wants pellet and corresponding address really, then, device can use the address of calculating, and the startup wafer is chosen pin.
In addition, flash memory die, the controller that reaches described in the present invention is single-chip design, in order to dwindling the overall volume of universal serial bus interface quick flash storage integrated circuit, and do not need the design of external random access storer (RAM) or ROM (read-only memory) (ROM).
For those people that skillful technology is arranged, clearly this framework can carry out modifications and variations miscellaneous down what do not depart from former scope of invention and spirit, in view of preamble described, its purpose be in the claim scope with and the condition of equal meaning under, the present invention has contained the related amendments and the variation of this invention.
Claims (6)
1, a kind of universal serial bus interface quick flash storage integrated circuit, be provided with controller, this controller comprises the system buffer, microprocessor, state machine, the USB (universal serial bus) interface, I/O control interface and flash memory interface, and described microprocessor is connected with the system buffer, the USB (universal serial bus) interface, I/O control interface and flash memory interface, described flash memory interface connects flash memory, described controller and at least one flash memory die are packaged into described integrated circuit, in order to order and the data between main control system and the described integrated circuit; The pin position of described integrated circuit encapsulation comprises:
USB (universal serial bus) USB interface pin position is in order to be connected to universal serial bus interface quick flash storage integrated circuit in the main frame of tool USB (universal serial bus) USB;
Flash memory extending interface pin position makes the external again storage type flash memory of universal serial bus interface quick flash storage integrated circuit with the increase capacity; And
I/O control interface pin position.
2, universal serial bus interface quick flash storage integrated circuit as claimed in claim 1, comprised an error correction code ECC circuit that is connected with described flash memory interface further, so that coding ECC when data write flash memory device, and the ECC that when reading the data of flash memory device, decodes.
3, universal serial bus interface quick flash storage integrated circuit as claimed in claim 2, wherein when taking place and righting the wrong, the ECC circuit is judged the invalid data address further.
4, universal serial bus interface quick flash storage integrated circuit as claimed in claim 1, wherein flash memory die, controller are single-chip design, in order to dwindle the overall volume of universal serial bus interface quick flash storage integrated circuit.
5, universal serial bus interface quick flash storage integrated circuit as claimed in claim 1, wherein said controller also is used for managing the data of at least one flash memory;
Described microprocessor is used to carry out the order that main frame has parameter;
Described system buffer provides the buffering between main frame and the flash memory device;
Described state machine is for sequential is read and writes in system buffer foundation.
6, universal serial bus interface quick flash storage integrated circuit as claimed in claim 1, its middle controller are one not need the single-chip design of external random access memory RAM or read only memory ROM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011403772A CN100345126C (en) | 2001-12-17 | 2001-12-17 | Universal serial bus interface quick flash storage integrated circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB011403772A CN100345126C (en) | 2001-12-17 | 2001-12-17 | Universal serial bus interface quick flash storage integrated circuit |
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| CN1427350A CN1427350A (en) | 2003-07-02 |
| CN100345126C true CN100345126C (en) | 2007-10-24 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100556907B1 (en) * | 2003-10-20 | 2006-03-03 | 엘지전자 주식회사 | Nand-type flash memory |
| CN101599295B (en) * | 2008-06-02 | 2011-12-07 | 联阳半导体股份有限公司 | integrated storage device and control method thereof |
| CN102110462B (en) * | 2009-12-25 | 2015-09-30 | 旺宏电子股份有限公司 | Addressing one stores the method and apparatus of integrated circuit |
| CN109725250B (en) * | 2019-01-04 | 2021-07-13 | 珠海亿智电子科技有限公司 | System and method for testing system-on-chip analog circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5799168A (en) * | 1996-01-05 | 1998-08-25 | M-Systems Flash Disk Pioneers Ltd. | Standardized flash controller |
| CN2405269Y (en) * | 1999-11-13 | 2000-11-08 | 邓国顺 | Quick-flashing electronic type external type memory device used for data processing system |
| US6246578B1 (en) * | 2000-01-23 | 2001-06-12 | Tzu Hsiang Wei | Computer-dedicated auxiliary data access device |
| CN1304509A (en) * | 1999-04-05 | 2001-07-18 | M-系统快闪盘开拓者公司 | Architecture for universal serial bus-based PC flash disk |
| CN1304115A (en) * | 1999-11-24 | 2001-07-18 | 姚立和 | Storage card with double interface and its conversion module |
-
2001
- 2001-12-17 CN CNB011403772A patent/CN100345126C/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5799168A (en) * | 1996-01-05 | 1998-08-25 | M-Systems Flash Disk Pioneers Ltd. | Standardized flash controller |
| CN1304509A (en) * | 1999-04-05 | 2001-07-18 | M-系统快闪盘开拓者公司 | Architecture for universal serial bus-based PC flash disk |
| CN2405269Y (en) * | 1999-11-13 | 2000-11-08 | 邓国顺 | Quick-flashing electronic type external type memory device used for data processing system |
| CN1304115A (en) * | 1999-11-24 | 2001-07-18 | 姚立和 | Storage card with double interface and its conversion module |
| US6246578B1 (en) * | 2000-01-23 | 2001-06-12 | Tzu Hsiang Wei | Computer-dedicated auxiliary data access device |
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