CN1253795C - Universal serial bus structural flash memory device - Google Patents
Universal serial bus structural flash memory device Download PDFInfo
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- CN1253795C CN1253795C CN 02108242 CN02108242A CN1253795C CN 1253795 C CN1253795 C CN 1253795C CN 02108242 CN02108242 CN 02108242 CN 02108242 A CN02108242 A CN 02108242A CN 1253795 C CN1253795 C CN 1253795C
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Abstract
The present invention relates to a storing device for a universal serial bus structural quick flashing memory. The present invention at least comprises a universal serial bus structure connector for connecting the storing device of the quick flashing memory to a main machine with the universal serial bus structure connector, at least one quick flashing memory die set or array for storing data, a controller for controlling commands and data between the main machine and the storing device of the quick flashing memory and managing the data in at least one quick flashing memory die set. The present invention is connected with the main machine through a universal serial bus structure, so the main machine can rapidly store the data to the device or read the data in the device. The main machine is connected with the device and interacts with the device easily.
Description
Technical field
The present invention relates to a kind of storer, especially can pass through a kind of universal serial bus structural flash memory device that universal serial bus structural (USB) connects.
Background technology
The portability of flash memory and the characteristic that can not erase make it become the important media of storage data, for for mancarried devices such as hand-held electronic device, this is a kind of very useful data storing mode, and the convenience that flash memory brought makes its storage device more traditional than major part (as rigid magnetic disc etc.) have bigger advantage, except portability, the advantage of flash memory also has advantages such as low power consumption rate, reliability, light and handy and high speed.
Flash memory is nonvolatile, still possess the data that stored even this expression power supply has been closed it, this random-access memory (ram) than standard is more progressive, and random access memory is volatile, therefore when power supply is closed, will lose the data that stored.
Increase along with movable-type, portable or palmtop device, flash memory is also favored gradually, the most general flash memory type is the memory card of removable formula, and this kind memory card is able to transmit between electronic installation or computer easily by the content of flash memory.
Yet, between electronic installation, need extra bus-bar interface or breakout box during mobile flash memory, so that allow main frame be able to carry out communication with flash memory cards, many electronic installations may not have built-in and the ability flash memory card connection, therefore just a special breakout box or card must be installed in main frame, in addition, the structure of its bus-bar just may restricting host and flash memory device between the transmission speed of data.
Therefore, people need the flash memory device that can not need special cable or breakout box just can directly be connected with main frame.
Summary of the invention
In order to reach these and other advantages, also have in order to overcome the shortcoming of traditional flash memory card, the present invention promptly provides a kind of universal serial bus structural flash memory device, and it is a kind of flash memory device that can be connected with main frame by universal serial bus structural.
Universal serial bus structural (being designated hereinafter simply as USB) has become the sequence interface of standard, it allows data be stored in USB flash memory device and reading of data from flash memory device apace apace, therefore, in conjunction with the speed of the advantage of flash memory device and USB with highly beneficial, in addition, flash memory device by design collocation USB interface, can make flash memory device become the USB storage device of standard, main frame can be linked to each other easily and interactive with flash memory device, and the capacity of this extension storage device easily.
For achieving the above object, universal serial bus structural flash memory device of the present invention includes at least: a universal serial bus structural connector, in order to flash memory device is connected to the main frame of tool universal serial bus structural connector; At least one flash memory module or array are with storage data; A controller in order to order between main control system and the flash memory device and data, and is managed data at least one flash memory module; And an accessory circuit plate that extends the memory size of this flash memory device, it comprises a flash memory module at least.
Particularly, the main circuit board of flash memory device has comprised a controller and at least one flash memory, and USB connector is connected the main frame of flash memory device with tool USB, flash memory on the main circuit board has comprised a flash memory die at least, as mentioned above, the memory span of this flash memory device can be expanded easily.
Controller is a primary clustering of device, this controller has been controlled order and the data between flash memory storage flash memorizer memory devices and the main frame, and the data in management flash memory array or the module, controller is a single-chip design that does not need random-access memory (ram) or ROM (read-only memory) (ROM) preferably.
The present invention also comprises: regulator is the voltage of scalable flash memory device, generally speaking, flash memory needs 3.3 volts or 5.0 volts of voltages, some flash memory devices are looked need switching of flash memory by the mode of switching between 3.3 volts or 5.0 volts, yet, an advantage of flash memory device of the present invention flash memory device for this reason only needs 3.3 volts, therefore, no matter what main frame sent is 5.0 volts or 3.3 volts, regulator can guarantee that all voltage is 3.3 volts and uses for the USB transceiver, and does not need to detect and changing voltage.
Clock pulse generator is as crystallization, for the controller at flash memory device has produced a clock signal.
The flash memory device of concrete manifestation of the present invention has been for having comprised an indicator (for example LED indicator) further, in order to the state of instruction memory storage device in using or holding state.
The main circuit board of flash memory device also can have a bay connector, in order to connect accessory circuit plate and main circuit board, so that utilize flash memory array to extend memory size, and the accessory circuit plate comprises an extra flash memory module or an array at least, it also can connect a plurality of accessory circuit plates, so that ad infinitum extended memory uses.
The write protection switch is one and prevents that main frame from writing the switch of data; this switch has two positions at least; one allows main frame normally can read and write; another position then is that protection writes; when switch is positioned at the position that writes protection; main frame just can only reading of data, but can't write or obliterated data.
The controling appliance of flash memory device of the present invention has myriad of functions, there is one to be control USB interface in these functions, controller is abideed by the USB standard aspect entity and logic agreement, controller has further comprised a FIF0 controller buffer zone, make the controller reception carry out package from the order and the parameter of the main frame of tool USB, this package is stored in the special working storage by the controller definition subsequently, and controller also is responsible for the data transmission between control and the main frame simultaneously, in addition, controller also provides status data to main frame.
When main frame sends a write command, will produce and interrupt and send to controller and microprocessor, so that the position of this order of notice microprocessor and order, this microprocessor (for example microprocessor of one 8 or 16-bit) is a primary clustering of controller, and microprocessor reads order and the parameter of USB from working storage, in addition, and microprocessor is also carried out the order of tool parameter, microprocessor is managed on the one hand and is shone upon USB FIF0 address to the controller buffer zone, receive on the one hand from the data of the main frame of tool USB and with data transmission to main frame, in addition, microprocessor also is the flash memory array management, for example wipe, program or order such as read, in addition, microprocessor is also according to the algorithm executive address method of controller.
The director demon code that ROM (read-only memory) (ROM) is built in the controller in inciting somebody to action is stored, and microprocessor controller employed system random access memory (RAM) when carrying out USB order or quickflashing algorithm, because it does not need to leave the wafer storer, therefore reduced the cost of system.
In order to the system buffer of buffering USB interface and flash memory array interface by as getting use soon, it also is simultaneously the FIF0 of USB agreement and the directional diagram that arrives buffer zone, the address of this buffer zone of microprocessor management, if necessary, buffer zone can carry out access by bit group or literal.
Flash memory device of the present invention has comprised a hardware state machine further, read and write sequential with what set up system buffer between main frame and the flash memory, quickflashing interface and circuit have been controlled reading of flash memory array and write command, in concrete manifestation of the present invention, this is a pure hardware circuit.
In addition, when the data of getting soon when buffer zone write to flash memory array, the ECC circuit ECC code of will encoding, and when the data that read flash memory array when buffer zone is got soon, the ECC circuit is then with the ECC code decoding, if the ECC mistake takes place, literal or the bit group during ECC circuit meeting interpretation buffer zone is got soon also corrected mistake.
USB order receives the order and the parameter control device of main frame actual having comprised, and will order and parameter is stored in the defined working storage of controller, and can produce and send and interrupt, and has received order to notify microprocessor.
Controller receives the data of main frame and sends the data to main frame according to USB logic and entity standard, and address approach comprised the wiping of management flash memory, read and the mapping to logic of write command and management entity.
When main frame will order and parameter write store storage device in the time, controller can be stored in it in specific working storage, data can be read as information from main frame by microprocessor subsequently, USB standard according to standard, require parameter for having comprised 7 bits, BmRequestType D6-D5 bit has been specified the type of order agreement, kind comprises standard, grade and manufacturer, this agreement of three types of flash memory device of the present invention is all supported, standard form is the matching requirements of standard, this is common order, as USB_Get_Status or USB_set_Feature etc.
Flash memory device of the present invention has utilized collocation bulk/ to control/interrupt the USB mass storage class of transmission on concrete form.
Because the restriction on the flash memory entity, before carrying out write command, must carry out erase command earlier, general flash memory needs after excessive 1,000,000 times wipe just can normal operation, so, reducing the step of wiping is very important with the serviceable life that prolongs flash memory, therefore, the invention provides a logic and physical address mapping table, and a mother/sub-framework reaches this target.
It below is the operation instruction of logic and physical address mapping table, when starting flash memory, all blocks all can be searched, and entity that searches and the relation record between the logical blocks will become the communication table, meanwhile, untapped physical blocks is then put into spare blocks allows the FIF0 formation use, then, logical blocks in logic and the physical address mapping table can be used to seek corresponding physical blocks address, thus, just can accurately write or the data of acquisition and special entity block associated.
When data are write flash memory, the block (new block) that may need a process to wipe replaces old block, then data are write in the new block, the data that will more not correct one's mistakes move to new block from old block at last, and this step has been finished the action that writes a page data.
If there are several page datas to hold the words that write, will repeat above step, yet, if data constantly repeatedly write in the same block, will produce many unnecessary actions of wiping and move, this measure is not only lost time, also can shorten simultaneously the serviceable life of flash memory, therefore, in flash memory device of the present invention, when data repeatedly write same block, it can avoid the action of wiping, and the migration action also only just can be carried out when changing block, uses this kind method not only to prolong the life-span of flash memory, and the while has also been improved the efficient of flash memory device.
Below be one and write data example, need the data of 32 block of cells (sector) are write in the flash memory that begins with 0/0 block/page or leaf, total physical blocks/logical blocks is I024/992, total spare blocks of FIF0 is 32, none block has flaw, each block has 32 pages, the sub-block 03E0h of initial index (Headpointer) indication takes from the FIF0 spare area, then, initial index can increase, 32 pages data then write in the sub-block, sub-block 03E0h is inserted among the logical block addresses 0000h of female block in logic and the physical address mapping table, female block 0000h is wiped free of and the increase of tail end index, and then, female block 0000h then inserts in the address of the tail end index indication in the spare area.
It below is write-in program narration according to concrete form of the present invention.
Main frame writes the write command and the address parameter of correspondence in the flash memory device, flash memory device begins executive routine quickflashing algorithm subsequently, then, the logical address of main frame can be converted into flash memory physical blocks and page or leaf block, and controller can check whether sub-block exists.
If the non-existent words of sub-block, it can take out a clean block from the FIF0 formation be that the existing block that writes is set up a sub-block, check the existing flash memory logical page number then, see whether equal " 0 " to be written, if equal " 0 ", data from main frame to flash memory will write buffer zone, and the counting of block of cells can reduce, this program can be repeated until that the block of cells counting equals till " 0 ", if during to be written being not equal to " 0 ", the data of female block (clean) will move on the sub-block between " last page that writes " and " existing write page ", then, data from main frame to flash memory can write the buffer zone, and the counting of block of cells can reduce, and this program can be repeated until that the block of cells counting equals till " 0 ".
If sub-block exists, will check the logical blocks of existing flash memory, see the flash memory logical block that last writes that whether equals to be written, if it is unequal, the data of female block will move to the last page that writes and the sub-block between " last page of this block ", and then with female block erase, logic in the update controller and physical address mapping table, replace original female block address with the sub-block address, then, the female block that is wiped free of put back to becomes clean block in the FIF0 formation, if the words that equal last flash memory logical block that writes to be written, will check the existing flash memory logical page number, see to be written whether greater than last flash memory page or leaf that writes, if greater than, to check the existing page number that writes, see that the last page whether it equals to be write adds 1, if, data from main frame to flash memory will write buffer zone, and the counting of block of cells can reduce, this program can be repeated until that the block of cells counting equals till " 0 ", if the existing page number that writes is not equal to the last page of being write and adds at 1 o'clock, the data of female block (clean) will move to " on the sub-block between the last page that writes and " existing write page ".
If it is to be written when being not more than last flash memory logical page or leaf that writes, the data of female block will be moved to the sub-block between " last page that writes " and " last page of this block ", and then with female block erase, logic in the update controller and physical address mapping table, replace original female block address with the sub-block address, then, the female block that is wiped free of is put back to become clean block in the FIF0 formation.
If hold write greater than last flash memory logical page or leaf that writes the time, the data of female block will be moved to the sub-block between " last page that writes " and " the existing page or leaf that writes ", data from main frame to flash memory will write buffer zone, and the counting of block of cells can reduce, and data can write till the block of cells counting equals " 0 ".
Flash memory device fetch program aspect as for foundation concrete form of the present invention, the logical address of main frame can be converted into flash memory physical blocks and page address, then, check existing flash memory logical block, see the flash memory logical block that last is read that whether equals to be read, if not words, the data of flash memory physical blocks and page or leaf will be read, and the counting of block of cells will reduce, this program can be repeated until that the block of cells counting equals till " 0 ", if the words that equal last flash memory logical block that is read to be read, whether it can check existing flash memory logical page or leaf, see to be read greater than last flash memory logical page or leaf that writes.
If, the data of flash memory physical blocks and page or leaf will be read, and the block of cells counting will reduce, this program can be repeated until that the block of cells counting equals till " 0 ", if the words that are not more than last flash memory logical page or leaf that writes to be read, the data of sub-block physical blocks and page or leaf will be read, and the block of cells counting will reduce, and this program can be repeated until that the block of cells counting equals till " 0 ".
When microprocessor begins fill order, flash memory device can be downloaded its parameter from main frame, for example read or write manufacturer order package, address pattern can be judged by the 6th bit that installs/open beginning bit group by system, flash memory device while support logic block address (LBA) of the present invention and right cylinder open beginning block of cells (CHS) pattern, if host computer using LBA pattern provides the words of address, flash memory device can convert it to the CHS pattern, makes the CHS pattern into physical address then.
When flash memory device is carried out reading order, controller at first can the buffer zone that reads controller (512 bit group) with the block of cells of a block of cells of data of flash memory in, the USB engine can be delivered to main frame with block of cells then, when the block of cells quantity of delivering to main frame equaled block of cells number that main frame desires to read, whole order had just been finished.
When flash memory device is carried out write command, controller can be by the buffer zone that read controller (512 bit group) of USB engine with a block of cells of a block of cells of data of main frame, this block of cells will be stored in the flash memory then, when the block of cells quantity of delivering to flash memory equaled block of cells number that main frame desires to write, whole order had just been finished.
Flash memory device can be supported more than one flash memory, provide a plurality of wafers to choose pin among the present invention, when starting flash memory device, employed flash memory type (capacity) on its meeting inspection plate, and what wafers are system have, flash memory device can be added up all memory chips, find out total volume, when main frame needs the data of this class, flash memory device will provide total volume to main frame, rather than the capacity of single wafer.
When main frame sends a certain address (logic) to flash memory device, flash memory device can be carried out calculating, find out access that main frame wants pellet really, and corresponding address, then, flash memory device can use the address of calculating, and the startup wafer is chosen pin.
Description of drawings
Figure 1A: the flash memory device schematic layout pattern that shows according to concrete form of the present invention;
Figure 1B: accessory circuit plate schematic layout pattern in the flash memory device that shows according to concrete form of the present invention;
Fig. 2: the flash memory device controller synoptic diagram that shows according to concrete form of the present invention;
Fig. 3: the system architecture block synoptic diagram of the flash memory device that shows according to concrete form of the present invention;
Fig. 4: the USB agreement application flow synoptic diagram of the operating system of all kinds that shows according to concrete form of the present invention;
Fig. 5: show the tabular parameter that is implemented into USB agreement in the flash memory device according to concrete form of the present invention;
Fig. 6: the write-in program flow process that shows flash memory device according to concrete form of the present invention;
Fig. 7: the fetch program flow process that shows flash memory device according to concrete form of the present invention;
Fig. 8: show the block synoptic diagram that data is write new block according to concrete form of the present invention;
Fig. 9: the block synoptic diagram that shows the data that write extra page number according to concrete form of the present invention;
Figure 10: the block synoptic diagram that shows female and sub-technology according to concrete form of the present invention;
Figure 11: according to the synoptic diagram of concrete form display logic of the present invention and physical address mapping table;
Figure 12: the synoptic diagram that shows initial index and the operation of tail end index according to concrete form of the present invention;
Figure 13: do not write logic and physical address mapping table synoptic diagram before according to concrete form demonstration of the present invention;
Figure 14: the synoptic diagram that shows initial index and the operation of tail end index according to concrete form of the present invention;
Figure 15: according to the order package configuration diagram of concrete form demonstration of the present invention.
Embodiment
Explanation hereby, the general narration and following being described in detail of preamble are all example, and will further explain described invention.
Accompanying drawing is in order to allow people can understand the present invention more, and enrolls and become a part of the present invention, the picture concrete manifestation the present invention, cooperate character narrate and then explained the principle of invention, in picture, the narration of preferential concrete manifestation.
See also Figure 1A, shown in the 1B, the flash memory device schematic layout pattern and the accessory circuit plate schematic layout pattern that show for foundation concrete form of the present invention, the main circuit board 100 that discloses flash memory device 5 in figure has comprised a controller 40 and at least one flash memory die 50, and USB connector 10 is connected between the main frame of flash memory device 5 and tool USB, and comprised a flash memory die 50 on the main circuit board 100 at least, flash memory device 5 has then comprised one further and has extended bay connector 20, can allow flash memory 120 arrays or module quantity on the accessory circuit plate 150 be extended, and extension bay connector 20 can butt up against the bay connector 110 on the accessory circuit plate 150, be connected to utilize bay connector 110 that flash memory 120 arrays or module and controller 40 on the main circuit board 100 are formed, thus, the memory span of flash memory device 5 just can be looked actual needs and expanded easily.
Moreover, its controller 40 is the primary clustering of this flash memory device 5, order and data between the main frame of this controller 40 control USB and tool USB, and the data in management flash memory 120 arrays or the module, and preferably single-chip design that does not need external random access storer (RAM) or ROM (read-only memory) (ROM) of controller 40.
In addition, regulator 90 is responsible for regulating the voltage of flash memory device 5, generally speaking, this flash memory needs the voltage of 3.3 volts or 5.0 volts, the mode that some flash memory devices 5 are looked the needs utilization conversion of flash memory 120 is switched between 3.3 volts or 5.0 volts, yet, an advantage of flash memory device 5 of the present invention is 3.3 volts of 5 needs of flash memory device for this reason, therefore, no matter what main frame sent is 5.0 volts or 3.3 volts, its regulator 90 can guarantee that all voltage is that 3.3 volts of supply flash memory devices 5 use, and does not need detecting and changing voltage.
Clock pulse generator 80 as crystallization, has produced a clock signal at the controller 40 of flash memory device 5.
The flash memory device 5 of concrete manifestation of the present invention has comprised an indicator 70 (for example LED indicator) further, and the state that can indicate flash memory device 5 is in use or the holding state.
The main circuit board 100 of flash memory device 5 also can have a bay connector 20, in order to connect accessory circuit plate 150 and main circuit board 100, so that utilize extra flash memory 120 arrays or module to extend memory size according to actual needs, and accessory circuit plate 150 comprises extra flash memory 120 arrays or module at least, it also can connect a plurality of accessory circuit plates 150, so that look actual needs extended memory quantity.
Protection switch 30 is one can prevent that main frame from writing the switch of data, Protection switch 30 has two positions at least, one allows main frame normally can read and write use, another position then is to prevent to write, when switch 30 is positioned at the position that prevents to write, main frame just can only reading of data, and can't write or obliterated data.
This flash memory device 5 further comprises an indicator 70 (for example LED indicator), in order to the state of instruction memory storage device 5 in using or holding state.
See also shown in Figure 2, the flash memory device controller synoptic diagram that shows for foundation concrete form of the present invention, the controller 200 of flash memory device of the present invention has myriad of functions, has one to be control USB interface 210 in these functions.
Above-mentioned controller 200 is abideed by the USB standard aspect entity and logic agreement, and controller 200 has further comprised a system buffer 250 or FIF0 controller buffer zone.
Order and parameter package that controller 200 receives from main frame, this package is stored in the system buffer 250 by controller 200 definition subsequently, and controller 200 also is responsible for the data transmission between control and the usb host simultaneously, in addition, controller 200 also provides status data to main frame.
When main frame sends a write command, will produce the microprocessor 220 that interrupts and send in the controller, so that the position of 220 these orders of notice microprocessor and order.
Microprocessor 220 (for example microprocessor of one 8 or 16-bit) is a primary clustering in the controller 200, and this microprocessor 220 reads order and the parameter of USB from system buffer 250, and in addition, microprocessor 220 is also carried out the order of tool parameter.
In addition, microprocessor 220 also is flash memory array management (for example wipe, program or order such as read), and in addition, microprocessor 220 is also according to the algorithm executive address method of controller 200.
In order to the system buffer 250 of buffering USB interface 210 and flash memory array interface 260 by as getting use soon, it also is simultaneously the FIF0 of USB agreement and the directional diagram that arrives buffer zone, and the address of microprocessor 220 these buffer zones of management, if necessary, buffer zone can be by bit group or literal access.
Flash memory device of the present invention has comprised a hardware state machine further, reads and write sequential with what set up system buffer 250 between main frame and the flash memory.
Reading and write command of flash memory array interface 260 control flash memory arrays, in concrete manifestation of the present invention, this is a pure hardware circuit.
When the data of getting soon when system buffer 250 write to flash memory array interface 260, the ECC circuit 270 ECC code of will encoding, and when the data that read flash memory array to the system buffer 250 when getting soon, 270 in ECC circuit is with the ECC code decoding, if the ECC mistake takes place, literal or the bit group during ECC circuit 270 meeting interpreting system buffer zones 250 are got soon also corrected mistake.
I/O control interface 280, the I/O control that provides system need carry out other.
See also shown in Figure 3, the system architecture block synoptic diagram of the flash memory device that shows for foundation concrete form of the present invention, in the operating system (as Wind Ows ME and WindOws 2000 etc.) of the main frame 300 of some tool USB, comprised default USB device driver, other operating system may be installed a USB device driver at main frame, and the real work 320 of USB order has comprised the order that receives main frame 300 and parameter controller 305 by USB connector 310, and will order and parameter be stored in the controller 305 defined working storages, and can produce and send and interrupt, receive order with the notice microprocessor.
See also shown in Figure 4, the USB agreement application flow synoptic diagram of the operating system of all kinds that shows for foundation concrete form of the present invention, when main frame will be ordered and parameter when writing in the flash memory device in step 410, controller can be stored in the specific working storage, and when step 420, produce one and interrupt to microprocessor, data subsequently can be when step 430 be read information from main frame by microprocessor.
In step 440, microprocessor begins fill order according to parameter, if order for write command, buffer zone get the data that will receive the main frame of tool USB in step 450 soon.
Microprocessor is converted to logical address the physical address of flash memory subsequently in step 460, in step 470, microprocessor will read the data of flash memory or data will be write in the flash memory, if order is reading order, data can transfer to the main frame of tool USB in step 480.
USB standard according to standard, require parameter to comprise 7 bits, see also shown in Figure 5 again, the D6-D5 bit of BmRequest Type has been specified the type of order agreement, its kind comprises standard, grade and manufacturer, and this agreement of three types of flash memory device of the present invention is all supported, and standard form is the matching requirements of standard, this is common order, as USB_Get_Status or USB_set_Feature etc.
Flash memory device of the present invention has utilized collocation bulk/ to control/interrupt the USB mass storage class of transmission on concrete form.
Because the physical constraints of flash memory, before finishing write command, must carry out erase command earlier, general flash memory need be through just can normal operation after about 1,000,000 times the wiping, so, reduce the step of wiping, be very important serviceable life with the prolongation flash memory, therefore the invention provides a logic and physical address mapping table, and a mother/sub-framework reaches this target.
It below is the operation instruction of logic and physical address mapping table, when starting quickflashing, all blocks all can be searched, and entity that searches and the relation record between the logical blocks will become the communication table, in this while, untapped physical blocks is then put into spare blocks allows the FIF0 formation use.
Then, the logical blocks in logic and the physical address mapping table can be used to seek corresponding physical blocks address, thus, just can accurately write or the data of acquisition and special entity block associated.
See also shown in Figure 8, show the block synoptic diagram that data is write new block for foundation concrete form of the present invention, when data are write flash memory, the block (new block) 810 that may need a process to wipe replaces old block 800, data are write in the new block 810 then, the data that to more not correct one's mistakes move to new block 810 from old block 800 at last, and this step has been finished the action that writes a page data.
If several page datas words to be written are arranged, will repeat above step, see also shown in Figure 9, show the block synoptic diagram of the data that write extra page number for foundation concrete form of the present invention, this is the block synoptic diagram that shows the data that write extra page number according to concrete form of the present invention, data are write in the new block 910, and the data of more not corrected one's mistakes move to new block 910 from old block 900.
Yet, if data constantly repeatedly write in the same block, will produce many unnecessary actions of wiping and move, this measure is not only lost time and also can be shortened the serviceable life of flash memory simultaneously.
See also shown in Figure 10, the block synoptic diagram that shows female and sub-technology for foundation concrete form of the present invention, this is the block synoptic diagram that shows female and sub-technology according to concrete form of the present invention, therefore, in flash memory device of the present invention, when data repeatedly write same block, it can avoid the action of wiping, just can carry out when changing block and move to move also to have only, all data all write earlier in the new block (sub-block) 1010, the data of more not corrected one's mistakes then then write the new block 1010 from old block (female block) 1000, use this kind method not only to prolong the life-span of flash memory, the while has also been improved the efficient of flash memory device.
See also shown in Figure 11, synoptic diagram for foundation concrete form display logic of the present invention and physical address mapping table, below be one and write data example, its logic and physical address mapping table have chained a physical blocks address 1100 and a logical block addresses 1110, need the data of 320 block of cells (Sector) are write in the flash memory that begins with 0/0 block/page or leaf, total physical blocks/logical blocks is 1024/992, total spare blocks of FIF0 is 32, none block has flaw, and each block has 32 pages.
See also shown in Figure 12,13 and 14, the synoptic diagram that shows initial index and the operation of tail end index for foundation concrete form of the present invention, show logic and physical address mapping table synoptic diagram before not writing, and the synoptic diagram of initial index of demonstration and the operation of tail end index, in this example, the address 03E0h of the sub-block 1300 of initial index 1210 indications takes from FIF0 spare area 1200, then, the address of initial index 1210 can increase, the data that become 1410,32 pages of initial indexs then write in the sub-block 1300.
Again sub-block 1300 address 03E0h are inserted among the logical block addresses 0000h of female block 1310 in logic and the physical address mapping table, female block 1310 address 0000h are wiped free of, and tail end index 1220 increases, then, female block address 0000h then inserts in the address of tail end index 1420 indications in the spare area.
To make the narration reference of write-in program according to concrete manifestation of the present invention now.
Main frame writes corresponding write command and address parameter in the flash memory device, and this flash memory device begins executive routine quickflashing algorithm subsequently.
See also shown in Figure 6ly, for foundation concrete form of the present invention shows the write-in program flow process of flash memory device, at first, in step 601, the logical address that main frame is sent converts flash memory physical blocks and page address to.
Then in step 602, controller can be checked and see whether sub-block exists, if the non-existent words of sub-block, then skip to step 605, if sub-block exists, in step 603, can check the logical blocks of existing flash memory, see the memory logic block that last writes that whether equals that writes, if unequal, then skip to step 611.
If equate, in step 604, can check the existing flash memory logical page number, see write whether greater than last flash memory logical page or leaf that writes, if, then continue step 610, if not, then skip to step 611.
Step 605 is got a clean block from the FIF0 formation be that a sub-block is set up in existing write command.
Check the existing flash memory logical page number in step 606, see whether equal " 0 " that writes,, continue step 608 if equal " 0 ".
If be not equal to " 0 ", in step 607, the data of female block can be moved to the sub-block between " last page that writes " and " the existing page or leaf that writes ".
In step 608, the data of main frame to flash memory are write in the buffer zone, and the counting of block of cells can reduce.
In step 609, if the counting of block of cells equals " 0 ", then advance to " terminal point ", if not, then continue step 608.
In step 610, if the existing page number that writes equals to write the page number at last and adds 1, then continue step 608, if not, then continue step 607.
In step 611, the data of female block can be moved to the sub-block between " last page that writes " and " last page of this block ", and wipe female block, and logic in the update controller and physical address mapping table, replace female block address with the sub-block address, female block that will be wiped free of simultaneously is returned in the FIF0 formation as clean block.
See also shown in Figure 7ly, for foundation concrete form of the present invention shows the fetch program flow process of flash memory device, this is the fetch program flow process that shows flash memory device according to concrete form of the present invention.
In step 701, for the logical address with the main frame of tool USB converts flash memory entity and page address to.
In step 702, check existing flash memory, see the flash memory logical block that last reads that whether equals to be read, if, then skip to step 705, if not, continue step 703.
In step 703, read the flash memory physical blocks and the page or leaf data and the counting of block of cells can reduce.
In step 704, check the block of cells counting, see whether it equals " 0 ",, then advance to " terminal point ", if not, then get back to step 703 if equal " 0 ".
In step 705, check the existing memory logical page (LPAGE), see to be read whether greater than the flash memory logical page or leaf that writes at last, if, get back to step 703, if not, advance to step 706.
In step 706, read the data of sub-block physical blocks and page or leaf, and the counting of block of cells can reduce.
In step 707, check the block of cells counting, see whether it equals " 0 ",, then advance to " terminal point ", if not, then get back to step 705 if equal " 0 ".
See also shown in Figure 15, be the order package configuration diagram that foundation concrete form of the present invention shows, when microprocessor began fill order, the USB flash memory device can be downloaded its parameter from main frame, for example read or write, shown manufacturer's order package among the figure.
Address pattern can be judged by installing/open beginning bit group by system, and flash memory device while support logic block address (LBA) of the present invention and right cylinder open beginning block of cells (CHS) pattern.
If host computer using LBA pattern provides the address, flash memory device can convert it to the CHS pattern, makes the CHS pattern into physical address then.
When flash memory device is carried out reading order, controller at first can the buffer zone that reads controller (512 bit group) with the block of cells of a block of cells of data of flash memory in, the USB engine can be delivered to main frame with block of cells then, when the block of cells quantity of delivering to main frame equaled block of cells number that main frame desires to read, whole order had just been finished.
When flash memory device is carried out write command, controller can be by the buffer zone that read controller (512 bit group) of USB engine with a block of cells of a block of cells of data of main frame, this block of cells will be stored in the flash memory then, when the block of cells quantity of delivering to flash memory equaled block of cells number that main frame desires to write, whole order had just been finished.
Flash memory device can be supported more than one flash memory, provide a plurality of wafers to choose pin among the present invention, when starting flash memory device, what wafers employed flash memory type (capacity) and system have on its meeting inspection plate, flash memory device can be added up all memory chips, find out total volume, when main frame needs the data of this class, flash memory device will provide total volume to main frame, rather than the capacity of single wafer.
When main frame sends a certain address (logic) to flash memory device, flash memory device can be carried out calculating, find out access that main frame wants pellet really, and corresponding address, then, flash memory device can use the address of calculating, and the startup wafer is chosen pin.
In addition, described in the present invention and flash memory, controller be single-chip design, in order to dwindling the overall volume of flash memory device, and do not need the design of external random access storer (RAM) or ROM (read-only memory) (ROM).
The above embodiment only is explanation technological thought of the present invention and characteristics, its purpose makes the personage who has the knack of this skill can understand content of the present invention and is implementing according to this, when not limiting claim of the present invention with it, promptly the equalization of doing according to disclosed spirit generally changes or modifies, and must be encompassed in the claim scope of the present invention.
Claims (11)
1, a kind of universal serial bus structural flash memory device, it includes at least:
A universal serial bus structural connector is connected to this flash memory device in the main frame of tool universal serial bus structural connector;
The flash memory module or the array of at least one storage data; And
One in order to order between main control system and the flash memory device and data and manage the controller of the data at least one flash memory module; It is characterized in that:
Described flash memory device has further comprised an accessory circuit plate that extends the memory size of this flash memory device, and described accessory circuit plate comprises a flash memory module at least.
2, universal serial bus structural flash memory device as claimed in claim 1 is characterized in that: the indicator that further comprises the state of this flash memory device of indication in this flash memory device.
3, universal serial bus structural flash memory device as claimed in claim 1 is characterized in that: further comprise one in this flash memory device and prevent to write this flash memory device or with the write protection switch of data erase.
4, universal serial bus structural flash memory device as claimed in claim 1 is characterized in that: comprised a system buffer in this flash memory device further, the buffering between main frame and the flash memory device is provided.
5, universal serial bus structural flash memory device as claimed in claim 1 is characterized in that: comprised a state machine that reads and write sequential for system buffer foundation in this flash memory device further.
6, universal serial bus structural flash memory device as claimed in claim 1, it is characterized in that: comprised I/O control interface in this flash memory device further, the I/O control that provides this flash memory device need carry out other.
7, universal serial bus structural flash memory device as claimed in claim 1, it is characterized in that: comprised an error correction labeling scheme in this flash memory device further, when data write this flash memory device, encode this error correction code and this error correction code of when reading the data of this flash memory device, decoding.
8, universal serial bus structural flash memory device as claimed in claim 7 is characterized in that: this ECC circuit has comprised further when taking place and righting the wrong, the judgement of invalid data address.
9, universal serial bus structural flash memory device as claimed in claim 1, it is characterized in that: comprised a flash memory interface in this flash memory device further, reading and write command of at least one flash memory module delivered in control.
10, universal serial bus structural flash memory device as claimed in claim 1 is characterized in that: further comprised one in this flash memory device and carried out the microprocessor that main frame has the order of parameter.
11, universal serial bus structural flash memory device as claimed in claim 1 is characterized in that: this controller is one not need the single-chip of external random access storer or ROM (read-only memory).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02108242 CN1253795C (en) | 2002-03-28 | 2002-03-28 | Universal serial bus structural flash memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02108242 CN1253795C (en) | 2002-03-28 | 2002-03-28 | Universal serial bus structural flash memory device |
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| CN1448847A CN1448847A (en) | 2003-10-15 |
| CN1253795C true CN1253795C (en) | 2006-04-26 |
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| CN 02108242 Expired - Lifetime CN1253795C (en) | 2002-03-28 | 2002-03-28 | Universal serial bus structural flash memory device |
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| CN (1) | CN1253795C (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101178933B (en) * | 2007-12-05 | 2010-07-28 | 苏州壹世通科技有限公司 | Flash memory array device |
| CN102193747B (en) * | 2010-03-03 | 2015-06-10 | 群联电子股份有限公司 | Data writing-in method, rewritable non-volatile memory controller and system |
| TWI492051B (en) * | 2012-09-05 | 2015-07-11 | Silicon Motion Inc | Data storage device and control method for flash memory |
| US10496289B2 (en) * | 2016-06-16 | 2019-12-03 | Nuvoton Technology Corporation | System and methods for increasing useful lifetime of a flash memory device |
| CN109582599B (en) * | 2017-09-29 | 2023-12-22 | 上海宝存信息科技有限公司 | Data storage device and non-volatile memory operation method |
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