CN102023811B - Method for transmitting programming command to flash memory, controller and storage system - Google Patents
Method for transmitting programming command to flash memory, controller and storage system Download PDFInfo
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- CN102023811B CN102023811B CN2009101721618A CN200910172161A CN102023811B CN 102023811 B CN102023811 B CN 102023811B CN 2009101721618 A CN2009101721618 A CN 2009101721618A CN 200910172161 A CN200910172161 A CN 200910172161A CN 102023811 B CN102023811 B CN 102023811B
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Abstract
The embodiment of the invention provides a method for transmitting a programming command to a flash memory, a controller and a storage system. The method is used for writing data from a host system into a flash memory chip. The method comprises the following steps of: receiving a plurality of host write commands from the host system and write data corresponding to the host write commands by using a native command queuing (NCQ) protocol; and transmitting a caching programming command to the flash memory chip to write the write data into the flash memory chip. Thus, the data is written by only using the caching programming command and the native command queuing protocol, so that the time for executing the host write command can be effectively shortened.
Description
Technical field
The present invention relates to a kind of flash controller and flash memory system of flash memory being assigned method and use the method for programmed instructions.
Background technology
Because flash memory (Flash Memory) has that data are non-volatile, power saving, volume is little and the characteristic of no mechanical structure etc., the most suitable being used on the portable electronic product.For example, solid state hard disc is exactly a kind of with the storage device of nand flash memory as Storage Media, and extensively is disposed in the mobile computer as main storage device.
Fig. 1 is the summary calcspar of the general flash memory of diagram.In general; When host computer system 110 saw through connector 122 with flash memory electric connection and desire storage data to flash memory 120, the program that writes the flash memory module 126 of data to flash memory 120 can be divided into data transmission (transfer) and two parts of data programization (program).Specifically; When host computer system 110 is desired in flash memory 120 storage data; Flash controller 124 can be through data input/output bus 128 with the buffer zone 132 in data transmission to the flash memory module 126; Flash memory module 126 can be with the storer (that is, the storage area) 134 of data programization to the flash memory module 126 in the buffer zone 132, wherein during flash memory module 126 is with data programization to storer 134 afterwards; Flash memory module 126 is to be in actual busy (busy) state, and can't assign any instruction or transmit any data it when flash memory module 126 is under the actual busy condition flash controller 124.That is to say that flash controller 124 must could respond the next instruction of host computer system 110 and processing host system 110 after flash memory module 126 is accomplished sequencing.
Specifically; When flash controller 124 receives main frame when writing instruction and needing to write data with writing data and write to flash memory module 126 from host computer system 110; Flash controller 124 can be assigned programmed instructions through data input/output bus 128, and the relevant information in this programmed instructions will be temporary in the buffer zone 132.For example; This programmed instructions is made up of with character strings such as " instruction W2 " " instruction W1 ", " physical address ", " writing data "; Wherein flash controller 124 is prepared the executive routine program through " instruction W1 " indication flash memory module 126; Through the address that " physical address " indication flash memory module 126 is desired sequencing, desire the data of sequencing and pass through " instruction W2 " indication flash memory module 126 beginning executive routineizations through " writing data " indication flash memory module 126.Therefore; When flash memory module 126 begins that according to " instruction W2 " in the programmed instructions data in the buffer zone 132 are write to storer 134; Flash controller 124 just can be replied host computer system 110 after need receiving affirmation (acknowl edgement) information of the completion sequencing that comes from flash memory module 126; In general, assign the time of instructing host computer system to receive confirmation when host computer system and be called the response time (response time).
Along with the development of transmission technology, make the transmission speed of connector significantly promote, for example; Advanced annex (the Serial Advanced Technology Attachment of sequence; SATA) connector can reach 1,500,000,000 of per seconds (Gigabit, Gb), even per second 30Gb.Yet the speed of said procedure flash memory but under the speed of far low connector, still can't effectively improve by the whole usefulness that stores, and how to shorten therefore that to carry out the time that main frame writes instruction be the target that these those skilled in the art endeavour.
Summary of the invention
The present invention provides a kind of method of assigning programmed instructions, and it can shorten effectively carries out the time that main frame writes instruction.
The present invention provides a kind of flash controller, and it can shorten effectively carries out the time that main frame writes instruction.
The present invention provides a kind of flash memory system, can shorten effectively and carry out the time that main frame writes instruction.
Exemplary embodiment of the present invention proposes a kind of method of assigning programmed instructions, is used for the data that come from a host computer system are write to a flash chip.Originally the method for assigning programmed instructions comprises provides a flash controller, and (Native Command Queuing, NCQ) agreement receives a plurality of main frames and writes instruction from host computer system to use a primary instruction ordering by flash controller.Originally the method for assigning programmed instructions comprises that also writing instruction transmission one by flash controller according to main frame assigns instruction sequences to host computer system.Originally the method for assigning programmed instructions also comprises according to assigning instruction sequences and from host computer system, receives main frame in order and write instruction and write a plurality of data that write of instruction with respective hosts, and assigns a fast program fetch instruction to flash chip respectively and write in the flash chip will write data.
Exemplary embodiment of the present invention proposes a kind of flash controller, is used for the data that come from a host computer system are write to a flash chip.This flash controller comprises a microprocessor unit, a memory buffer, a flash interface unit, a host interface unit and a memory management unit.The flash interface unit is electrically connected to microprocessor unit, and in order to connect flash chip.Memory buffer is electrically connected to microprocessor unit.Host interface unit is electrically connected to microprocessor unit, and in order to connect above-mentioned host computer system, wherein host interface unit is supported the NCQ agreement.Memory management unit is electrically connected to microprocessing unit, and writes instruction in order to use the NCQ agreement from host computer system, to receive a plurality of main frames through host interface unit.In addition, memory management unit writes instruction transmission one through host interface unit according to main frame and assigns instruction sequences to host computer system.Moreover; Memory management unit sees through host interface unit and from host computer system, receives main frame in order and write instruction and write a plurality of data that write of instruction with respective hosts according to assigning instruction sequences, and assigns fast program fetch instruction to flash chip respectively and write in the flash chip will write data.
Exemplary embodiment of the present invention proposes a kind of flash memory system, is used to store the data that come from a host computer system.This flash memory system comprises that in order to a connector that electrically connects above-mentioned host computer system, a flash chip and a flash controller wherein connector is supported the NCQ agreement.Flash controller is electrically connected to connector and flash chip, and writes instruction in order to use the NCQ agreement from host computer system, to receive a plurality of main frames through connector.In addition, flash controller writes instruction transmission one according to main frame and assigns instruction sequences to host computer system.Moreover; Flash controller sees through connector and from host computer system, receives main frame in order and write instruction and write a plurality of data that write of instruction with respective hosts according to the above-mentioned instruction sequences of assigning, and assigns a fast program fetch instruction to flash chip respectively and write in the flash chip will write data.
Based on above-mentioned, the method for assigning programmed instructions, flash controller and the flash memory system of exemplary embodiment of the present invention can shorten effectively to be carried out the time that main frame writes instruction, promotes the usefulness of data access thus.
Below through specific embodiment and combine accompanying drawing that the present invention is done further detailed description.
Description of drawings
Fig. 1 is the summary calcspar of the general flash memory system of diagram;
Fig. 2 A is a host computer system of using flash memory according to embodiment of the invention diagram;
Fig. 2 B is the synoptic diagram of the illustrated computing machine of exemplary embodiment, input/output device and flash memory according to the present invention;
Fig. 2 C is the synoptic diagram of the illustrated host computer system of another exemplary embodiment and flash memory according to the present invention;
Fig. 2 D is the summary calcspar of the illustrated flash memory of exemplary embodiment according to the present invention;
Fig. 3 is the summary calcspar of the illustrated flash memory crystal grain of exemplary embodiment according to the present invention;
Fig. 4 A is that the illustrated flash controller of exemplary embodiment sees through the example schematic that the data input/output bus is assigned fast program fetch instruction according to the present invention;
Fig. 4 B is the time sequences figure according to the flash chip that instruction illustrates shown in Fig. 4 A;
Fig. 5 is the illustrated process flow diagram of assigning programmed instructions of exemplary embodiment according to the present invention.
Description of reference numerals:
110: host computer system; 120: flash memory;
122: connector; 124: flash controller;
126: flash memory module; 128: the data input/output bus;
132: buffer zone; 134: storer;
200: flash memory; 202: connector;
204: flash controller; 206: microprocessor unit;
208: memory management unit; 210: host interface unit;
212: the flash interface unit; 214: memory buffer;
220: flash chip; 290: host computer system;
295: bus; 300: the 0 flash memory modules;
302: the 0 data input/output bus; 310: the 1 flash memory modules;
312: the 1 data input/output bus; 320: the 2 flash memory modules;
322: the 2 data input/output bus; 330: the 3 flash memory modules;
332: the 3 data input/output bus; 340: the 4 flash memory modules;
342: the 4 data input/output bus; 350: the 5 flash memory modules;
352: the 5 data input/output bus; 360: the 6 flash memory modules;
362: the 6 data input/output bus; 370: the 7 flash memory modules;
372: the 7 data input/output bus; 400: the 0 flash memory crystal grain;
402: the storage area; 404: the first buffer zones;
406: the second buffer zones; 410: the 1 flash memory crystal grain;
420: the 2 flash memory crystal grain; 430: the 3 flash memory crystal grain;
440: the 4 flash memory crystal grain; 450: the 5 flash memory crystal grain;
460: the 6 flash memory crystal grain; 470: the 7 flash memory crystal grain;
480: the 8 flash memory crystal grain; 490: the 9 flash memory crystal grain;
500: the 10 flash memory crystal grain; 510: the 11 flash memory crystal grain;
520: the 12 flash memory crystal grain; 530: the 13 flash memory crystal grain;
540: the 14 flash memory crystal grain; 550: the 15 flash memory crystal grain;
1100: computing machine; 1102: microprocessor;
1104: random access memory; 1106: input/output device;
1108: system bus; 1110: data transmission interface;
1202: mouse; 1204: keyboard;
1206: display; 1208: printer;
1212: carry-on dish; 1214: memory card;
1216: solid state hard disc; 1310: digital still camera;
The 1310a:SD card; The 1310b:MMC card;
The 1310c:CF card; 1310d: memory stick;
1310e: embedded storage device; W1, W2, W3: instruction;
D1, D2, D3: data; ADD1, ADD2, ADD3: physical address;
CM1, CM2, CM3, CM4, CM5, CM6, CM7, CM8, CM9: instruction;
T1, T2, T3: data transmission; B1, B2, B3: busy time;
S501, S503, S505, S507, S509, S511, S513, S515, S517: the step of assigning programmed instructions.
Embodiment
Generally speaking flash memory comprises flash chip and controller (also claiming control circuit).Usually flash memory can use with host computer system, so that host computer system can write to flash memory or reading of data from flash memory with data.In addition, flash memory also being arranged is to comprise embedded flash memory and can be executed on the host computer system with substantially as the software of this embedded flash controller.
Fig. 2 A is a host computer system of using flash memory according to embodiment of the invention diagram.
Please with reference to Fig. 2 A, host computer system 290 generally comprises computing machine 1100 and I/O (input/output, I/O) device 1106.Computing machine 1100 comprise microprocessor 1102, random access memory (random access memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises mouse 1202, keyboard 1204, the display 1206 and printer 1208 like Fig. 2 B.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Fig. 2 B, input/output device 1106 can also comprise other device.
Generally speaking, but host computer system 290 can be any system of storage data substantially.Though in this exemplary embodiment, host computer system 290 is to explain with computer system, yet host computer system 290 can be systems such as digital camera, video camera, communicator, message player or video signal player in another exemplary embodiment of the present invention.For example; In host computer system is digital camera (video camera) 1310 o'clock, and flash memory then is its employed SD card 1310a, mmc card 1310b, CF card 1310c, memory stick (memory stick) 1310d or embedded storage device 1310e (shown in Fig. 2 C).Embedded storage device 1310e comprise the built-in multimedia card (Embedded MMC, eMMC).What deserves to be mentioned is that the built-in multimedia card is directly to be electrically connected on the substrate of host computer system.
Fig. 2 D is the detailed block diagram of flash memory 200 shown in the pictorial image 2A.
Please with reference to Fig. 2 D, flash memory 200 comprises connector 202, flash controller 204 and flash chip 220.
Connector 202 is to be electrically connected to flash controller 204 and to connect host computer systems 290 in order to pass through bus 295.In this exemplary embodiment, connector 202 is advanced annex (Serial AdvancedTechnology Attachment, a SATA) connector of sequence.Particularly, the primary instruction ordering of connector 202 supports (Native Command Queuing, NCQ) agreement, and be to transmit with the NCQ agreement to write instruction between host computer system 290 and the flash controller 204.Specifically; When transmitting main frame and write instruction with the NCQ agreement between host computer system 290 and the flash controller 204; A plurality of main frames that host computer system 290 can be sent desire earlier write instruction and send flash controller 204 together to, and flash controller 204 assigns instruction sequences to host computer system 290 its expections of response, particularly; Host computer system 290 only transmits the instruction of desiring to assign and gives flash controller 204 in this process, and can not transmit the data of desiring to write.Afterwards, host computer system 290 transmits main frame according to the response of flash controller 204 and writes instruction and data, and flash controller 204 responds host computer system 290 again each writes the executing state of instruction in accomplishing after All hosts writes instruction.Particularly, when sequencing mistake (program fail) took place, host computer system 290 can retransfer instruction and the data that the sequencing mistake takes place correspondence to flash controller 204 according to the reported information (that is executing state) of flash controller 204.Perhaps, in another exemplary embodiment of the present invention, when sequencing mistake (program fail) took place, host computer system 290 can retransfer all instructions to flash controller 204 with data.
In addition, it must be appreciated that in exemplary embodiment of the present invention, connector 202 so the invention is not restricted to this for supporting the SATA connector of NCQ, connector 202 also can be other connector of supporting the NCQ agreement.
Flash controller 204 can be carried out with hardware pattern or real a plurality of logic locks or the steering order of doing of firmware pattern, and in flash chip 220, carries out the runnings such as writing, read and erase of data according to the instruction of host computer system 290.Flash controller 204 comprises microprocessor unit 206, memory management unit 208, host interface unit 210, flash interface unit 212 and memory buffer 214.
Microprocessor unit 206 is the main control unit of flash controller 204, in order to cooperative cooperatings such as memory management unit 208, host interface unit 210, flash interface unit 212 and memory buffer 214 to carry out the various runnings of flash memory 200.
Memory management unit 208 is to be electrically connected to microprocessor unit 206, in order to carry out according to this exemplary embodiment to assign programmed instructions machine-processed with block management, the running of memory management unit 208 will elaborate in following cooperation is graphic.
In this exemplary embodiment, memory management unit 208 is to be embodied in the flash controller 204 with a firmware pattern.For example; The memory management unit 208 that will comprise a plurality of steering orders (for example is burned onto a program internal memory; ROM (read-only memory) (Read Only Memory; ROM)) be embedded in the flash controller 204 in and with this program internal memory, when flash memory 200 running, a plurality of steering orders of memory management unit 208 can by microprocessor unit 206 carry out with accomplish according to the embodiment of the invention to assign programmed instructions machine-processed with block management.
In another exemplary embodiment of the present invention, the steering order of memory management unit 208 also can the program code pattern be stored in the specific region (for example, being exclusively used in the system region of storage system data in the flash chip) of flash chip 220.Same, when flash memory 200 runnings, a plurality of steering orders of memory management unit 208 can be carried out by microprocessor unit 206.In addition, in another exemplary embodiment of the present invention, memory management unit 208 also can a hardware pattern be embodied in the flash controller 204.
Host interface unit 210 is instruction and the data that are electrically connected to microprocessor unit 206 and transmitted in order to reception and identification host computer system 290.That is to say that instruction that host computer system 290 is transmitted and data can be sent to microprocessor unit 206 through host interface unit 210.In this exemplary embodiment, host interface unit 210 is that corresponding connector 202 is the SATA interface.Yet, it must be appreciated to the invention is not restricted to this that host interface unit 210 also can be other data transmission interface that is fit to.
Flash interface unit 212 is to be electrically connected to microprocessor unit 206 and in order to access flash chip 220.That is to say that the data of desiring to write to flash chip 220 can convert 220 receptible forms of flash chip into through flash interface unit 212.
Memory buffer 214 is to be electrically connected to microprocessor unit 206 and in order to the temporary data that come from the data and instruction of host computer system 290 or come from flash chip 220.
In addition, though not shown in this exemplary embodiment, flash controller 204 yet comprises general utility functions modules such as error correction unit and PMU.
Flash chip 220 is to be electrically connected to flash controller 204 and in order to storage data.Flash chip 220 comprises the 0th flash memory module the 300, the 1st flash memory module the 310, the 2nd flash memory module the 320, the 3rd flash memory module the 330, the 4th flash memory module the 340, the 5th flash memory module the 350, the 6th flash memory module 360 and the 7th flash memory module 370.In this exemplary embodiment; The 0th flash memory module the 300, the 1st flash memory module the 310, the 2nd flash memory module the 320, the 3rd flash memory module the 330, the 4th flash memory module the 340, the 5th flash memory module the 350, the 6th flash memory module 360 and the 7th flash memory module 370 are multilayer storer (Multi LevelCell, MLC) nand flash memory module.Yet; The invention is not restricted to this; The 0th flash memory module the 300, the 1st flash memory module the 310, the 2nd flash memory module the 320, the 3rd flash memory module the 330, the 4th flash memory module the 340, the 5th flash memory module the 350, the 6th flash memory module 360 and the 7th flash memory module 370 be single layer of memory (Single Level Cell, SLC) nand flash memory module also.
In this exemplary embodiment, the 0th flash memory module the 300, the 1st flash memory module the 310, the 2nd flash memory module the 320, the 3rd flash memory module the 330, the 4th flash memory module the 340, the 5th flash memory module the 350, the 6th flash memory module 360 and the 7th flash memory module 370 are to be electrically connected to flash controller 204 respectively.Specifically, the flash interface unit 212 of flash controller 204 transmits data through the 0th data input/output bus (Data input/output bus) the 302, the 1st data input/output bus the 312, the 2nd data input/output bus the 322, the 3rd data input/output bus the 332, the 4th data input/output bus the 342, the 5th data input/output bus the 352, the 6th data input/output bus 362 and the 7th data input/output bus 372 respectively and gives the 0th flash memory module the 300, the 1st flash memory module the 310, the 2nd flash memory module the 320, the 3rd flash memory module the 330, the 4th flash memory module the 340, the 5th flash memory module the 350, the 6th flash memory module 360 and the 7th flash memory module 370.
In this exemplary embodiment; The 0th flash memory module 300 comprises the 0th flash memory crystal grain (die) 400 and the 1st flash memory crystal grain 410; The 1st flash memory module 310 comprises the 2nd flash memory crystal grain 420 and the 3rd flash memory crystal grain 430; The 2nd flash memory module 320 comprises the 4th flash memory crystal grain 440 and the 5th flash memory crystal grain 450; The 3rd flash memory module 330 comprises the 6th flash memory crystal grain 460 and the 7th flash memory crystal grain 470; The 4th flash memory module 340 comprises that the 8th flash memory crystal grain 480 and the 9th flash memory crystal grain 490, the 5 flash memory modules 350 comprise that the 10th flash memory crystal grain 500 and the 11st flash memory crystal grain 510, the 6 flash memory modules 360 comprise that the 12nd flash memory crystal grain 520 and the 13rd flash memory crystal grain 530 and the 7th flash memory module 370 comprise the 14th flash memory crystal grain 540 and the 15th flash memory crystal grain 550.
What deserves to be mentioned is; In exemplary embodiment of the present invention; Dispose the 0th data input/output bus the 302, the 1st data input/output bus the 312, the 2nd data input/output bus the 322, the 3rd data input/output bus the 332, the 4th data input/output bus the 342, the 5th data input/output bus the 352, the 6th data input/output bus 362 and the 7th data input/output bus 372 between the 0th flash memory module the 300, the 1st flash memory module the 310, the 2nd flash memory module the 320, the 3rd flash memory module the 330, the 4th flash memory module the 340, the 5th flash memory module the 350, the 6th flash memory module 360 and the 7th flash memory module 370 and the flash controller 204 respectively; Therefore memory management unit 208 can use parallel model (parallelmode) to transmit through many data input/output bus simultaneously and write data to corresponding flash memory module, to promote access speed.In addition, each flash memory module comprises two flash memory crystal grain, so memory management unit 208 can use interleaving modes (interleave mode) be sent to two interior flash memory crystal grain of same flash memory module with will writing data interlace, more to increase access usefulness.More detailed; As stated; The process that in flash memory crystal grain, writes data comprises data transmission (transfer) and two parts of data programization (program); And interleaving mode (interleave mode) is exactly in the example of two flash memory crystal grain that use same data input/output bus transmission data, utilize one of them flash memory crystal grain just carrying out the data sequencing during transmit data and give another flash memory crystal grain.
Fig. 3 is the summary calcspar of the illustrated flash memory crystal grain of exemplary embodiment according to the present invention.At this; The 0th flash memory crystal grain the 400, the 1st flash memory crystal grain the 410, the 2nd flash memory crystal grain the 420, the 3rd flash memory crystal grain the 430, the 4th flash memory crystal grain the 440, the 5th flash memory crystal grain the 450, the 6th flash memory crystal grain the 460, the 7th flash memory crystal grain the 470, the 8th flash memory crystal grain the 480, the 9th flash memory crystal grain the 490, the 10th flash memory crystal grain the 500, the 11st flash memory crystal grain the 510, the 12nd flash memory crystal grain the 520, the 13rd flash memory crystal grain the 530, the 14th flash memory crystal grain 540 is all identical with the structure and the function mode of the 15th flash memory crystal grain 550, below only describes with the 0th flash memory crystal grain 400.
Please with reference to Fig. 3, the 0th flash memory crystal grain 400 comprises storage area 402, first buffer zone 404 and second buffer zone 406.
What deserves to be mentioned is that the physical blocks in the 0th flash memory crystal grain the 400, the 1st flash memory crystal grain the 410, the 2nd flash memory crystal grain the 420, the 3rd flash memory crystal grain the 430, the 4th flash memory crystal grain the 440, the 5th flash memory crystal grain the 450, the 6th flash memory crystal grain the 460, the 7th flash memory crystal grain the 470, the 8th flash memory crystal grain the 480, the 9th flash memory crystal grain the 490, the 10th flash memory crystal grain the 500, the 11st flash memory crystal grain the 510, the 12nd flash memory crystal grain the 520, the 13rd flash memory crystal grain the 530, the 14th flash memory crystal grain 540 and the 15th flash memory crystal grain 550 can be that a plurality of solid elements carry out writing, read and erasing of data by memory management unit 208 groups.Particularly each solid element is made up of the physical blocks in a plurality of flash memory crystal grain, so memory management unit 208 can use above-mentioned parallel model and interleaving mode to promote the speed of access.
Moreover, because the storer of flash memory only can turn to " 0 " from " 1 " program, the data in the physical blocks of must erasing earlier in the time of therefore will upgrading the data in the physical blocks.Yet writing of flash memory is to be unit with the page, is to be unit with the physical blocks and erase, so the physical blocks in the storage area 402 can be come storage data with the mode of rotating.Specifically; Memory management unit 208 can logically be grouped into the solid element that divides into groups system region (system area), data field (data area), spare area (spare area) and replace district (replacement area); The solid element that wherein is grouped into system region is in order to store the relevant important information of flash memory; And be grouped into the solid element that replaces the district is the solid element that has damaged in data field or the spare area in order to replace; Therefore under general access status, host computer system 290 is can't access system district and the solid element that replaces in the district.Write the data that instruction writes as for storing in the solid element that is grouped into the data field by main frame, and the solid element in the spare area is in order to the solid element in the replacement data district when the execution main frame writes instruction.For example; The main frame that receives host computer system 290 when flash memory 200 writes instruction and desire when upgrading a certain page of (or writing) data a certain solid element to the data field; Memory management unit 208 can extract a solid element and effective legacy data in the solid element of desiring to be updated and the new data of desiring to write are write in the solid element that from the spare area, extracts from the spare area; And the solid element that will write effective legacy data and new data logically is associated as the data field, and the solid element of desiring in the data field to be updated is erased and logically is associated as the spare area.In order to let host computer system 290 access successfully with the solid element of the mode storage data of rotating, flash memory 200 can provide logical address to host computer system 290.That is to say; Flash memory 200 can through record in logical address-physical address bitmap (logical address-physicaladdress mapping table) and more the enantiomorphic relationship between the solid element of new logical addresses and data field reflect rotating of solid element, flash memory 200 is understood according to logical address-physical address bitmap the physical address of the solid element of institute's mapping is read or write data so host computer system 290 only need be directed against that the logical address that provides writes.
Specifically; When memory management unit 208 receives main frame when writing instruction and needing to write data with writing data and write to the 0th flash memory crystal grain 400 from host computer system 290; Memory management unit 208 can be assigned programmed instructions through flash interface unit 212 and data input/output bus 302; And the data of desiring to write in this programmed instructions are transferred to first buffer zone 404 from buffering storer 214; The data of desiring afterwards to write can be moved to second buffer zone 406 from first buffer zone 404, and last, data can be programmed into storage area 402 from second buffer zone 406.Particularly; In this exemplary embodiment; Memory management unit 208 only can use by " instruction W1 ", " physical address ", " writing data " and come the sequencing data with programmed instructions that character string is formed such as " instruction W3 "; Wherein memory management unit 208 is prepared the executive routine program through " instruction W1 " indication the 0th flash memory crystal grain 400; Through the physical address of " physical address " indication the 0th flash memory crystal grain 400 desire sequencing, desire the data of sequencing and begin to carry out fast program fetchization (cache program) through " instruction W3 " indication the 0th flash memory crystal grain 400 through " writing data " indication the 0th flash memory crystal grain 400.At this, when " instruction W3 " in the service routine instruction, flash controller 204 can just receive the affirmation information of the 0th flash memory crystal grain 400 when data have been moved second buffer zone 406 from first buffer zone 404, and can handle next instruction.
For example; Using the NCQ agreements from host computer system 290, to receive two continuous main frames at flash controller 204 writes instruction and needs in the example of two page executive routineizations of the 0th flash memory crystal grain 400; Because the 0th flash memory crystal grain 400 has two buffer zones (promptly; First buffer zone 404 and second buffer zone 406); Therefore the data that first main frame write instruction when the 0th flash memory crystal grain 400 are moved to second buffer zone 406 from first buffer zone 404, and first buffer zone 404 just can be eliminated and receive the data that second main frame writes instruction.Particularly; Write data from second buffer zone 406 during sequencing to the storage area 402 what the 0th flash memory crystal grain 400 was just writing first main frame instruction; What first buffer zone 404 can be responsible for receiving next programmed instructions writes data (that is, second main frame writes the data of instruction).That is to say; Through using " instruction W3 " can make memory management unit 208 need not to wait for that the 0th flash memory crystal grain 400 accomplishes under the situation of sequencing that first main frames write instruction; Just can continue to handle second main frame and write instruction, and second main frame write writing in data transmission to the first buffer zone 404 of instruction.Therefore, the 0th flash memory crystal grain 400 can side by side be carried out first main frame and write the data programization that data of instruction and the data transmission that writes data of second host command, carries out the time that main frame writes instruction and shorten.
Fig. 4 A is that the illustrated flash controller of exemplary embodiment sees through the example schematic that the data input/output bus is assigned fast program fetch instruction according to the present invention, and Fig. 4 B is the time sequences figure according to the flash chip that instruction illustrates shown in Fig. 4 A.In the example of Fig. 4 A and Fig. 4 B, memory management unit 208 is to use the NCQ agreement from host computer system 290, to receive 3 main frames and writes instruction.At this; It is 3 continuous logical addresses that these 3 main frames write the instruction logical address desiring to write; And memory management unit 208 can produce according to the order of these a little logical addresses and assign instruction sequences; So that host computer system 290 is assigned these 3 main frames and is write instruction according to the instruction sequences of assigning that memory management unit 208 is produced; Wherein the 1st main frame writes to instruct and comprises logical address of desiring to write and the data D1 that desires to write; The 2nd main frame writes instruction and comprises logical address of desiring to write and the data D2 that desires to write, and the 3rd main frame writes instruction and comprise logical address of desiring to write and the data D3 that desires to write, and these 3 main frames to write that instruction desires in the logical address that writes be the physical blocks of mapping to the 0 flash memory crystal grain 400.
Please with reference to Fig. 4 A and Fig. 4 B; Assigning instruction sequences according to this when the memory management unit 208 of flash controller 204 receives after the 1st main frame that comes from host computer system 290 write instruction and the data desiring to write; Memory management unit 208 can write among the data D1 that the logical address in the instruction desires with it to write to flash chip 220 according to the 1st main frame and assign the fast program fetch instruction be made up of " instruction W1 ", " ADD1 ", " data D1 " and character strings such as " instruction W3 " (the instruction CM1 shown in Fig. 4 A, instruction CM2, transmit T1 and instruction CM3), the wherein physical address of " ADD1 " representation program data.Also be just to say; Memory management unit 208 can send the physical address that main frame writes the logical address institute mapping in the instruction to the 0th flash memory crystal grain 400 (promptly according to logical address-physical address bitmap; Instruction CM2), and with data D1 transfer to first buffer zone 404 (that is transmission T1).Afterwards; The 0th flash memory crystal grain 400 can be according to fast program fetch instruction (promptly; Instruction CM3) data D1 is moved to second buffer zone 406 from first buffer zone 404; And in completion data D1 is moved to second buffer zone 406 from first buffer zone 404, data D1 sequencing to storage area 402 from second buffer zone 406.Particularly; When the 0th flash memory crystal grain 400 begins to execute instruction CM3; The 0th flash memory crystal grain 400 can be in a busy condition, and data D1 is moved from first buffer zone 404 to second buffer zone 406, promptly to reply be (ready) state of awaiting orders (that is, have much to do time B1) accomplishing.When the 0th flash memory crystal grain 400 is replied to armed state; Memory management unit 208 can respond host computer system 290; From host computer system 290, receive the 2nd main frame and write instruction and data D2; And the 0th flash memory crystal grain 400 is assigned the fast program fetch instruction of being made up of " instruction W1 ", " ADD2 ", " data D2 " and character strings such as " instruction W3 " (the instruction CM4 shown in Fig. 4 A, instruction CM5, transmission T2 and instruction CM6) transfer to first buffer zone 404 (that is transmission T2) with the data D2 that the 2nd main frame write instruction.At this moment, the data programization of data D1 is side by side to carry out with the data transmission of data D2.That is to say; Owing to have 2 buffer zones (promptly in the 0th flash memory crystal grain 400; First buffer zone 404 and second buffer zone 406); Therefore see through to get soon to write to instruct the data of desiring to write are moved to second buffer zone 406 from first buffer zone 404, second buffer zone 406 is used for data programization to storage area 402, and first buffer zone 406 just can continue from buffering storer 214, to receive data.
Then; After transmission data D2; After the 0th flash memory crystal grain 400 is accomplished the data programization of data D1; The 0th flash memory crystal grain 400 can be moved data D2 to second buffer zone 406 from first buffer zone 404 according to instruction CM6, and in completion data D2 is moved to second buffer zone 406 from first buffer zone 404, with data D2 sequencing to storage area 402 from second buffer zone 406.When the 0th flash memory crystal grain 400 began to execute instruction CM6, the 0th flash memory crystal grain 400 can be in busy condition, and was armed state (that is, have much to do time B2) accomplishing data D2 moved to second buffer zone 406, promptly to reply from first buffer zone 404.Similarly; When the 0th flash memory crystal grain 400 is replied to armed state; Memory management unit 208 can respond host computer system 290; From host computer system 290, receive the 3rd main frame and write instruction and data D3; And the 0th flash memory crystal grain 400 is assigned the fast program fetch instruction of being made up of " instruction W1 ", " ADD3 ", " data D3 " and character strings such as " instruction W3 " (the instruction CM7 shown in Fig. 4 A, instruction CM8, transmission T3 and instruction CM9) transfer to first buffer zone 404 (that is transmission T3) with the data D3 that the 3rd main frame write instruction.
Then; After transmission data D3; After the 0th flash memory crystal grain 400 is accomplished the data programization of data D2; The 0th flash memory crystal grain 400 can be moved data D3 to second buffer zone 406 from first buffer zone 404 according to instruction CM9, and in completion data D3 is moved to second buffer zone 406 from first buffer zone 404, with data D 3 sequencing to storage area 402 from second buffer zone 406.Similarly, when the 0th flash memory crystal grain 400 began to execute instruction CM9, the 0th flash memory crystal grain 400 can be in busy condition, and was armed state (that is, have much to do time B3) accomplishing data D3 moved to second buffer zone 406, promptly to reply from first buffer zone 404.
What deserves to be mentioned is; In memory management unit 208 receives to reply to the affirmation information of armed state from the 0th flash memory crystal grain 400, can comprise and get mode bit and actual busy condition position soon; Wherein getting mode bit soon is to represent whether the 0th flash memory crystal grain 400 has been ready to receive the next one more and has write data, and actual busy condition position is to represent whether the 0th flash memory crystal grain 400 is in actual busy condition at present.Thus, whether flash controller 204 can judge rightly the 0th flash memory crystal grain 400 just in the sequencing data through the information in the confirmation.In the example of Fig. 4 A and Fig. 4 B; After busy time B3; Though the 0th flash memory crystal grain 400 has been replied and has been ready; It is right because memory management unit 208 writes the action that programmed instructions is assigned in the instruction completion to this All hosts that is received through the NCQ agreement; Therefore memory management unit 208 can continue to confirm that the 0th flash memory crystal grain 400 accomplished the sequencing of all data (that is, memory management unit 208 can confirm that the 0th flash memory crystal grain 400 has been in non-actual busy condition) and afterwards, replied the executing state that each main frame writes instruction to host computer system 290.
Fig. 5 is the illustrated process flow diagram of assigning programmed instructions of exemplary embodiment according to the present invention.
Please with reference to Fig. 5, at first, flash memory 200 receives main frame and writes instruction from host computer system 290 in step S501.Specifically, in this exemplary embodiment, host computer system 290 is to use the NCQ agreement to transmit a plurality of main frames and writes instruction (writing instruction like described 2 main frames of Fig. 4 A).Therefore, flash memory 200 can receive host computer system 290 earlier and estimates that a plurality of main frames of assigning write instruction in step S501.
Then, memory management unit 208 can write the pairing logical address of instruction according to the main frame that is received and assign instruction sequences in step S503.Specifically; In the present embodiment; From host computer system 290, receive a plurality of main frames when writing instruction when memory management unit 208 uses the NCQ agreements, memory management unit 208 can write logical address in the instruction according to main frame and sort and write the order of instruction with the execution main frame of decision expection.What deserves to be mentioned is that in another exemplary embodiment of this example, memory management unit 208 also can not arranged the order that received main frame writes instruction again, produce and assign instruction sequences and assign order that main frame writes instruction originally with host computer system 290.
Memory management unit 208 can send the instruction sequences of assigning that is produced to host computer system in step S505.Afterwards, memory management unit 208 can then ground receive these a little main frames and writes and instruct the data that write that write instruction with corresponding these a little main frames according to assigning one of instruction sequences from host computer system 290 in step S507.
Afterwards, memory management unit 208 can be assigned fast program fetch instruction (for example, with " instruction W1 ", " physical address ", " writing data " and programmed instructions that character string is formed such as " instruction W3 ") to flash chip 220 in step S509.Afterwards, memory management unit 208 can wait and receive the affirmation information of flash chip 220 in step S511, and judges whether that in step S513 accomplishing the All hosts that host computer system 290 is desired to assign in step S501 writes instruction.If judge that in step S513 also not accomplishing the All hosts that host computer system 290 is desired to assign in step S501 writes when instructing, then execution in step S507 continuation receives next main frame and writes instruction.
If judge that in step S513 having accomplished the All hosts that host computer system 290 is desired to assign in step S501 writes when instructing, and judges in step S515 then whether flash chip 220 is in actual busy condition.If judging in step S515 that flash chip 220 is non-is in actual busy condition, execution in step S517 response host computer system 290 and finish the flow process of Fig. 5 then, otherwise, then continue execution in step S511.
Based on above-mentioned; Receiving a plurality of main frames that come from host computer system 290 in use NCQ agreement writes in the example of instruction; Memory management unit 208 can in the All hosts that this batch assigned according to the NCQ agreement write instruction all complete after; Write the executing state (for example, whether the sequencing of generation mistake being arranged) of instruction to host computer system 290 repayment All hosts.Particularly, memory management unit 208 can wait flash chip 220 when the actual busy condition of carrying out last main frame and writing instruction is replied to armed state, just writes the executing state of instruction to host computer system 290 repayment All hosts.
In sum, the programmed instructions method of assigning of exemplary embodiment of the present invention only uses fast program fetch instruction to come the flash chip sequencing, can significantly shorten thus and carry out the time that main frame writes instruction.In addition, the programmed instructions method of assigning of exemplary embodiment of the present invention more utilizes the NCQ agreement to come move instruction between host computer system and flash memory, can avoid host computer system each main frame that can't judge rightly to write the actual executing state of instruction thus.Moreover, in above-mentioned exemplary embodiment, more utilize the NCQ agreement to come to write the logical address that instruction desires to write and come to arrange again to assign the order that main frame writes instruction according to main frame, can more shorten thus and carry out main frame and write and instruct the required time.
What should explain at last is: above embodiment is only in order to explaining technical scheme of the present invention, but not to its restriction; Although with reference to previous embodiment the present invention has been carried out detailed explanation, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these are revised or replacement, do not make the spirit and the scope of the essence disengaging various embodiments of the present invention technical scheme of relevant art scheme.
Claims (12)
1. method of flash memory being assigned programmed instructions; The data that are used for coming from a host computer system write to a flash chip; Wherein said flash chip comprises one first buffer zone, one second buffer zone and a storage area, and the said method of assigning programmed instructions comprises:
One flash controller is provided;
Use a primary instruction ordering agreement from said host computer system, to receive a plurality of main frames by said flash controller and write instruction;
Write instruction transmission one by said flash controller according to said main frame and assign instruction sequences to said host computer system; And
From said host computer system, receive said main frame in order and write instruction and write a plurality of data that write of instruction according to the said instruction sequences of assigning with corresponding said main frame; And assign a fast program fetch instruction so that the said write data are write in the said flash chip to said flash chip respectively
Wherein from said host computer system, receive said main frame in order and write instruction and write the said write data of instruction, and assign said fast program fetch instruction to said flash chip respectively and comprise with the step that the said write data are write in the said flash chip with corresponding said main frame according to the said instruction sequences of assigning:
From said host computer system, receiving said main frame writes one first main frame among the instruction and writes among instruction and the said write data corresponding said first main frame and write one first of instruction and write data;
Assign said fast program fetch instruction by said flash controller to said flash chip and write data transmission to said first buffer zone with said first, wherein said first writes data is moved to said second buffer zone and from said second buffer zone from said first buffer zone and is written into said storage area;
From said host computer system, receiving said main frame writes one second main frame among the instruction and writes among instruction and the said write data corresponding said second main frame and write one second of instruction and write data; And
Assign said fast program fetch instruction to write data transmission to said first buffer zone by said flash controller to said flash chip with said second; Wherein said second writes data is moved to said second buffer zone and from said second buffer zone from said first buffer zone and is written into said storage area
Wherein write data and moved to said second buffer zone from said first buffer zone when said first, said second writes data is transferred in said first buffer zone.
2. according to claim 1 flash memory is assigned the method for programmed instructions, wherein writes instruction according to said main frame and transmit the said instruction sequences of assigning and comprise for the step of said host computer system by said flash controller:
Assign the order that said main frame writes instruction by said flash controller according to said host computer system and decide the said instruction sequences of assigning; And
The said instruction sequences of assigning is transmitted said host computer system.
3. according to claim 1 flash memory is assigned the method for programmed instructions, wherein writes instruction according to said main frame and transmit the said instruction sequences of assigning and comprise for the step of said host computer system by said flash controller:
Decide the said instruction sequences of assigning by said flash controller according to a plurality of logical addresses that the said main frame of correspondence writes instruction; And
The said instruction sequences of assigning is transmitted said host computer system.
4. according to claim 1 flash memory is assigned the method for programmed instructions, also comprises:
The executing state that the corresponding said main frame of transmission writes instruction after said flash controller is accomplished all said main frames to write instruction is to said host computer system.
5. the method for flash memory being assigned programmed instructions according to claim 4; When wherein among corresponding said main frame writes the executing state of instruction, comprising at least one sequencing mistake, then receive said main frame again from said host computer system and write that the main frame of corresponding said at least one sequencing mistake writes instruction and writes data among the instruction by said flash controller.
6. the method for flash memory being assigned programmed instructions according to claim 4; When wherein among corresponding said main frame writes the executing state of instruction, comprising at least one sequencing mistake, then receive all said main frames again from said host computer system and write instruction and said write data by said flash controller.
7. system of flash memory being assigned programmed instructions; The data that are used for coming from a host computer system write to a flash chip; Wherein said flash chip comprises one first buffer zone, one second buffer zone and a storage area, and the said system that flash memory is assigned programmed instructions comprises:
First module writes instruction in order to use a primary instruction ordering agreement from said host computer system, to receive a plurality of main frames;
Second module is assigned instruction sequences to said host computer system in order to write instruction transmission one according to said main frame; And
Three module; In order to from said host computer system, to receive said main frame in order and write instruction and write a plurality of data that write of instruction with corresponding said main frame according to the said instruction sequences of assigning; And assign a fast program fetch instruction so that the said write data are write in the said flash chip to said flash chip respectively
Wherein said three module receives said main frame and writes one first main frame among the instruction and write among instruction and the said write data corresponding said first main frame and write one first of instruction and write data from said host computer system; Assign said fast program fetch instruction to said flash chip and write data transmission to said first buffer zone with said first, wherein said first writes data is moved to said second buffer zone and from said second buffer zone from said first buffer zone and is written into said storage area;
Wherein said three module receives said main frame and writes one second main frame among the instruction and write among instruction and the said write data corresponding said second main frame and write one second of instruction and write data from said host computer system,
Wherein said three module is assigned said fast program fetch instruction to write data transmission to said first buffer zone with said second to said flash chip; Wherein said second writes data is moved to said second buffer zone and from said second buffer zone from said first buffer zone and is written into said storage area; And write data and moved to said second buffer zone from said first buffer zone when said first, said second writes data is transferred in said first buffer zone.
8. according to claim 7 flash memory is assigned the system of programmed instructions, wherein said second module is assigned order that said main frame writes instruction according to said host computer system and is decided and saidly assign instruction sequences and the said instruction sequences of assigning is transmitted said host computer system.
9. according to claim 7 flash memory is assigned the system of programmed instructions, a plurality of logical addresses that wherein said second module writes instruction according to the said main frame of correspondence decide saidly to be assigned instruction sequences and the said instruction sequences of assigning is transmitted said host computer system.
10. according to claim 7 flash memory is assigned the system of programmed instructions, also comprises:
Four module, the executing state that writes instruction in order to the corresponding said main frame of transmission after accomplishing all said main frames to write instruction is given said host computer system.
11. according to claim 10 flash memory is assigned the system of programmed instructions, also comprises:
The 5th module; When comprising at least one sequencing mistake among the executing state that writes instruction when corresponding said main frame, from said host computer system, receive said main frame again and write that the main frame of corresponding said at least one sequencing mistake writes instruction and writes data among the instruction.
12. according to claim 10 flash memory is assigned the system of programmed instructions, also comprises:
The 6th module when comprising at least one sequencing mistake among the executing state that writes instruction when corresponding said main frame, receives said main frame again and writes instruction and said write data from said host computer system.
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| CN102707771A (en) * | 2012-04-01 | 2012-10-03 | 宜鼎国际股份有限公司 | Embedded memory module and plugged mainboard thereof |
| TWI544487B (en) * | 2015-01-22 | 2016-08-01 | 慧榮科技股份有限公司 | Data storage device and flash memory control method |
| CN107632902B (en) * | 2016-07-18 | 2021-03-30 | 深圳衡宇芯片科技有限公司 | Method, controller and storage system for replying data in case of programming failure |
| US20200073595A1 (en) * | 2018-09-02 | 2020-03-05 | Silicon Motion Inc. | Flash memory controller capable of improving IOPS performance and corresponding method |
| TWI808229B (en) * | 2019-07-29 | 2023-07-11 | 宜鼎國際股份有限公司 | System and method capable of controlling electronic apparatus to execute program |
| US11392499B2 (en) * | 2020-09-18 | 2022-07-19 | Kioxia Corporation | Dynamic buffer caching of storage devices |
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