CN100342416C - Data drive circuit for organic LED display - Google Patents
Data drive circuit for organic LED display Download PDFInfo
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- CN100342416C CN100342416C CNB2004100353438A CN200410035343A CN100342416C CN 100342416 C CN100342416 C CN 100342416C CN B2004100353438 A CNB2004100353438 A CN B2004100353438A CN 200410035343 A CN200410035343 A CN 200410035343A CN 100342416 C CN100342416 C CN 100342416C
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Abstract
The present invention relates to a data drive circuit for organic LED displays. The present invention divides K-bit pixel data into N-bit data and M-bit data; a plurality of groups of N-bit data is respectively processed by a plurality of main digital-analog current converters and a plurality of main current storing, reproducing and regenerating current currents for generating a plurality of main regenerating current; a plurality of groups of M-bit data is respectively processed by a subsidiary digital-analog current converter and a plurality of subsidiary current storing, reproducing and regenerating current currents for generating a plurality of subsidiary regenerating current; pixel brightness is relevant to the addition of corresponding main regenerating current and the subsidiary regenerating current. The present invention can effectively reduce errors because of the differences of the component characteristics of a plurality of traditional digital-analog converters.
Description
Technical field
The present invention is relevant for a kind of data drive circuit, and particularly relevant for a kind of data drive circuit that is used for organic light emitting diode display.
Background technology
Please refer to Fig. 1, the driving circuit 100 of its expression conventional thin film transistor (Thin Film Transistor) display panels (Liquid Crystal Display Panel).Driving circuit 100 includes horizontal shifting register (Horizontal Shift Register) 102, level shifter (LevelShifter) 104, latch (Latch) 106, digital analog converter (Digital to AnalogConverter, DAC) 108 and vertical transfer register (Vertical Shift Register) 110.
110 of vertical transfer registers are in order to exporting a plurality of vertical movement control signals, for example VSR (1)-VSR (3).Vertical movement control signal VSR (1)-VSR (3) is in regular turn for enabling, so that the aanalogvoltage V (1) that digital analog converter 108 (1)-108 (X) is exported-V (X) is orderly sent in the corresponding pixel 112.Wherein, the brightness of pixel 112 will be relevant to the aanalogvoltage V that is received.
Can convert the digital data into the digital analog converter of analog current by digital analog converter 108 with traditional TFT LCD driving circuit shown in Figure 1, and with Organic Light Emitting Diode (the Organic Light Emitting Diode of pixel with current-driven (currentdriven type), OLED) after pixel replaces, can obtain the driving circuit of current-driven TFT-OLED panel.
Yet, because the threshold voltage value (thresholdvoltage) of the TFT in each D/A conversion circuit and mobility (mobility) and incomplete same make the electric current of each D/A conversion circuit output will have error to produce.So, will make the shown picture of TFT-OLED panel that the phenomenon of brightness irregularities be arranged.Therefore, how to reduce the influence that the component characteristic difference of D/A conversion circuit is caused, one of problem of endeavouring for this area.
Summary of the invention
In view of this, purpose of the present invention is exactly that a kind of data drive circuit that is used for organic light emitting diode display is being provided, the present invention can reduce the error of the output current of D/A conversion circuit effectively, to improve the luminance uniformity of the shown picture of TFT-OLED panel.
According to purpose of the present invention, a kind of data drive circuit is proposed, it is applied in the display, and this display has one first pixel and one second pixel.Data drive circuit is in order to receive one first pixel data and one second pixel data, and first pixel data and second pixel data respectively have the K position, and K is a positive integer.Data drive circuit of the present invention comprises one first main number analog current converter and one second main number analog current converter, one first main electric current storage replication and regenerative current circuit (currentcopier/current mirror with Vgs stored function) and one second main electric current storage replication and regenerative current circuit, one auxiliary figure analog current converter, and one first auxiliary current storage replication and regenerative current circuit and one second auxiliary current storage replication and regenerative current circuit.
The first main number analog current converter and one second main number analog current converter are in order to convert the N bit data of first pixel data and the N bit data of second pixel data to one first main output current and one second main output current respectively, and N is a positive integer.The first main electric current storage replication and regenerative current circuit and one second main electric current storage replication and regenerative current circuit according to the first main output current and the second main output current, are exported one first main regenerative current and one second main regenerative current in order to respectively respectively.Auxiliary figure analog current converter receives the M bit data of first pixel data and the M bit data of second pixel data in order to (sequentially) sequentially, and produce one first auxiliary output current accordingly and assist output current with one second, M is a positive integer, and N adds M more than or equal to K.The first auxiliary current storage replication and regenerative current circuit and one second auxiliary current storage replication and regenerative current circuit, according to the first auxiliary output current and the second auxiliary output current, export one first auxiliary regenerative current and one second auxiliary regenerative current in order to respectively respectively.
Wherein, after first pixel receives the first main regenerative current and the first auxiliary regenerative current, the brightness of first pixel corresponding to the first main regenerative current and the first auxiliary regenerative current and, after second pixel receives the second main regenerative current and the second auxiliary regenerative current, the brightness of second pixel corresponding to the second main regenerative current and second assist regenerative current with.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail as follows:
Fig. 1 represents the driving circuit of conventional thin film transistor display panels.
Fig. 2 represents the driving circuit according to a kind of organic light emitting diode display of the present invention one first embodiment.
Fig. 3 represents the example of the circuit structure of main number analog current converter 210 (1).
Fig. 4 A and 4B represent the example of the circuit structure of main electric current storage replication and regenerative current circuit 212 (1), Fig. 4 A is expressed as the main electric current storage replication and the regenerative current circuit 212 (1) of electric current memory module, and Fig. 4 B is expressed as the main electric current storage replication and the regenerative current circuit 212 (1) of regenerative current pattern.
Fig. 5 represents the example of the circuit structure of auxiliary current storage replication and regenerative current circuit 216 (1).
The example of the circuit structure of Fig. 6 A and 6B remarked pixel 208 (1).
Fig. 7 represents the example of the circuit structure of auxiliary figure analog current converter 214 (1).
Fig. 8 represents horizontal control signal SR0, SR1, SR2 and SRX, and the example of the oscillogram of sweep signal Scan1 and Scan2.
Fig. 9 represents the driving circuit according to a kind of organic light emitting diode display of the present invention one second embodiment.
Figure 10 represents the example of the oscillogram of horizontal control signal SR0, SR1, SR2 and SRX, sweep signal Scan1 and the Scan2 of the second embodiment of the present invention and switch controlling signal CTRL.
The drawing reference numeral explanation
100: driving circuit
102: horizontal shifting register
104: level shifter
106: latch
108: digital analog converter
110,206: vertical transfer register
112,208: pixel
114,218: switches set
The 200:OLED display
202: pel array
206: data drive circuit
210: main number analog current converter
212: main electric current storage replication and regenerative current circuit
214: auxiliary figure analog current converter
216: auxiliary current storage replication and regenerative current circuit
220: main level shifter
222: auxiliary level shifter
224A, 224B: signal transmssion line
602：OLED
Embodiment
Embodiment one
Please refer to Fig. 2, its expression is according to the driving circuit of a kind of Organic Light Emitting Diode (OLED) display of the present invention one first embodiment.OLED display 200 includes a pel array 202, a vertical transfer register 204 and a data drive circuit 206.Pel array 202 is made up of multiple row multirow OLED pixel (Pixel), for example is pixel 208 (1,1) and 208 (1,2) in the first row pixel.204 weeks of vertical transfer register, each sweep signal was in order to control each row pixel to export a plurality of sweep signal Scan to pel array 202.For example, sweep signal Scan1 inputs to the first row pixel to control this first row pixel.Data drive circuit then is in order to receive many group pixel datas, for example is the pixel data Dt (1,1) and Dt (1,2) corresponding to pixel 208 (1,1) and 208 (1,2).Pixel data Dt (1,1) and Dt (1,2) respectively have the K position, and K is a positive integer.
Having the capable pixel of X with pel array 202 is the example explanation, and X is a positive integer.Data drive circuit 206 includes a horizontal shifting register 208, an X main number analog current converter 210, an X main electric current storage replication and regenerative current circuit 212, an auxiliary figure analog current converter 214 and X auxiliary current storage replication and regenerative current circuit (current copier/current mirror withVgs stored function) 216.Horizontal shifting register 208 comprises SR (0)-SR (X) in order to X+1 horizontal control signal of output.X main number analog current converter 210 (1)-210 (X) is in order to respectively under the control of control signal SR (1)-SR (X), receive N bit data respectively, and produce main output current IN (1)-IN (X) respectively accordingly corresponding to all pixel data Dt of particular row pixel.According to main output current IN (1)-IN (X), (1)-IN ' (X) to export main regenerative current IN ' respectively in order to respectively for individual main electric current storage replication of X and regenerative current circuit.
Auxiliary figure analog current converter 214 is in order to receive the M bit data corresponding to all pixel data Dt of particular row pixel sequentially, and produce auxiliary output current IM (1)-IM (X) accordingly, and M is a positive integer, N adds M more than or equal to K, preferably, N adds M and equals K.According to auxiliary output current IM (1)-IM (X), (1)-IM ' (X) for the auxiliary regenerative current IM ' of output respectively in order to respectively for auxiliary current storage replication and regenerative current circuit 216 (1)-216 (X).
Wherein, main regenerative current IN ' (1)-IN ' (X) and auxiliary regenerative current IM ' (1)-IM ' (X) input to all pixels of particular row respectively.In all pixels of particular row receive main regenerative current IN ' (1)-IN ' (X) with auxiliary regenerative current IM ' (1)-IM ' (X) afterwards, the brightness of all pixels of particular row correspond respectively to separately main regenerative current IN ' with auxiliary output current IM's ' and.
Further illustrate as follows at technical characterictic of the present invention.Data drive circuit 206 more can have X group switches set 218 (1)-218 (X), an X main level shifter 220 (1)-220 (X) and an auxiliary level shifter 222.Main level shifter 220 (1)-220 (X) is the level shifter of N position, and auxiliary level shifter 222 then is the level shifter of M position.Signal transmssion line 224A optionally is electrically connected with level shifter 220 (1)-220 (X) via switches set 218 (1)-218 (X), and main level shifter 220 (1)-220 (X) is electrically connected with main number analog current converter 210 (1)-210 (X).
Main number analog current converter 210 (1)-210 (X) under the control of horizontal SR (1)-SR (X), receives the N bit data of X group pixel data Dt respectively respectively.That is, when horizontal control signal SR (0)-SR (X) in regular turn when enabling, switches set 218 (1)-218 (X) conducting in regular turn under the control of horizontal control signal SR (1)-SR (X).At this moment, the N bit data general of X group pixel data Dt is sent in the corresponding main level shifter 220 (1)-220 (X) via the switches set 218 (1)-218 (X) of conducting in regular turn.Main level shifter 220 (1)-220 (X) is organized X the N bit data of pixel data Dt respectively and is amplified, and exports main number analog current converter 210 (1)-210 (X) to.
Each is electrically connected main number analog current converter 210 (1)-210 (X) with main electric current storage replication and regenerative current circuit 212 (1)-212 (X) respectively via switch SW A (1)-SWA (X).Switch SW A (1)-SWA (X) is subjected to the control of horizontal control signal SR (1)-SR (X).Main electric current storage replication and regenerative current circuit 212 (1)-212 (X) also are subjected to the control of horizontal control signal SR (1)-SR (X), and main electric current storage replication and regenerative current circuit 212 (1)-212 (X) also all have an electric current memory module and a regeneration current-mode.
When horizontal control signal SR (1)-SR (X) in regular turn when enabling (enabled), when for example transferring high level to, switch SW A (1)-SWA (X) conducting in regular turn, main electric current storage replication and regenerative current circuit 212 (1)-212 (X) change the electric current memory module in regular turn into, and receive main output current IN (1)-IN (X) in regular turn.When horizontal control signal SR (1)-SR (X) is forbidding (disabled) in regular turn, it for example is low level, switch SW A (1)-SWA (X) transfers not conducting in regular turn to, main electric current storage replication and regenerative current circuit 212 (1)-212 (X) change the regenerative current pattern in regular turn into, and (1)-IN ' (X) to continue the main regenerative current IN ' of output.Main regenerative current IN ' (1)-IN ' size (X) equals the size of main output current IN (1)-IN (X).
On the other hand, signal transmssion line 224B is electrically connected with auxiliary level shifter 222, and auxiliary level shifter 222 is electrically connected with auxiliary figure analog current converter 214.Auxiliary level shifter 222 receives and amplifies the M bit data of X group pixel data Dt in regular turn, the M bit data of X group pixel data Dt after the amplification inputs to auxiliary figure analog current converter 214 in regular turn and carries out digital-to-analogue conversion, to export auxiliary output current IM (1)-IM (X) to auxiliary current storage replication and regenerative current circuit 216 (1)-216 (X).
Auxiliary current storage replication and regenerative current circuit 216 (1)-216 (X) also are subjected to the control of horizontal control signal SR (1)-SR (X), and all have electric current memory module and regenerative current pattern.When horizontal control signal SR (1)-when SR (X) was respectively and enables, auxiliary current storage replication and regenerative current circuit 216 (1)-216 (X) changed the electric current memory module respectively into, and receive auxiliary output current IM (1)-IM (X) respectively.When horizontal control signal SR (1)-SR (X) was respectively forbidding, auxiliary current storage replication and regenerative current circuit 216 (1)-216 (X) changed the regenerative current pattern respectively into, and (1)-IM ' (X) to continue the auxiliary regenerative current IM ' of output.Auxiliary regenerative current IM ' (1)-IM ' size (X) equals the size of auxiliary output current IM (1)-IM (X).
Data drive circuit 206 also includes X switch SW C (1)-SWC (X).The main electric current storage replication and the output terminal of regenerative current circuit 212 (1) and the output terminal of auxiliary current storage replication and regenerative current circuit 216 (1) all are electrically connected with one first end of switch SW C (1), and one second end of switch SW C (1) and pixel 208 (1,1) are electrically connected.The main electric current storage replication and the output terminal 212 (2) of regenerative current circuit and the output terminal of auxiliary current storage replication and regenerative current circuit 216 (2) all are electrically connected with one first end of switch SW C (2), one second end of switch SW C (2) and pixel 208 (1,2) are electrically connected.
When horizontal control signal SR (1) is forbidding, switch SW C (1) conducting, make main regenerative current IN ' (1) and auxiliary regenerative current IM ' (1) input to pixel 208 (1 simultaneously, 1), so that pixel 208 (1,1) produce corresponding to main regenerative current IN ' (1) and auxiliary regenerative current IM's ' (1) and brightness.When horizontal control signal SR (2) is forbidding, switch SW C (2) conducting, make main regenerative current IN ' (2) and auxiliary regenerative current IM ' (2) input to pixel 208 (1 simultaneously, 2), so that pixel 208 (1,2) produce corresponding to main regenerative current IN ' (1) and auxiliary regenerative current IM's ' (1) and brightness.The output terminal of the output terminal of remaining main electric current storage replication and regenerative current circuit 212 (3)-212 (X) and auxiliary current storage replication and regenerative current circuit 216 (3)-216 (X) is identical with aforesaid way with connected mode and the mode of operation of switch SW C (3)-SWC (X), will not repeat in this.
Preferably, the N bit data of pixel data Dt is least significant bit (LSB) (the Least Significantbit of N position, LSB) data Dt_NLSB, and the M bit data among the pixel data Dt is highest significant position (Most Significant bit, MSB) the data Dt_MMSB of M position.The pairing analog current of pixel data Dt equals the pairing analog current of LSB data Dt_NLSB of N position, with the pairing analog current of MSB data Dt_MMSB of M position and.
For instance, if pixel data is (101100)
2, then the LSB data of its N position are (100)
2, the MSB data of its M position then are (101)
2Because (101100)
2=(101)
2* 2
3+ (100)
2So,, (101100)
2Pairing analog current can be obtained by following method: produce respectively earlier (101)
2Pairing analog current and (100)
2Pairing analog current is again with (101)
2Pairing analog current multiply by 2
3Then, will multiply by 2
3After (101)
2Pairing analog current and (100)
2Pairing analog current addition, can obtain (101100)
2Pairing analog current.Wherein, the MSB data with the M position multiply by 2
3Operation can be 2 by means of using the current value size in the auxiliary figure analog current converter 214
3Current source doubly gets final product.
Because the M position MSB data Dt_MMSB among the pixel data Dt is to the influence of the brightness of the pixel N position LSB data Dt_NLSB in the pixel data Dt, so the present invention makes all pixels all share same auxiliary figure analog current converter 214, M position MSB data Dt_MMSB among all pixel data Dt is carried out digital-to-analogue conversion, to improve the luminance uniformity and the color uniformity of display pannel.In the present embodiment, because all M position MSB data Dt_MMSB all use same auxiliary figure analog current converter 214 to carry out digital-to-analogue conversion, use different D/A conversion circuits to compare with the pixel data of traditional each row pixel, present embodiment can reduce tradition effectively because the error of the threshold voltage value of the TFT in each D/A conversion circuit and mobility and the incomplete same output current generation that causes.
Example with main number analog current converter 210 (1), main electric current storage replication and regenerative current circuit 212 (1), auxiliary current storage replication regenerative current circuit 216 (1), pixel 208 (1) and auxiliary figure analog current converter 214 (1) cooperates circuit diagram to be described as follows respectively.Suppose that pixel data Dt is 6, be respectively a D0, D1, D2, D3, D4 and D5 from right to left, that is pixel data Dt equals (D5 D4 D3 D2 D1 D0)
2Suppose M=N=3 simultaneously, then the MSB data of M position are (D5 D4 D3)
2, and the LSB data of N position are (D2 D1 D0)
2
Please refer to Fig. 3, the example of the circuit structure of its expression main number analog current converter 210 (1).Main number analog current converter 210 (1) is made up of 9 N transistor npn npn QA1-QA3, QB1-QB3 and QC1-QC3.The source grounding of transistor QA1-QA3, and grid all is biased in voltage Vbias1.The source electrode of transistor QB1-QB3 is coupled to the drain electrode of transistor QA1-QA3 respectively, and grid is then distinguished inversion signal XD0, XD1 and the XD2 of received signal D0, D1 and D2.The source electrode of transistor QC1-QC3 is coupled to the drain electrode of transistor QA1-QA3 respectively, and the grid of transistor QC1-QC3 then all is biased in voltage Vbias2.The channel width of transistor QA1-QA3 and the ratio of length are respectively W/L, 2W/L and 4W/L, and it produces electric current I 1,2I1 and 4I1 respectively.As the LSB of N position data (D2 D1 D0)
2Be (100)
2The time, (XD2 XD1 XD0)
2Equal (011)
2, make not conducting of transistor QB1, transistor QB2 and QB3 conducting, at this moment, the output terminal DAC1_out of main number analog current converter 210 will draw main output current IN (1) and be the electric current of I1.
Please refer to Fig. 4 A and 4B, the example of the circuit structure of its represented main electric current storage replication and regenerative current circuit 212 (1), wherein, Fig. 4 A is expressed as the main electric current storage replication and the regenerative current circuit 212 (1) of electric current memory module, and Fig. 4 B is expressed as the main electric current storage replication and the regenerative current circuit 212 (1) of regenerative current pattern.
Main electric current storage replication and regenerative current circuit 212 (1) by N transistor npn npn QD1, QD4 and QD5, reach P transistor npn npn QD2, QD3 and QD6 is formed.Input end Input1 couples by the switch SW A (1) and the output terminal DAC1_out of main number analog current converter 210 (1).The source electrode of transistor QD1, QD2 and QD3 is coupled to high level VDD, and the grid of the drain electrode of transistor QD1, QD2 and QD3 is coupled to node N1.The two ends of capacitor C 1 then couple with grid and the source electrode of transistor QD2 respectively.The drain electrode of the source electrode of the drain electrode of transistor QD2, transistor QD5 and transistor QD4 all is coupled to the source electrode of transistor QD6.The grounded drain of transistor QD6.The drain electrode of transistor QD3 is as output terminal Output1.The grid of transistor QD1 receives horizontal control signal SR0.The grid of transistor QD4, QD5 and QD6 receives horizontal control signal SR1.
When horizontal control signal SR0 when enabling, transistor QD1 conducting, capacitor C 1 is discharged, so that the voltage on the capacitor C 1 is zero to finish replacement (reset) operation of capacitor C 1.When horizontal control signal SR1 when enabling, main electric current storage replication and regenerative current circuit 212 (1) enter the electric current memory module, transistor QD4 and QD5 conducting and produce electric current I D1.Not conducting of transistor QD6 this moment.When capacitor C 1 charges to one first particular level, transistor QD2 conducting, and produce electric current I D2.When capacitor C 1 continues to charge to one second particular level, electric current I D2 will equal electric current I 1 shown in Figure 3, and capacitor C 1 will stop charging and remain in this second particular level this moment.
Please refer to Fig. 4 B, when horizontal control signal SR1 is when forbidding, main electric current storage replication and regenerative current circuit 212 (1) enter the regenerative current pattern, transistor QD4 and not conducting of QD5 and transistor QD6 conducting.At this moment, because capacitor C 1 is maintained at second particular level, and make transistor QD2 continue conducting, and produce electric current I D3 that the size of electric current I D3 equates with I1.Because the source electrode of transistor QD3 is identical with transistor QD2 with the voltage difference of grid, flow through so transistor QD3 will have electric current I D4, and the size of electric current I D4 equals the size of electric current I D3, also equal the size of electric current I 1.At this moment, main electric current storage replication and regenerative current circuit 212 (1) will be exported main regenerative current IN ' (1) and be the electric current of I4.
Please refer to Fig. 5, the example of the circuit structure of its expression auxiliary current storage replication and regenerative current circuit 216 (1).Auxiliary current storage replication and regenerative current circuit 216 (1) by N transistor npn npn QD7, QD10 and QD11, and P transistor npn npn QD8, QD9 and QD12 formed.Its connected mode and mode of operation and main electric current storage replication and regenerative current circuit 212 (1) are approximate.When the regenerative current pattern, the voltage on the capacitor C 2 is maintained at one the 3rd particular level, and electric current I D5 and ID6 flow through transistor QD8 and QD9 respectively.Auxiliary current storage replication and regenerative current circuit 216 (1) will be exported auxiliary regenerative current IM ' (1) and be the electric current of ID6.
Please refer to Fig. 6 A and 6B, the example of the circuit structure of its represented pixel 208 (1).Pixel 208 (1) by N transistor npn npn QE2, QE4 and QE5, and P transistor npn npn QE3 and a light emitting diode OLED 602 formed.The negativing ending grounding of OLED 602, and the source electrode of anode and transistor QE5 couples.The two ends of capacitor C 3 are respectively coupled to the grid of transistor QE5 and the negative electrode of OLED (Cathode).The drain electrode of the source electrode of transistor QE2 and transistor QE3 is coupled to the drain electrode of transistor QE5.The drain electrode of transistor QE4 is coupled to the drain electrode of transistor QE5, and the source electrode of transistor QE4 then is coupled to the grid of transistor QE5.Transistor QE1 is switch SW C (1), and its source electrode is in order to coupling with output terminal Output1 and Output2, and the drain electrode of its drain electrode and transistor QE2 couples.
Please refer to Fig. 6 A, horizontal control signal SR1 inputs to the grid of transistor QE1, and sweep signal Scan1 inputs to the grid of transistor QE2, QE3 and QE4.When horizontal control signal SR1 for forbidding and sweep signal Scan1 when enabling, transistor QE1 conducting, main regenerative current IN ' (1) inputs to pixel 208 (1,1) simultaneously with auxiliary regenerative current IM ' (1), flow through transistor QE2, QE4 and QE5, and to capacitor C 3 chargings.When the voltage on the capacitor C 3 is one the 4th particular level, the size that flows through the electric current I E1 of transistor QE5 equal main regenerative current IN ' (1) with auxiliary regenerative current IM's ' (1) and.
Please refer to Fig. 6 B, when sweep signal Scan1 transfers forbidding to, transistor QE2 and not conducting of QE4, transistor QE3 and QE5 conducting.At this moment,, make the electric current I E4 that flows through transistor QE5 equal IE3 because capacitor C 3 is maintained at the 4th particular level, that is equal main regenerative current IN ' (1) with auxiliary regenerative current IM's ' (1) and.The pixel 208 (1,1) of this moment enters the pixel current regeneration mode, up to entering next picture, sweep signal Scan1 again transfer to enable till.
Please refer to Fig. 7, the example of the circuit structure of its expression auxiliary figure analog current converter 214.Auxiliary figure analog current converter 214 is made up of 9 N transistor npn npn QF1-QF3, QG1-QG3 and QH1-QH3.Grid difference received signal D3, the D4 of transistor QG1-QG3 and inversion signal XD3, XD4 and the XD5 of D5.Its connected mode and mode of operation are similar to main number analog current converter 210 (1).Different is, the channel width of transistor QF1-QF3 and the ratio of length are respectively 8W/L, 16W/L and 32W/L, and it produces electric current 8I1,16I1 and 32I1 respectively.
Please refer to Fig. 8, it represents horizontal control signal SR0, SR1, SR2 and SRX, and the example of the oscillogram of sweep signal Scan1 and Scan2.In sweep signal Scan1 is to enable and horizontal control signal SR1 is in the time period T1 that enables, and main electric current storage replication and regenerative current circuit 212 (1) are the electric current memory module with auxiliary current storage replication and regenerative current circuit 216 (1).In sweep signal Scan1 be enable and the time period T2 of horizontal control signal SR1 for forbidding in, main electric current storage replication and regenerative current circuit 212 (1) are the regenerative current pattern with auxiliary current storage replication and regenerative current circuit 216 (1).And in the time period T3 of sweep signal Scan1 for forbidding, pixel 208 (1,1) enters the pixel current regeneration mode.
In present embodiment, when the high-voltage level of the pixel data Dt of numeral was enough big, main level shifter 210 can save with auxiliary level shifter 222.And above-mentioned switch can be realized by N transistor npn npn, P transistor npn npn or transmission gate circuit (Transmission Gate).The present invention is not limited to above-mentioned main number analog current converter and auxiliary figure analog current converter, all can as long as digital signal can be changed into the digital analog converter of analog current signal.The present invention also is not limited to above-mentioned main electric current storage replication and regenerative current circuit and auxiliary current storage replication and regenerative current circuit, and other has the current replication circuit (current copier) that the voltage difference of the grid of TFT and source electrode can be stored or current mirror (current mirror) all applicable to the present invention.
It is the example explanation that present embodiment outputs current to pixel with main electric current storage replication and regenerative current circuit and auxiliary current storage replication and regenerative current circuit, and right the present invention also is applicable to the design that main electric current storage replication and regenerative current circuit and auxiliary current storage replication and regenerative current circuit draw (sink) pixel current.
In addition, the N bit data in the pixel data of the present invention also can be N position MSB data, and the M bit data in the pixel data also is M position LSB data.The present invention also is not limited to and only uses an auxiliary figure analog current converter, also can use plural auxiliary figure analog current converter, and the data that cooperate the K bit data with pixel data to be divided into more than three groups simultaneously get final product.Very and, corresponding to delegation's pixel, the present invention also can use two main electric current storage replications and regenerative current circuit, two auxiliary current storage replications and regenerative current circuit, and two auxiliary current storage replications and regenerative current circuit simultaneously, with alternately in horizontal control signal when enabling or forbidding, provide main regenerative current and auxiliary regenerative current to pixel.
Embodiment two
In embodiment one, switch SW C (1)-SWC (X) is controlled by horizontal control signal SR (1)-SR (X) respectively, and in embodiment two, switch SW C (1)-SWC (X) is controlled by switch controlling signal CTRL simultaneously, as shown in Figure 9.Please be simultaneously with reference to Figure 10, the example of horizontal control signal SR0, SR1, SR2 and SRX, sweep signal Scan1 and the Scan2 of its expression second embodiment of the present invention and the oscillogram of switch controlling signal CTRL.After all main electric current storage replications and regenerative current circuit and auxiliary current storage replication and regenerative current circuit all produce main regenerative current and auxiliary regenerative current electric current, switch controlling signal CTRL transfers to and enabling, and makes all conductings of switch SW C (1)-SWC (X).With the first row pixel is example.At this moment, main regenerative current IN ' (1) and auxiliary regenerative current IM ' (1) input to pixel 208 (1,1), and main regenerative current IN ' (2) and auxiliary regenerative current IM ' (2) input to pixel 208 (1,2).Main regenerative current IN ' (3)-IN ' (X) and auxiliary regenerative current IM ' (3)-IM ' (X) then input to respectively pixel 208 (1,3)-208 (1, X) so that corresponding pixel is shinny.
The disclosed data drive circuit that is used for organic light emitting diode display of the above embodiment of the present invention can reduce the error of the output current of D/A conversion circuit effectively, to improve the luminance uniformity of the shown picture of TFT-OLED panel.
In sum; though the present invention with a preferred embodiment openly as above; right its is not in order to limit the present invention; any those skilled in the art; under the situation that does not break away from the spirit and scope of the present invention; can carry out various changes and modification, so protection scope of the present invention is as the criterion when looking the claim restricted portion that is proposed.
Claims (9)
1. data drive circuit, it is applied in the organic light emitting diode display, this organic light emitting diode display has one first pixel and one second pixel, this data drive circuit is in order to receive one first pixel data and one second pixel data, this first pixel data and this second pixel data respectively have the K position, K is a positive integer, and this data drive circuit comprises:
One first main number analog current converter and one second main number analog current converter, in order to convert the N bit data of this first pixel data and the N bit data of this second pixel data to one first main output current and one second main output current respectively, N is a positive integer;
One first main electric current storage replication and regenerative current circuit and one second main electric current storage replication and regenerative current circuit, according to this first main output current and this second main output current, export one first main regenerative current and one second main regenerative current in order to respectively respectively;
One auxiliary figure analog current converter in order to the M bit data that receives this first pixel data and the M bit data of this second pixel data, and produces one first auxiliary output current accordingly and assists output current with one second, and M is a positive integer; And
One first auxiliary current storage replication and regenerative current circuit and one second auxiliary current storage replication and regenerative current circuit, according to this first auxiliary output current and this second auxiliary output current, export one first auxiliary regenerative current and one second auxiliary regenerative current in order to respectively respectively;
Wherein, after this first pixel receives this first main regenerative current and this first auxiliary regenerative current, the brightness of this first pixel corresponding to this first main regenerative current and this first auxiliary regenerative current and, after this second pixel receives this second main regenerative current and this second auxiliary regenerative current, the brightness of this second pixel corresponding to this second main regenerative current with this second assist regenerative current with.
2. data drive circuit as claimed in claim 1, wherein this data drive circuit also comprises a horizontal shifting register, in order to export one first horizontal control signal and one second horizontal control signal, this first main number analog current converter and this second main number analog current converter under the control of this first horizontal control signal and this second horizontal control signal, receive the N bit data of this first pixel data and the N bit data of this second pixel data respectively respectively.
3. data drive circuit as claimed in claim 2, wherein this first and second main electric current storage replication and regenerative current circuit and this first and second auxiliary current storage replication and regenerative current circuit all have an electric current memory module and a regeneration current-mode;
When this first and second horizontal control signal is respectively when enabling, this first and second main electric current storage replication and regenerative current circuit change this electric current memory module respectively into, and receive this first and second main output current respectively;
When this first and second horizontal control signal is respectively when enabling, this first and second auxiliary current storage replication and regenerative current circuit change this electric current memory module respectively into, and receive this first and second auxiliary output current respectively;
When this first and this second horizontal control signal be respectively when forbidding, this first and second main electric current storage replication and regenerative current circuit change this regenerative current pattern respectively into, and continue output this first and this second main regenerative current, this first and the size of this second main regenerative current equal the size of this first and second main output current;
When this first and this second horizontal control signal be respectively when forbidding, this first and second auxiliary current storage replication and regenerative current circuit change this regenerative current pattern respectively into, and continue output this first and this second auxiliary regenerative current, this first and the size of this second auxiliary regenerative current equal the size of this first and second auxiliary output current.
4. data drive circuit as claimed in claim 3, wherein this data drive circuit also includes one first switch and a second switch, the output terminal of this first main electric current storage replication and regenerative current circuit and the output terminal of this first auxiliary current storage replication and regenerative current circuit all are electrically connected with one first end of this first switch, and one second end of this first switch is electrically connected with this first pixel;
The output terminal of this second main electric current storage replication and regenerative current circuit and the output terminal of this second auxiliary current storage replication and regenerative current circuit all are electrically connected with one first end of this second switch, and one second end of this second switch is electrically connected with this second pixel;
When this first horizontal control signal was forbidding, this first switch conduction made this first main regenerative current and this first auxiliary regenerative current input to this first pixel; When this second horizontal control signal was forbidding, this second switch conducting made this second main regenerative current and this second auxiliary regenerative current input to this second pixel.
5. data drive circuit as claimed in claim 3, wherein this data drive circuit also includes one first switch and a second switch, all be subjected to the control of a switch controlling signal, the output terminal of this first main electric current storage replication and regenerative current circuit and this first auxiliary current storage replication and regenerative current circuit all is electrically connected with one first end of this first switch, and one second end of this first switch is electrically connected with this first pixel;
The output terminal of this second main electric current storage replication and regenerative current circuit and this second auxiliary current storage replication and regenerative current circuit all is electrically connected with one first end of this second switch, and one second end of this second switch is electrically connected with this second pixel;
When this switch controlling signal when enabling, this first switch conduction, make this first main regenerative current and this first auxiliary regenerative current input to this first pixel, and this second switch conducting, make this second main regenerative current and this second auxiliary regenerative current input to this second pixel.
6. data drive circuit as claimed in claim 1, wherein when M adds N and equals K, the least significant bit (LSB) data that this N bit data in this first pixel data is the N position, the highest significant position data that this M bit data in this first pixel data is the M position, this N bit data in this second pixel data is N position least significant bit (LSB) data, and this M bit data in this second pixel data is M position highest significant position data.
7. data drive circuit as claimed in claim 1, wherein when M adds N and equals K, this N bit data in this first pixel data is N position highest significant position data, this M bit data in this first pixel data is M position least significant bit (LSB) data, this N bit data in this second pixel data is N position highest significant position data, and this M bit data in this second pixel data is M position least significant bit (LSB) data.
8. data drive circuit as claimed in claim 1, wherein this data drive circuit also comprises one first main level shifter, one second main level shifter and an auxiliary level shifter, this first main level shifter and this second main level shifter be in order to amplifying the N bit data of the N bit data of this first pixel data and this second pixel data respectively, and export this first main number analog current converter and this second main number analog current converter to; Should auxiliary level shifter in order to amplifying the M bit data in this first pixel data, and export this auxiliary figure analog current converter to.
9. organic light emitting diode display comprises:
One pel array comprises one first pixel and one second pixel;
One vertical transfer register is in order to export the one scan signal to this first pixel and this second pixel; And
One data drive circuit, in order to receive one first pixel data and one second pixel data, this first pixel data and this second pixel data respectively have the K position, and K is a positive integer, and this data drive circuit comprises:
One horizontal shifting register is in order to export one first horizontal control signal and one second horizontal control signal;
One first main number analog current converter and one second main number analog current converter, in order to respectively under the control of this first horizontal control signal and this second horizontal control signal, receive the N bit data of this first pixel data and the N bit data of this second pixel data, and producing one first main output current and one second main output current respectively accordingly, N is a positive integer;
One first main electric current storage replication and regenerative current circuit and one second main electric current storage replication and regenerative current circuit, according to this first main output current and this second main output current, export one first main regenerative current and one second main regenerative current in order to respectively respectively;
One auxiliary figure analog current converter in order to the M bit data that receives this first pixel data and the M bit data of this second pixel data, and produces one first auxiliary output current accordingly and assists output current with one second, and M is a positive integer; And
One first auxiliary current storage replication and regenerative current circuit and one second auxiliary current storage replication and regenerative current circuit, according to this first auxiliary output current and this second auxiliary output current, export one first auxiliary regenerative current and one second auxiliary regenerative current in order to respectively respectively;
Wherein, after this first pixel receives this first main regenerative current and this first auxiliary regenerative current, the brightness of this first pixel corresponding to this first main regenerative current and this first auxiliary regenerative current and, after this second pixel receives this second main regenerative current and this second auxiliary regenerative current, the brightness of this second pixel corresponding to this second main regenerative current with this second assist regenerative current with.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100353438A CN100342416C (en) | 2004-04-22 | 2004-04-22 | Data drive circuit for organic LED display |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100353438A CN100342416C (en) | 2004-04-22 | 2004-04-22 | Data drive circuit for organic LED display |
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| CN100342416C true CN100342416C (en) | 2007-10-10 |
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| EP0780986A2 (en) * | 1995-12-22 | 1997-06-25 | THOMSON multimedia | Auto calibrated digital to analog converter for a video display |
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| EP0780986A2 (en) * | 1995-12-22 | 1997-06-25 | THOMSON multimedia | Auto calibrated digital to analog converter for a video display |
| US6586888B2 (en) * | 2001-03-26 | 2003-07-01 | Rohm Co., Ltd. | Organic EL drive circuit and organic EL display device using the same |
| JP2003255898A (en) * | 2001-03-26 | 2003-09-10 | Rohm Co Ltd | Organic el drive circuit and organic el display device using the circuit |
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