CN110544455B

CN110544455B - Pixel circuit and driving method thereof

Info

Publication number: CN110544455B
Application number: CN201910778001.1A
Authority: CN
Inventors: 林峻锋
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2019-02-27
Filing date: 2019-08-22
Publication date: 2021-01-29
Anticipated expiration: 2039-08-22
Also published as: CN110544455A

Abstract

The invention provides a pixel circuit and a driving method thereof. The pixel circuit electrically connected with the first gate line and the second gate line comprises a light emitting diode, a driving transistor, a first switching transistor, a second switching transistor, a third switching transistor and a data capacitor. The driving method comprises the following steps: the driving transistor receives a low voltage; the first gate line and the second gate line respectively transmit a first gate signal and a second gate signal; during a first data receiving period, the data capacitor receives a first data voltage and a low voltage through the first switching transistor and the second switching transistor respectively, and further generates a data capacitor voltage difference; and during a second data receiving period, the data capacitor generates a pixel driving voltage corresponding to the brightness of the light emitting diode at the control node according to the data capacitor voltage difference and a second data voltage received by the third switching transistor.

Description

Pixel circuit and driving method thereof

Technical Field

The present invention relates to a pixel circuit and a driving method thereof, and more particularly, to a pixel circuit and a driving method thereof capable of adjusting a voltage of a control node of a light emitting diode during two data receiving periods.

Background

For the convenience of user operation, electronic products are usually provided with a display panel. The display panel is required to be matched with a timing controller for use, and the display panel comprises a plurality of pixel units which are arranged in an array. For convenience of description, it is assumed herein that Pixel Units (PU) in a display panel are arranged in M rows and N columns, and each pixel unit PU includes three Pixel Circuits (PC). Therefore, the display panel includes N columns of pixel circuits, where each column includes M × 3 pixel circuits. For convenience of description, m and n represent the number of rows and columns of the pixel circuit PC.

The timing controller transmits data signals DAT [1] -DAT [ M × 3] to the pixel circuits of each row through the pixel data lines DAT, and transmits gate signals GL [1] -GL [ N ] to the pixel circuits of each column through the gate lines GL [1] -GL [ N ]. For convenience of description, signals and wirings are represented by the same symbols, for example, GL [ n ] represents a gate line of an nth column and a gate signal of the nth column.

Fig. 1 is a schematic diagram of a pixel circuit in the prior art. The pixel circuits PC (m, n) in the mth row and the nth column are electrically connected to the pixel data lines DAT [ m ] and the gate lines GL [ n ]. The gate lines GL [ n ] are used for transmitting logic signals, and the pixel data lines DAT [ m ] are used for transmitting analog voltage signals. When the gate line GL [ n ] is at a high logic level (level) H, the data voltages transmitted by the representative data signals DAT [1] -DAT [ M × 3] correspond to the M × 3 pixel circuits in the nth row. On the contrary, when the gate line GL [ n ] is at the low logic level L, the data voltages transmitted by the representative data signals DAT [1] -DAT [ M × 3] do not correspond to the M × 3 pixel circuits in the nth row. The pixel circuit PC (M, n) includes a driving transistor TFT, a light emitting diode LED, a switching transistor M, and a voltage stabilizing capacitor Cs. Among them, the pixel circuit PC (m, n) may be: a red pixel circuit PCr (m, n), a green pixel circuit PCg (m, n), and a blue pixel circuit PCb (m, n).

It is assumed herein that the driving transistor TFT is an NMOS transistor, and the drain, gate and source thereof are electrically connected to the supply voltage source (Vdd), the switching transistor M and the anode of the light emitting diode LED, respectively. The cathode of the light emitting diode LED is electrically connected to a low voltage source (e.g., Vss). The voltage stabilizing capacitor Cs is electrically connected between the gate and the source of the driving transistor TFT. When the driving transistor TFT is turned on, a driving current i is generated_dFlows through the light emitting diode LED and then causes the light emitting diode LED to emit light. Therefore, the voltage level of the control node Nc affects not only the conduction of the driving transistor TFT but also the brightness of the light emitting diode LED.

Assuming that the switching transistor M is an NMOS transistor, its drain, gate and source are electrically connected to the pixel data line DAT [ M ] respectively]Gate line GL [ n ]]And a control node Nc. When the gate line GL n]At a high logic level, the switching transistor M is turned on and the data signal DAT [ M]To the control node Nc. At this time, the data signal DAT [ m ]]Will determine the conduction level of the driving transistor TFT and the driving current i_dAnd the brightness of the light emitting diode LED.

In general, the light emitting efficiency of the light emitting diodes LED in the red pixel circuit PCr (m, n), the green pixel circuit PCg (m, n), and the blue pixel circuit PCb (m, n) are not exactly the same. For example, if the same pixel driving voltage Vdis is used to represent the luminance of the gray scale value 255, the luminance of the red led LEDr according to the pixel driving voltage Vdis will be higher than that of the green led LEDg and that of the blue led LEDb because the luminance efficiency of the red led LEDr is better than that of the green led LEDg and that of the blue led LEDb. Therefore, depending on the color of the led, the voltage at the control node Nc of the pixel circuit PC needs to be adjusted within a sufficient range to adjust the voltage value according to the light emitting efficiency.

However, the source of the data signal DAT [ m ] is a timing controller, but the timing controller is a semiconductor chip, which can provide a limited maximum threshold data voltage (DATmax) (e.g., 6V). Accordingly, since the adjustable voltage value of the control node Nc is too small, the pixel circuits of different colors having the same gray-scale value cannot provide equivalent brightness when actually displaying.

Disclosure of Invention

The invention relates to a pixel circuit and a driving method thereof, which provides a mode of receiving data voltage in two degrees in two data receiving periods, so that a pixel data line can still generate the requirement of higher pixel driving voltage under the condition of transmitting the data voltage with lower voltage.

According to a first aspect of the present invention, a pixel circuit is provided. The pixel circuit is electrically connected to the pixel data line, the first gate line and the second gate line. The first gate line and the second gate line respectively transmit a first gate signal and a second gate signal. The pixel circuit includes: the driving circuit comprises a light emitting diode, a driving transistor, a first switching transistor, a second switching transistor, a third switching transistor and a data capacitor. The driving transistor is electrically connected to the control node and the light emitting diode, and receives a low voltage. The first switching transistor is electrically connected to the control node, the first gate line and the pixel data line. The first switching transistor is turned on in a first data receiving period according to the first gate signal, and then transmits a first data voltage on the pixel data line to the control node. The second switching transistor is electrically connected to the first gate line and the bias node. The second switching transistor receives the low voltage and is turned on during a first data receiving period according to the first gate signal, thereby transmitting the low voltage to the bias node. The third switching transistor is electrically connected to the bias voltage node, the second gate line and the pixel data line. The third switching transistor is turned on during a second data receiving period according to the second gate signal, thereby transmitting the second data voltage on the pixel data line to the bias node. The data capacitor is electrically connected to the control node and the bias node. The data capacitor generates a data capacitor voltage difference in a first data receiving period, and generates a pixel driving voltage corresponding to the brightness of the light emitting diode at the control node according to the data capacitor voltage difference in a second data receiving period.

According to a second aspect of the present invention, a driving method applied to a pixel circuit is provided. The pixel circuit is electrically connected to the pixel data line, the first gate line and the second gate line. The pixel circuit comprises a light emitting diode, a driving transistor, a first switching transistor, a second switching transistor, a third switching transistor and a data capacitor. The driving method comprises the following steps: the driving transistor receives a low voltage; the first gate line and the second gate line respectively transmit a first gate signal and a second gate signal; the first switching transistor is conducted in a first data receiving period according to the first grid signal, and then transmits a first data voltage on the pixel data line to the control node; the second switching transistor is conducted in a first data receiving period according to the first grid signal so as to transmit the low voltage to the bias voltage node; the third switching transistor is turned on in a second data receiving period according to the second gate signal, and further transmits a second data voltage on the pixel data line to the bias node; and the data capacitor generates a data capacitor voltage difference in a first data receiving period, and generates a pixel driving voltage corresponding to the brightness of the light emitting diode at the control node according to the data capacitor voltage difference in a second data receiving period.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments is made with reference to the accompanying drawings:

drawings

Fig. 1 is a schematic diagram of a pixel circuit employed in the prior art.

Fig. 2 is a schematic diagram of a pixel circuit according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of a pixel circuit according to another embodiment contemplated by the present invention.

Fig. 4A is a schematic diagram of an operation of a pixel circuit during a data receiving period Ta according to an embodiment of the invention.

Fig. 4B is a schematic diagram of the operation situation of the pixel circuit Tb during data reception according to the embodiment of the present invention.

Fig. 5 is a waveform diagram related to the operation of a pixel circuit according to an embodiment of the present invention.

Fig. 6 is a schematic diagram of a pixel unit according to an embodiment of the invention.

Fig. 7 is a waveform diagram associated with the operation of a pixel cell according to an embodiment of the present invention.

Description of reference numerals:

supply voltage Vdd low voltage Vss

Gate line (signal) GL [ n ], GL [ n-1], GL [ n +1]

Drive transistors TFT, TFTr, TFTg, TFTb

Pixel data line (Signal) DAT [ m ]

Switching transistors M, M1, M2, M3, M1r, M2r, M3r, M1g, M2g, M3g, M1b, M2b, M3b

Control nodes Nc, Ncr, Ncg, Ncb voltage stabilization capacitances Cs, 27

LED Pixel circuit PC (m, n)

Drive current i_d、i_dr、i_dg、i_db

Data capacitances Cb, Cbr, Cbg, Cbb

Bias nodes Nb, Nbr, Nbg, Nbb

Data voltages Vd1 and Vd2 data capacitance differential pressure delta V_Cb

Pixel unit PU (m, n) high logic level H

Ta, Tb in low logic level L data receiving period

Common data line DATcm Red pixel circuit PCR (m, n)

Red light emitting diode LEDr red selection circuit SCr

Select transistors Sr1, Sr2, Sg1, Sg2, Sb1, Sb2

Green pixel circuit PCg (m, n) blue pixel circuit PCb (m, n)

Green light emitting diode LEDg green selection circuit SCg

Blue light emitting diode LEDb blue selection circuit SCb

Red multiplex signals MUXr1, MUXr2

Green multiplex signals MUXg1 and MUXg2

Blue multiplex signals MUXb1, MUXb2

Red data voltages Vd1r, Vd2r, green data voltages Vd1g, Vd2g

Blue data voltages Vd1b, Vd2b Red pixel data line DATr [ m ]

Green pixel data line DATg m and blue pixel data line DATb m

Sub-data reception periods Ta1, Ta2, Ta3, Tb1, Tb2, Tb3

Detailed Description

As described above, the threshold value of the data voltage transmitted by the pixel data line cannot be too high due to the timing controller. In conjunction, the magnitude of the driving current for driving the led is also affected, and the brightness adjustment range of the led is limited accordingly. Therefore, the pixel circuit of the present invention receives the data voltages Vd1 and Vd2 in the two data receiving periods Ta and Tb, respectively, and further generates the pixel driving voltage Vdis required for driving the light emitting diode at the control node Nc.

Please refer to fig. 2, which is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure. The pixel circuits PC (M, N) in the mth row and nth column in the figure are exemplified, where M is 1 to M3, and N is 1 to N. The pixel circuit PC (m, n) is electrically connected to the pixel data lines DAT [ m ], the gate lines GL [ n-1], GL [ n ]. The pixel circuit PC (m, n) includes: a light emitting diode LED, a driving transistor TFT, switching transistors M1, M2, M3, and a data capacitor (boosting capacitor) Cb. In addition, the pixel circuit PC (m, n) may further optionally include a voltage stabilization capacitor Cs electrically connected to the control node Nc and the driving transistor TFT. The light emitting diode LED may be a micro light emitting diode display (micro LED) or a sub-millimeter light emitting diode (mini LED).

The light emitting diode LED receives a supply voltage Vdd. The driving transistor TFT is electrically connected to the control node Nc, the light emitting diode LED, and a low voltage source (e.g., Vss). The driving transistor TFT is turned on or off depending on the voltage of the control node Nc. When the driving transistor TFT is turned on, the light emitting diode LED emits light. The switching transistor M1 is electrically connected to the control node Nc, the gate line GL [ n-1] and the pixel data line DAT [ M ]. The switching transistor M2 is electrically connected to the bias node Nb, the gate line GL [ n-1] and a low voltage source. The switching transistor M3 is electrically connected to the bias node Nb, the gate line GL [ n ], and the pixel data line DAT [ M ]. The switching transistors M1, M2 are selectively enabled by being controlled by the gate line GL [ n-1], and the switching transistor M3 is selectively enabled by being controlled by the gate line GL [ n ].

Since the switching transistors M1 and M2 are controlled by the gate line GL [ n-1], they are turned on simultaneously. When the switching transistor M1 is turned on, the data voltage Vd1 on the pixel data line DAT [ M ] is transmitted to the control node Nc. When the switching transistor M2 is turned on, a low voltage is delivered to the bias node Nb. The operation of the pixel circuit when the switching transistors M1 and M2 are turned on will be described with reference to fig. 4A.

The switching transistor M3 is controlled by the gate line GL [ n ], and the switching transistor M3 is not turned on simultaneously with the switching transistors M1 and M2. When the switching transistor M3 is turned on, the data voltage Vd2 received via the pixel data line DAT [ M ] will be transferred to the bias node Nb. The operation of the pixel circuit when the switching transistor M3 is turned on will be described with reference to fig. 4B.

Since the gate signals are sent to the pixel circuits of each row selected for display, the high logic levels of the gate signals GL [1] GL [ N ] are generated in a sequential manner. Herein, a period in which the gate signal GL [ n-1] is at the high logic level (H) is defined as a data reception period Ta; the period during which the gate signal GL [ n ] is at the high logic level (H) is defined as a data reception period Tb. In addition, the gate signal GL [ n-1] is maintained at a low logic level (L) during the data reception period Tb, and the gate signal GL [ n ] is maintained at a low logic level (L) during the data reception period Ta.

In this context, it is assumed that the switching transistors M1, M2, M3 are all NMOS transistors, and thus, if the gate lines GL [ n-1], GL [ n ] connected to the switching transistors M1, M2, M3 are at the high logic level (H), the switching transistors M1, M2, M3 will be turned on. However, if the switching transistors M1, M2, M3 are PMOS transistors in different applications, the logic level for turning on received by the switching transistors M1, M2, M3 via the gate lines GL [ n-1], GL [ n ] will be a low logic level (L). The type of switching transistor and the logic level used to control it may vary depending on the application and is not described in detail herein.

Please refer to fig. 3, which is a schematic diagram of a pixel circuit according to another embodiment of the present disclosure. The architecture and connections of this embodiment are substantially similar to the embodiment of fig. 2. The difference between fig. 2 and fig. 3 is that the source of the low voltage received by the source of the switching transistor M2 is different. In fig. 2, the switching transistor M2 receives a low voltage from a common low voltage source; in fig. 3, the switching transistor M2 receives a low voltage from the independent reference voltage source Vref.

Since the display panel includes a large number of pixel circuits, a resistance may be generated in each wiring. As the number of pixel circuits increases, the stability of the low voltage may also be affected by the current flowing through the resistance on the wiring. Therefore, when the low voltage is provided by the independent reference voltage source Vref, the level of the low voltage received by the switching transistor M2 can be ensured to be more accurate.

Please refer to fig. 4A, which is a schematic diagram illustrating an operation of the pixel circuit in the data receiving period Ta according to an embodiment of the present invention. In the data receiving period Ta, the gate line GL [ n-1] is at a high logic level (H), the gate line GL [ n ] is at a low logic level (L), and the pixel data line DAT [ m ] transmits a data voltage Vd 1. At this time, the switching transistors M1, M2 are turned on; the switching transistor M3 is off.

Please refer to fig. 4B, which is a schematic diagram illustrating an operation situation of the pixel circuit Tb during data receiving according to an embodiment of the present invention. In the data receiving period Tb, the gate line GL [ n ] is at a high logic level (H), the gate line GL [ n-1] is at a low logic level (L), and the pixel data line DAT [ m ] transmits a data voltage Vd 2. At this time, the switching transistors M1, M2 are off; the switching transistor M3 is on.

After the data receiving period Ta, a data capacitor voltage difference delta V exists between the two ends of the data capacitor Cb_Cb(wherein. DELTA.V_CbVd 1-Vss). Then, during the data receiving period Tb, the bias node Nb is equal to the pixel data line DAT [ M ] because the switching transistor M3 is turned on]The transferred data voltage Vd 2. At this time, the voltage of the control node Nc is equal to the sum of the data voltage Vd2 and the voltage difference between both ends of the data capacitor Cb, that is,

that is, during the data receiving period Tb, the voltage of the control node Nc is greater than the data voltage Vd2, which in turn causes the driving transistor TFT to provide a larger driving current i_d。

Accordingly, during the data receiving period Tb, the voltage of the control node Nc is not only equal to the data voltage Vd2, but is further increased

That is, in the data receiving period Tb, the pixel driving voltage Vdis is generated according to the data capacitor Cb, the stabilizing capacitor Cs and the data voltages Vd1 and Vd 2. Let Cb be 4 Cs, and Vd1 be Vd2 be 6V. Then, according to a simulation result, the supplied pixel driving voltage Vdis of the control node Nc is 10.2V. In other words, the pixel driving voltage Vdis may be greater than the data voltages Vd1, Vd 2.

According to the invention, the capacitance of the stabilizing capacitor Cs is smaller than the capacitance of the data capacitor Cb. If the capacitance of the data capacitor Cb is much larger than that of the stabilizing capacitor Cs, the voltage of the control node Nc during the data receiving period Tb is equivalent to Vd1+ Vd 2. The voltage stabilizing capacitor Cs is used to provide a voltage stabilizing function, but the data capacitor Cb may also provide a voltage stabilizing function. Alternatively, a parasitic capacitance between the gate and the source of the driving transistor TFT may be used as the voltage stabilizing capacitance Cs.

In the data receiving period Tb, the driving transistor is turned on according to the voltage of the control node Nc, thereby generating a driving current i for driving the light emitting diode LED_d. In this embodiment, the voltage at the control node Nc is raised from Vd1 to

In conjunction with the driving current i generated by the driving transistor TFT_dAnd also with the increase.

Please refer to fig. 5, which is a waveform diagram related to the operation of the pixel circuit according to the embodiment of the invention. The waveforms shown in this figure are from top to bottom: a voltage change of the bias node Nb, a voltage change of the control node Nc, a voltage change of the pixel data line, and a voltage change of the gate lines GL [ n-1], GL [ n ].

Please refer to fig. 4A and fig. 5 for the data receiving period Ta. The switching transistors M1, M2 are turned on in response to the gate signal GL [ n-1] of high logic level (H) during the data receiving period Ta. Among them, the switching transistor M1 transmits the data voltage Vd1 received via the pixel data line DAT [ M ] to the control node Nc. On the other hand, the switching transistor M2 transmits the low voltage to the bias node Nb.

Please refer to fig. 4B and fig. 5 for the data reception period Tb simultaneously. The data reception period Tb follows the data reception period Ta.

After the data receiving period Ta is over, the data capacitor Cb generates a data capacitor differential pressure Δ V between the control node Nc and the bias node Nb_Cb. The data capacitor Cb receives the data voltage Vd2 via the switching transistor M3 during the data receiving period Tb and according to the data capacitor voltage difference Δ V_CbAnd the data voltage Vd2, determines the voltage of the control node Nc. Wherein, the data capacitance differential pressure DeltaV_CbIs less than or equal to the pixel driving voltage Vdis corresponding to the light emitting diode.

As described above, the pixel circuit of the present invention achieves the effect of boosting the voltage of the control node Nc in the two data reception periods Ta and Tb. Accordingly, the pixel data line DAT does not need to directly supply a high voltage to the pixel circuit, but Vd1 and Vd2 having a smaller voltage value of the data voltage may be transferred to the pixel circuit PC (m, n) in several times by the function of accumulating charges in the data capacitor Cb. The control method for transmitting the data voltages Vd1 and Vd2 in two data receiving periods Ta and Tb is flexible, and the levels of the data voltages Vd1 and Vd2 can be designed according to different applications.

For example, the following cases may be made in combination of the data voltage Vd1 in the data reception period Ta and the data voltage Vd2 in the data reception period Tb. First, when the voltage of the control node Nc is lower than the pixel driving voltage Vdis after the data receiving period Ta is over, the bias node Nb receives the data voltage Vd2 in the data receiving period Tb, and the voltage of the control node Nc is raised to the pixel driving voltage Vdis. Second, when the voltage of the control node Nc is equal to the pixel driving voltage Vdis after the data receiving period Ta ends, the bias node Nb receives a low voltage during the data receiving period Tb, and the voltage of the control node Vc is maintained. Alternatively, the data voltage Vd1 received during the data reception period Ta is equal to the low voltage, and the data voltage Vd2 received during the data reception period Tb is equal to the pixel driving voltage Vdis.

The pixel circuit adopting the idea of the invention can dynamically provide different pixel driving voltages Vdis according to different colors of the light emitting diodes. For example, for a red light emitting diode with better light emitting efficiency, the data voltage is provided only during one data receiving period (only the data voltage Vd1 or only the data voltage Vd2 is provided), and then the red light emitting diode is driven by the pixel driving voltage Vdis which is lower without being superimposed (Vdis Vd1 or Vd 2); on the other hand, for the green light emitting diode and the blue light emitting diode with poor light emitting efficiency, the data voltages (the data voltage Vd1 and the data voltage Vd2) are provided in both data receiving periods, so that the superimposed pixel driving voltages are higher

Driving it. Therefore, even though the light emitting diodes of different colors have different light emitting efficiencies, the pixel circuits of different colors of the display panel adopting the idea of the invention can still emit equivalent brightness aiming at the same gray-scale value.

In practical applications, the two data receiving periods Ta and Tb may be used to provide the data voltages Vd1 and Vd2 according to different considerations. When the electronic product may be used indoors or outdoors, the electronic product may provide an indoor mode (indoor mode) and an outdoor mode (outdoor mode), and the display panel may adopt different driving modes according to the modes.

In the outdoor mode, the display of the display panel is easily affected by ambient light. That is, if the ambient light is too strong, the user cannot see the display. Therefore, the display panel needs to use higher luminance for the application in the outdoor mode. At this time, the voltage of the control node Nc may be increased by supplying the data voltage to the outdoor mode in two data reception periods Ta and Tb. Accordingly, the current i is driven_dIt will become larger and the LED will emit brighter brightness.

On the other hand, in the indoor mode, the data voltage is supplied using only one of the data receiving periods. For example, the data voltage supplied during the data reception period Ta is equal to the low voltage Vd1 — Vss, and the data voltage supplied during the data reception period Tb is equal to the pixel driving voltage Vd2 — Vdis. Since the voltage of the control node Nc is not affected by the voltage Vss of the bias node Nb during the data receiving period Ta, the control node Nc will remain equal to the data voltage Vd 2. That is, the voltage of the control node Nc is adjusted only in the data reception period Tb. Alternatively, the data voltage supplied during the data reception period Ta is equal to the pixel driving voltage Vd1 — Vdis, and the data voltage supplied during the data reception period Tb is equal to the low voltage Vd2 — Vss. That is, the voltage of the control node Nc is adjusted only in the data reception period Ta. Since the voltage of the control node Nc is not affected by the low voltage Vss of the bias node Nb during the data receiving period Tb, the control node Nc will remain equal to the data voltage Vd 1. When the driving mode is adopted, the control nodeThe voltage of Nc is low. Accordingly, the pixel circuit uses a smaller driving current i_dThe LED is driven, the brightness of the LED is low, and electricity is saved.

Please refer to fig. 6, which is a diagram of a pixel unit according to an embodiment of the invention. The pixel unit PU (m, n) includes a red pixel circuit PCr (m, n), a green pixel circuit PCg (m, n), and a blue pixel circuit PCb (m, n). The red pixel circuit PCr (m, n) and the green pixel circuit PCg (m, n) are similar to the blue pixel circuit PCb (m, n), and the difference is that the leds in the pixel circuits are the red led LEDr, the green led LEDg, and the blue led LEDb, respectively.

In the red pixel circuit PCr (m, n), the driving transistor TFTr supplies a driving current i required to drive the red light emitting diode LEDr to emit light_dr(ii) a In the green pixel circuit PCg (m, n), the driving transistor TFTg supplies a driving current i required to drive the green light emitting diode LEDg to emit light_dg(ii) a In the blue pixel circuit PCb (m, n), the driving transistor TFTb supplies a driving current i required to drive the blue light emitting diode LEDb to emit light_db. Each pixel circuit corresponds to a Selection Circuit (SC). That is, the red pixel circuit PCr (m, n) corresponds to the red selection circuit SCr; the green pixel circuit PCr (m, n) corresponds to the green selection circuit SCg; and, the blue pixel circuit PCr (m, n) corresponds to the blue selection circuit SCb.

The red selection circuit SCr corresponding to the red pixel circuit PCr (m, n) includes selection transistors Sr1, Sr 2. The select transistors Sr1, Sr2 are electrically connected to the common data line DATcm and the red pixel data line DATr [ m ]. The select transistor Sr1 is controlled by the red multiplexed signal MUXr 1; the select transistor Sr2 is controlled by the red multiplexed signal MUXr 2. When any one of the select transistors Sr1, Sr2 is turned on, the data voltage transmitted by the common data line DATcm will be transmitted to the red pixel data line DATr [ m ]. The select transistors Sr1, Sr2 are not turned on simultaneously.

The green selection circuit SCg corresponding to the green pixel circuit PCg (m, n) includes selection transistors Sg1, Sg 2. The select transistors Sg1 and Sg2 are electrically connected to the common data line DATcm and the green pixel data line DATg [ m ]. The select transistor Sg1 is controlled by a green multiplex signal MUXg 1; the select transistor Sg2 is controlled by the green multiplex signal MUXg 2. When any one of the select transistors Sg1, Sg2 is turned on, the data voltage transferred by the common data line DATcm will be transferred to the green pixel data line DATg [ m ]. The select transistors Sg1 and Sg2 are not turned on simultaneously.

The blue selection circuit SCb corresponding to the blue pixel circuit PCb (m, n) includes selection transistors Sb1, Sb 2. The select transistors Sb1, Sb2 are electrically connected to the common data line DATcm and the blue pixel data line DATb [ m ]. The select transistor Sb1 is controlled by the blue multiplex signal MUXb 1; the select transistor Sb2 is controlled by the blue multiplex signal MUXb 2. When any one of the selection transistors Sb1, Sb2 is turned on, the data voltage transmitted by the common data line DATcm will be transmitted to the blue pixel data line DATb [ m ]. The select transistors Sb1 and Sb2 are not turned on at the same time.

Please refer to fig. 7, which is a waveform diagram related to the operation of the pixel unit according to the embodiment of the invention. Fig. 7 shows, from top to bottom, a clock signal CLK, an inverted clock signal XCK, gate signals GL [ n-1], GL [ n +1], a voltage of the control node Ncr, a voltage of the control node Ncg, a voltage of the control node Ncb, red multiplexing signals MUXr1, MUXr2, green multiplexing signals MUXg1, MUXg2, blue multiplexing signals MUXb1, MUXb2, and a common data line dactm, respectively. The red multiplexing signals MUXr1, MUXr2, green multiplexing signals MUXg1, MUXg2, blue multiplexing signals MUXb1 and MUXb2 can be sent from the timing controller. The multiplex signal can save the number of pins required by the time schedule controller to output to the display panel.

In FIG. 7, it is assumed that the period in which the gate signal GL [ n-1] is at the high logic level corresponds to the high logic level period of the clock signal CLK (defined as the data reception period Ta); the period in which the gate signal GL [ n ] is at the high logic level corresponds to the low logic level period (defined as the data reception period Tb) of the clock signal CLK. The data reception period Ta is further divided into sub-data reception periods Ta1, Ta2, and Ta3 corresponding to the red pixel circuit PCr (m, n), the green pixel circuit PCg (m, n), and the blue pixel circuit PCb (m, n), respectively; the data reception period Tb is further divided into sub-data reception periods Tb1, Tb2, Tb3 corresponding to the red pixel circuit PCr (m, n), the green pixel circuit PCg (m, n), and the blue pixel circuit PCb (m, n), respectively. Please refer to fig. 6 and fig. 7 simultaneously.

In the sub data receiving period Ta1, the selection transistor Sr1 is turned on because the red multiplexing signal MUXr1 is at a high logic level. At this time, the common data line DATcm transfers the data voltage Vd1r corresponding to the red pixel circuit PCr (m, n), and the data voltage Vd1r is transferred to the red pixel data line DATr [ m ]. At the same time, the switching transistors M1r, M2r in the red pixel circuit PCR (M, n) are turned on because the gate signal GL [ n-1] is at a high logic level. Therefore, the bias node Nbr is equal to a low voltage during the sub data reception period Ta 1; and the control node Ncr is equal to the voltage of the red pixel data line DATr [ m ] (i.e., the red data voltage Vd1r) during the sub data receiving period Ta 1. In conjunction, the voltage of the control node Ncr rises from the sub data receiving period Ta1 to the red data voltage Vd1 r. In addition, the data capacitor Cbr is also charged according to the red data voltage Vd1r during the sub data receiving period Ta 1.

In the sub data receiving period Ta2, the selection transistor Sg1 is turned on because the green multiplexing signal MUXg1 is at a high logic level. At this time, the common data line DATcm transfers the data voltage Vd1g corresponding to the green pixel circuit PCg (m, n), and the data voltage Vd1g is transferred to the green pixel data line DATg [ m ]. At the same time, the switching transistors M1g, M2g in the green pixel circuit PCg (M, n) are turned on because the gate signal GL [ n-1] is at a high logic level. Therefore, the bias node Nbg is equal to a low voltage during the sub data reception period Ta 2; and the control node Ncg is equal to the voltage of the green pixel data line DATg [ m ] (i.e., the data voltage Vd1g) during the sub data receiving period Ta 2. In conjunction, the voltage of the control node Ncg rises from the sub data receiving period Ta2 to the data voltage Vd1 g. In addition, the data capacitor Cbg is also charged according to the green data voltage Vd1g during the sub data receiving period Ta 2.

In the sub data receiving period Ta3, the select transistor Sb1 is turned on because the blue multiplexing signal MUXb1 is at a high logic level. At this time, the common data line DATcm transfers the data voltage Vd1b corresponding to the blue pixel circuit PCb (m, n), and the data voltage Vd1b is transferred to the blue pixel data line DATb [ m ]. At the same time, the switching transistors M1b, M2b in the blue pixel circuit PCb (M, n) are turned on because the gate signal GL [ n-1] is at a high logic level. Therefore, the bias voltage node Nbb is equal to Ta2 low during sub data reception; and the control node Ncb is equal to the voltage of the blue pixel data line DATb [ m ] (i.e., the data voltage Vd1b) during the sub data receiving period Ta 3. In conjunction, the voltage of the control node Ncb rises from the sub data receiving period Ta3 to the data voltage Vd1 b. In addition, the data capacitance Cbb is also charged according to the blue data voltage Vd1b during the sub data receiving period Ta 3.

As can be seen from the foregoing description, although the switching transistors M1r and M2r in the red pixel circuit PCr (M, n), the switching transistors M1g and M2g in the green pixel circuit PCg (M, n), and the switching transistors M1b and M2b in the blue pixel circuit PCb (M, n) are all kept on during the data receiving period Ta, the pixel circuits actually receiving the data voltages from the common data line DATcm are not the same during the sub-data receiving periods Ta1, Ta2, and Ta3 due to the red multiplexing signal MUXr1, the green multiplexing signal MUXg1, and the blue multiplexing signal MUXb 1.

In the sub data receiving period Ta1, only the control node Ncr receives the red data voltage Vd1r transmitted through the common data line DATcm via the turned-on selection transistor Sr1 and the red pixel data line DATr [ m ]. In the sub data receiving period Ta2, only the control node Ncg receives the green data voltage Vd1g transferred from the common data line DATcm via the turned-on selection transistor Sg1 and the green pixel data line DATg [ m ]. In the sub data receiving period Ta3, only the control node Ncb receives the blue data voltage Vd1b transferred to the common data line DATcm via the turned-on selection transistor Sb1 and the blue pixel data line DATb [ m ].

In the sub data receiving period Tb1, the selection transistor Sr2 is turned on due to the high logic level of the red multiplexing signal MUXr 2. At this time, the common data line DATcm transfers the data voltage Vd2r corresponding to the red pixel circuit PCr (m, n), and the data voltage Vd2r is transferred to the red pixel circuit PCr (m, n)Pixel data line DATr [ m ]]. At the same time, the switching transistor M3r of the red pixel circuit PCRs (M, n) is also driven by the gate signal GL [ n ]]Is turned on due to the high logic level. Therefore, the voltage of the bias node Nbr is equal to the red data voltage Vd2r during the sub data receiving period Tb 1; and the pixel driving voltage Vdis of the control node Ncr supplied to the driving transistor TFTr during the sub data reception period Tb1 is equal to

In the sub data receiving period Tb2, the selection transistor Sg2 is turned on because the green multiplexing signal MUXg2 is at a high logic level. At this time, the common data line DATcm transfers the green data voltage Vd2g corresponding to the green pixel circuit PCg (m, n), and the green data voltage Vd2g is transferred to the green pixel data line DATg [ m [ ]]. At the same time, the switching transistor M3g of the green pixel circuit PCg (M, n) is also driven by the gate signal GL [ n ]]Is turned on due to the high logic level. Therefore, the voltage of the bias node Nbg is equal to the green data voltage Vd2g during the sub data receiving period Tb 2; and the pixel driving voltage Vdis supplied from the control node Ncg to the driving transistor TFTg during the sub data reception period Tb2 is equal to

In the sub data receiving period Tb3, the select transistor Sb2 is turned on because the blue multiplexing signal MUXb2 is at a high logic level. At this time, the common data line DATcm transmits the blue data voltage Vdb2 corresponding to the blue pixel circuit PCb (m, n), and the blue data voltage Vdb2 is transmitted to the blue pixel data line DATb [ m [ ]]. At the same time, the switching transistor M3b of the blue pixel circuit PCb (M, n) is also driven by the gate signal GL [ n ]]Is turned on due to the high logic level. Therefore, the voltage of the bias node Nbb is equal to the blue data voltage Vd2b during the sub data receiving period Tb 3; and the pixel driving voltage Vdis of the control node Ncb supplied to the driving transistor TFTb during the sub data reception period Tb3 is equal to

The pixel circuit and the driving method according to the present invention have many advantages. In addition to the above, the timing controller and the data driving circuit need not be implemented by high voltage tolerant chips, and the data voltage control during one or two data receiving periods can be provided for different applications, which can greatly reduce the area required by the pixel circuit and improve the resolution of gray scales.

With the pixel circuit of the related art as shown in fig. 1, the width-to-length ratio (W/L) of the driving transistor TFT in the red pixel circuit is about 160/4 μm; the width-to-length ratio (W/L) of the driving transistor TFT in the green and blue pixel circuits is about 45 μm/4 μm. When the pixel circuit of the embodiment of the invention is adopted, the width-to-length ratio of the driving transistor TFT in the pixel circuit of red, green or blue can be reduced to 2.5 μm/2.5 μm.

Accordingly, it is apparent that the area required by the driving transistor and the switching transistor is greatly reduced when the pixel circuit and the driving method of the embodiment of the invention are adopted. Even though the number of transistors required by the embodiment of the present invention is slightly larger than that of fig. 1, the area required by the embodiment of the present invention is still much smaller than that of the pixel circuit of the prior art in terms of the area required by the pixel circuit.

Furthermore, the current display gray scale usually has a resolution of 8 bits. If the amplitude of the data voltage receivable by the control node Nc increases, the gray scale resolution can be further improved. For example, gray scale may be represented by 12 bits or 16 bits. Accordingly, the display quality of the display panel can be improved.

While the present invention has been described with reference to the above embodiments, it is not intended to be limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention is subject to the claims.

Claims

1. A pixel circuit electrically connected to a pixel data line, a first gate line and a second gate line, wherein the first gate line and the second gate line respectively transmit a first gate signal and a second gate signal, the pixel circuit comprising:

a light emitting diode;

a driving transistor, electrically connected to a control node and the light emitting diode, for receiving a low voltage;

a first switching transistor electrically connected to the control node, the first gate line and the pixel data line, and turned on during a first data receiving period according to the first gate signal to transmit a first data voltage on the pixel data line to the control node;

a second switching transistor electrically connected to the first gate line and a bias node, receiving the low voltage, and turned on in the first data receiving period according to the first gate signal, thereby transmitting the low voltage to the bias node;

a third switching transistor electrically connected to the bias node, the second gate line and the pixel data line, and turned on during a second data receiving period according to the second gate signal to transmit a second data voltage on the pixel data line to the bias node; and

a data capacitor electrically connected to the control node and the bias node for generating a data capacitor voltage difference during the first data receiving period, and for generating a pixel driving voltage corresponding to the brightness of the light emitting diode at the control node according to the data capacitor voltage difference during the second data receiving period, wherein the second data receiving period is after the first data receiving period.

2. A pixel circuit as claimed in claim 1, wherein the data capacitance voltage difference is equal to the first data voltage.

3. The pixel circuit according to claim 1, wherein the driving transistor is turned on according to the pixel driving voltage during the second data receiving period, thereby generating a driving current flowing through the light emitting diode.

4. A pixel circuit as claimed in claim 1, wherein the data capacitance voltage difference is less than or equal to the pixel drive voltage.

5. The pixel circuit of claim 1, wherein the first gate signal is at a first logic level during the first data receiving period and at a second logic level during the second data receiving period, and the second gate signal is at the second logic level during the first data receiving period and at the first logic level during the second data receiving period, wherein the first logic level is not equal to the second logic level.

6. The pixel circuit of claim 1, wherein the width and length of the driving transistor are 2.5 microns, and the width and length of the first, second and third switching transistors are 2.5 microns, wherein the light emitting diode is a red light emitting diode, a green light emitting diode or a blue light emitting diode.

7. The pixel circuit of claim 1, further comprising:

and a voltage stabilizing capacitor electrically connected to the control node and the driving transistor, wherein the capacitance of the voltage stabilizing capacitor is smaller than that of the data capacitor.

8. The pixel circuit of claim 7, wherein the pixel driving voltage is determined according to the data capacitor, the voltage-stabilizing capacitor, the first data voltage and the second data voltage.

9. A driving method applied to a pixel circuit, wherein the pixel circuit electrically connected with a pixel data line, a first gate line and a second gate line comprises a light emitting diode, a driving transistor, a first switching transistor, a second switching transistor, a third switching transistor and a data capacitor, the driving method comprises the following steps:

the driving transistor receives a low voltage;

the first gate line and the second gate line respectively transmit a first gate signal and a second gate signal;

the first switching transistor is conducted in a first data receiving period according to the first grid signal, and further transmits a first data voltage on the pixel data line to a control node;

the second switching transistor is turned on during the first data receiving period according to the first gate signal, thereby transmitting the low voltage to a bias node;

the third switching transistor is turned on during a second data receiving period according to the second gate signal, thereby transmitting a second data voltage on the pixel data line to the bias node; and

the data capacitor generates a data capacitor voltage difference in the first data receiving period, and generates a pixel driving voltage corresponding to the brightness of the light emitting diode at the control node according to the data capacitor voltage difference in the second data receiving period.

10. The driving method as claimed in claim 9, wherein the second data receiving period is after the first data receiving period, and the data capacitor voltage difference is equal to the first data voltage.

11. The driving method according to claim 9, further comprising the steps of:

the driving transistor is conducted according to the pixel driving voltage in the second data receiving period, and further generates a driving current flowing through the light emitting diode.