CN1003274B - Scanning conversion method and scan converter unit employing the conversion method - Google Patents

Abstract

The present invention relates to a scanning converting method which has an aim to convert interlaced scanning video signals of 2 to 1 to line-by-line scanning system video signals, wherein the interlaced scanning video signals of 2 to 1 are composed of (2N+1)/2 scanning lines (N is a positive integer). A storage device (23) has addresses corresponding to N+1 scanning lines, the addresses of the storage device (23) used for the N+1 scanning lines are circulated, and therefore, the interlaced scanning video signals are written in the address one by one. Simultaneously, the signals are repeatedly read out twice from the addresses where the signals are written in at a speed twice of a writing speed.

Description

Scan conversion method and adopt the scan conversion apparatus of this scan conversion method

The present invention relates to a kind of scan conversion method, be used for the TV signal of interlaced scanning system transmission is converted to the TV signal of progressive-scan system.The invention still further relates to a kind of device that adopts this method.Further say, the present invention relates to a kind of method and apparatus that 2: 1 interlaced scanning systems is converted to progressive-scan system.

In order to eliminate the various influences such as the line flicker that causes by interlaced scanning system, so that image quality is comprehensively improved, convert the device of the television video frequency signal of progressive-scan system to for television video frequency signal with interlaced scanning system, in this technical field, narrate.

For example, in NTSC(NTSC) in the system television signal, transmit the field duration signal of 262.5 scan lines with interlacing scan in per 1/60 second, be equivalent to a frame image of 525 scan lines of two fields with formation.In other words, constituted each vision signal of different in per 1/60 second, therefore during 1/30 second, form a frame image scan conversion apparatus and be used for timing place in appointment, Xin And reads this signal between the field duration of storage transmission, thereby will constitute the vision signal of two fields of a frame, be converted to the scanning that carries out from interlacing scan.Like this, reproduced high-quality image, this visual field frequencies range is identical with interlaced scanning system, and its scan line quantity then is the twice of interlaced scanning system.

Fig. 1 is a block diagram, the formation of the scan conversion apparatus that expression is commonly used.Incoming video signal is carried out counting the sonization processing provisionally so that carry out " writing " and " reading " operation with a kind of like this scan conversion apparatus, thereby original input signal is regenerated as same analog signal in the moment of appointment.

Referring to Fig. 1, the incoming video signal behind the video detection of 2: 1 interlaced scanning systems is input to mould-number (A-D) transducer 2, it is converted to digital signal, then it " is write " to go in the memory 3 that is made of semiconductor memory etc.This memory 3 has " writing " and goes into to import some times of data and continue the time that " reading " goes out to write data by the time partitioning scheme.The digital signal of going into by " writing " and " reading " goes out regularly conversion and constitute, output in turn from memory 3.Again the digital signal of " reading " to go out is input to number-Mo (D-A) transducer 4 from memory 3, convert it to analog video signal 5 again, and, control each timing of A-D transducer, memory 3 and D-A transducer with a timing generator 6 display unit (not drawing among the figure) such as this analog video signal supply CRT.

Although the block diagram of expression common structure is just explained a signal system, and may be only the black and white television receiver of such circuit application to the processing luminance signal, but handling a plurality of signals that constitute by luminance signal and color difference signal, or handle and on color TV set, use each primary colour signal of desired red, green and blue, then must be circuit application shown in Figure 1 to each signal system.

Now by Fig. 1 and Fig. 2, the work of above-mentioned scan conversion apparatus commonly used is scanned.

Fig. 2 is one and is used for explaining that memory 3 " is write " and the diagram of " reading " signal timing.The numeral 7 on Fig. 2 top is represented the video waveform with interlaced scanning system transmission in 2: 1, and the waveform of the vertical scanning electric current in the numeral 8 expression interlacing scans below it.Fig. 2 below is depicted as regularly, regularly locates at these, and memory 3 is carried out " writing " and " reading " of signal respectively for above-mentioned waveform 7 and 8.

As shown in Figure 2, in the operation timing of memory 3, abscissa express time and ordinate is represented the memory address of memory 3, discontinuous ladder solid line 9 expression memories 3 " writing " regularly, and dotted line 10 expression memories 3 " reading " regularly continuously.In addition, symbol 1H represents a horizontal scanning interval in the interlacing scan, and symbol 1V represents a vertical scan intervals in the interlacing scan, a horizontal scanning interval during symbol 1H ' expression is lined by line scan.According to Fig. 2, can recognize clearly that vertical scan intervals 1V is the same in interlacing and the scanning system that carries out, and a horizontal scanning interval 1H ' in the scanning system that carries out is half of horizontal scanning interval in the interlaced scanning system.

In Fig. 2, select the ratio of horizontal scanning interval and vertical scan intervals as 1: 7.5 as for convenience of explanation.Therefore, in this case, 15 scan lines have formed one two picture frame (frame).

When " writing " when going into memory 3 vision signal 7 of the middle transmission of a particular field (for example field on the left side among the figure), the signal of a scan line " is write " address of going into an appointment, and be empty for the next address of scan line, so the vision signal 7 of next bar scan line " is write " to go into wherein, this " writing " operation is carried out repeatedly.When the vision signal 7 of a field " is write " go into after, the vision signal 7 of these scan lines is one after the other write the address blank on (shown in the right of Fig. 2) in back to back, this address blank does not have signal " to write " every delegation in previous.

The vision signal 7 that writes with preceding method, go into speed and continue " reading " according to sequence of addresses and go out (in Fig. 2 to double " writing ", the slope of expression " reading " dotted line 10 regularly is twices of the slope of expression " writing " solid line 9 regularly, therefore, can think that " reading " speed is the twice of " writing " speed).As mentioned above, the timing of this " writing " and " reading " is by regularly believing signal generator 6 supplies.

Let us considers during " writing ", in the horizontal scanning interval in the particular field of interleaved vision signal 7, and the working condition of memory 3.A in sweep spacing A ₁-a ₂During this time in (during a ₁-a ₂Be sweep spacing A the first half) " reading " be to write address AD a ₁-ADa ₂Signal, write ADa ₁-ADa ₂Signal be such signal, it is by ADa ₁-ADa ₂The signal of part in during pointed writing extended on the left side promptly is the vision signal of B during the 1H in previous.

Further, the second half a of sweep spacing A ₂-a ₃In " reading " go out is that now " writing " goes into the vision signal of A during the 1H among the A at interval.

Therefore, among the 1H time quantum, alternately arrange, just formed the vision signal of a field of from memory 3, reading by vision signal to two continuous fields.So by identical with the scanning system that carries out this vertical scanning frequency, and horizontal frequency is presented on the display of CRT and so on for the signal of its twice, the scanning picture reproducing just can carry out.In other words, in the example of this prior art, be in one, to have reproduced the image that forms by 15 scan lines every scan method continuously.Thereby, converted interlaced scanning system to progressive-scan system.

In the narration in front, for ease of explanation, the ratio of choosing horizontal scanning interval and perpendicular separation is 1: 7.5, therefore, when converting progressive-scan system to, 15 scan lines will be arranged in one.Should be noted that in existing NTSC system, the horizontal scanning interval is to that is to say when converting progressive-scan system at 1: 262.5 to the ratio of vertical scan intervals, the scan line in is 525.

Although described is a signal minimum unit that writes and read in horizontal scanning interval, in same memory 3, carry out the write and read of signal simultaneously, in fact this operation is to carry out in the mode that the time is cut apart.

In the example of above-mentioned prior art, as shown in Figure 2, memory 3 requires to have X-X ' address, in more detail, for by writing the vision signal of a scan line, and, write next address in turn with vision signal with next scan line by the address that the signal of vacating a scan line can write, thereby the vision signal of a field is write, so the address sum that requires should be the twice that can store the address of a vision signal.Memory 3 desired capacity should be able to be stored two (frame) vision signals.

In explanation to scan converter shown in Figure 1, suppose in A-D transducer 2,910 sub-samplings to have been carried out in a horizontal scanning interval, the frequency of i.e. this sampling is four times of colored carrier frequency in the vitascan, and in the NTSC video signal system, formed a pixel by 8 information, by the amount of information P that deposited in be as a frame:

P=910 * 525 * 8=467KB(byte)

In view of the above, require the information of memory 3 storage huge amounts.

Therefore, when memory 3 was made into extensive assembly, the cost that is spent also increased thereupon, and memory 3 occupied spaces also increase with the setting of scan converter.

An object of the present invention is to provide a kind of scan conversion method, this method can reduce the capacity of the needed memory of storage conversion.

Another object of the present invention is to provide a kind of conversion equipment of small scanning cheaply by the memory that uses low capacity.

In brief, the invention provides a kind of scan conversion method, this method has been prepared a memory, its capacity, only need to store the vision signal of the smallest positive integral bar scan line bigger than the number of scanning lines that forms a field of interlacing scan, so that the method with circulation " is write the interlaced scanning system vision signal " each address of going into memory one by one, and in " writing " process, " reads " to go out the content of address with the speed that doubles " writing ".

In this scan converter provided by the invention, also comprise " writing " and " reading " timing control apparatus of above-mentioned memory.

Therefore, according to the present invention, memory can have such memory capacity, and it can store an about interlaced scanning system vision signal, and needn't resemble and generally require memory can store two vision signals.So, the invention provides a kind of scan conversion method of the memory capacity that can reduce memory and the device that adopts this method.

By with reference to the accompanying drawings to can clearly recognizing in of the present invention being described in detail, to describing and other purpose, characteristic, viewpoint and advantage above of the present invention.

Fig. 1 is the schematic block diagram of expression scan converter structure commonly used;

Fig. 2 is the schematic diagram that is used for explaining " writing " and " reading " timing signal of memory;

Fig. 3 has shown the operation timing of memory in embodiment of the present invention;

Fig. 4 has shown first and second signal waveform of the vision signal of carrying out 2: 1 interleaved NTSC systems;

Fig. 5 shows the state that appears at the scan line on the picture tube by interlacing scan;

Fig. 6 represents signal waveform, is used to explain the work of the memory of embodiment of the present invention;

Fig. 7 is a block diagram, and it shows the structure of embodiment of the present invention;

The block diagram of Fig. 8 shows the structure of second embodiment of the present invention;

Fig. 9 shows when the vision signal input of interlaced scanning system transmission in 2: 1 of standard, according to the work timing of the second embodiment memory of the present invention;

Figure 10 represents when the vision signal input of interlaced scanning system transmission in non-standard 2: 1, according to the work timing of the second embodiment memory of the present invention;

Figure 11 is a block diagram, and it shows the detailed formation according to the control circuit of third embodiment of the invention;

Figure 12 is a timing diagram, when it shows the input of modular system vision signal, and the work of the 3rd embodiment;

Figure 13 is a time diagram, the work of expression the 3rd embodiment when being input as non-standard video signal system;

Figure 14 is a block diagram, and it has shown the structure of the 4th embodiment of the present invention;

Figure 15 is a timing diagram of explaining the 4th embodiment course of work;

Figure 16 shows the signal output waveform of the various piece of the 4th embodiment;

Figure 17 is a block diagram, and it has shown the structure of fifth embodiment of the invention;

Figure 18 is the timing diagram of the course of work of expression the 5th embodiment;

Figure 19 is the block diagram of the structure of expression sixth embodiment of the invention;

Figure 20 and 21 is timing diagrams of the course of work of expression the 6th embodiment.

With reference now to Fig. 3,, to scan conversion method of the present invention, the work of memory control is described when especially implementing this scan conversion method.

Fig. 3 has shown the work timing of first embodiment of the present invention.With reference to figure 3, reference number 7 expressions are by the video waveform of interlacing scan in 2: 1 transmission, and numeral 8 is represented the current waveform of the vertical scanning in the interlacing scans.Below waveform 7 and 8, represented " writing " and " reading " operation timing of memory.That is to say that Fig. 3 shown for video waveform 7 and vertical scanning current waveform 8, memory " is write " and the timing of " reading " signal.In work timing shown in Figure 3, transverse axis express time, the longitudinal axis are represented the memory address of memory, solid line 9 expression memories " writing " regularly, dotted line 10 expression memories " reading " regularly, they are to represent with the form corresponding with the work timing of the memory of prior art shown in Figure 2.

In addition, symbol 1H represents a horizontal scanning interval in the interlaced scanning system, and symbol 1V represents a vertical scan intervals, and the horizontal scanning interval of symbol 1H ' expression in lining by line scan, these symbolic representations are similar to Fig. 2.As shown in Figure 3, the vertical scan intervals 1V in interlacing scan is identical with vertical scan intervals in lining by line scan, and the horizontal scanning interval 1H ' in lining by line scan is half of horizontal scanning interval in the interlacing scan.

In Fig. 3, for convenience of explanation, choosing the horizontal scanning interval is 1: 7.5 to the ratio of vertical scan intervals.So in 2: 1 interlaced scanning systems, a picture frame of being made up of 15 scan lines is formed by two vertical scanning operations (two=1 frame) by two.

(N wherein will be a natural number for the scanning system television video frequency signal that carries out of its twice in order to be converted into the identical and scan line quantity of field frequencies range (being vertical scanning frequency) by two field interlaced scanning system vision signals that (2N+1)/2 scan line forms respectively, in Fig. 3 for 7.5 scanning line selection N=7), in the present embodiment, adopted a memory, it has address (2N+1)/the 2+(1/2)=N+1 of the interlaced scanning system vision signal that can deposit N+1 bar scan line, in Fig. 3, select N=7.In other words, by half memory of the memory capacity memory capacity that is the prior art memory, can finish the scan line conversion.

" writing " of memory and " reading " signal controlling are the addresses of N+1 bar scan line of periodically circulating.As shown in Figure 3, the circulation of this address and vertical deflection cycle 1V And do not match, and the storage address that the specified level sweep spacing signal in each vertical scan intervals is write has a skew that is equivalent to write a 1/2H signal.The control that memory is subjected to is such: when the vision signal in the address that has each bar scan line with the speed twice " reading " that doubles " writing " operation when going out, in each of interlaced scanning system, the signal on each scan line writes these addresses successively.

During twice repetition " read ", what at first " read " was previous the vision signal of the field " write ", and what " read " then is the vision signal of the field " write ".

With reference to figure 3, make a more detailed description.In the operating process of memory, that consider now is horizontal scanning interval A in a particular field.A during in the A of horizontal scanning interval ₁-a ₂In (during a ₁-a ₂The Yi Ban And that is horizontal scanning interval A is corresponding with 1H '), " reading " goes out to write address AD a ₁-ADa ₂Signal.In Fig. 3, the signal that writes in the address is equivalent to ADa ₁-ADa ₂The left-half of line segment and solid line intersect and the solid line part of intercepting, promptly are the vision signals by an indicated scan line of a horizontal scanning interval B in the previous field.In addition, a during another in the A of horizontal scanning interval ₂-a ₃What " read " to go out is the vision signal of a scan line of carrying out the field of " writing " among the A of this horizontal scanning interval.At a ₁-a ₂And a ₂-a ₃Signal during each is read, and all is to carry out with the speed that doubles " writing " operation.

Though signal " is read " and the description of " writing " is " writing " and " reading " side by side to be carried out as minimum unit in a horizontal scanning interval operate in same memory, and in fact this operation is carried out with the time partitioning scheme.

Therefore, by making vertical scanning frequency identical with the vertical scanning frequency maintenance in the interlacing scan, and make horizontal frequency is the twice of horizontal frequency in the interlacing scan, just the video signal information of reading can be converted into the analog signal that can show on the such display of for example CRT.Like this, just the interlaced scanning system picture inversion can be become the image of progressive-scan system.

Here it is according to the characteristic of scan conversion method of the present invention.

So according to the present invention, the memory capacity of memory can be half of prior art memory span.In the comparison below, suppose when the present invention being applied to standard NTSC system that sampling is 910 times in a horizontal scanning interval, and the amount of information of a pixel is 8, then stored amount of information P ' is as follows

P '=910 * 263 * 8=234KB(byte)

Therefore can think that above-mentioned amount of information is half of amount of information 467KB of prior art.

With reference now to Fig. 4, to Fig. 6, when narration applied the present invention to the NTSC system, how correct being converted to lined by line scan.

Fig. 4 shows the signal waveform of carrying out 2: 1 first and second vision signals in the interleaved NTSC system, and symbol VB represents vertical flyback at interval, and the ratio of vertical-scan period with horizontal scanning period is 262.5: 1.

For the ease of narration, signal waveform among Fig. 4 is numbered in the following manner: first the complete horizontal scanning interval that occurs in first vertical flyback at interval is with 1. representing, later on each horizontal scanning interval that occurs in turn is respectively by 2., 3. ... expression is successively used in the horizontal scanning interval that first least significant end and second 's initiating terminal occurs Expression.For second, be right after in the horizontal scanning interval

First complete horizontal scanning interval that the back occurs with 1. ' represent, and later in turn each horizontal scanning interval of appearance successively by 2. ', 3. ' ... expression.In a horizontal scanning interval, front 1., first horizontal scanning interval (promptly being the horizontal scanning interval that occurs at second least significant end) by

' expression.

During the vision signal interlacing scan that Fig. 5 represents to number with said method, appear at the state of the scan line on the picture tube.Say that further Fig. 5 (A) has shown first state, and Fig. 5 (B) has shown second state, Fig. 5 (C) is depicted as the overlapping and state of the frame that forms of first and second.Can see obviously that from Fig. 5 a picture frame is formed by two interlacing scan.

With reference now to Fig. 6,, this situation is described, in this case, memory has storage (N+1)=263(because 262.5=(2N+1)/2) address of this interleaved vision signal of individual execution, thereby so that these addresses of circulating are carried out " writing " and " reading " by means of the described method of Fig. 3 to signal.

Consider the operation of memory, be located in the scan line that label is N or N ' (in Fig. 6, be elected to be into Or

'), the signal of described scan line is written among the appropriate address M of memory.

At first constantly, the signal that writes address M earlier " is read " to go out from memory, in fact this signal is exactly the signal of address M in the previous cycle of memory, promptly is 263 scan lines of vision signal of front.So, when the number of the scan line of writing the now N in first is corresponding, this scan line previous on the scene be second.Each bar scan line of second respectively by 1. '～

' expression.Therefore the vision signal on the scan line (N-1) is read as its result.Vision signal on the scan line N that second moment " reads " to go out from the M of address in scan line N " is write " second " reading " constantly.

Equally, if corresponding at the N ' of " writing " fashionable number of scanning lines in second, then this scan line previous on the scene be first.First scan line respectively by 1.～ Expression, therefore the vision signal on first the scan line N first constantly " writing " go into, and on scan line N ', " write " vision signal of going into second " reading " operating period, go out in second o'clock two moment " being read ".

Therefore, interleaved field at interval in, vision signal from memory with ..., N-1, (N-1) ', N, N ', N+1, (N+1) ' ... order continuously " reading " go out.Vision signal is shown on the display unit of this class of CRT, thereby has formed the scanned picture that carries out that the scan line that this image is had is the twice of scan line in field of interlaced scanning system, shown in Fig. 5 (C) in interval, a field.

With reference now to Fig. 7,, the example of the scan converter of implementing above-mentioned scan conversion method is illustrated.

Fig. 7 is a block diagram, and it shows the structure according to scan converter embodiment of the present invention.

With reference to figure 7, numeral 21 expression mould-number (A-D) transducers, 22 expression Chuan Yi And transducers, 23 expression memories, 24 Biao Shi And-string transducers, 25 expression number-Mo (D-A) transducers, 26 expression synchronizing separator circuits, 27 expression phase-comparison circuits, 28 expression center frequencies of oscillation are the voltage controlled oscillator (VCO) of 28.6MHZ, 29 expression frequency dividing ratios are 1/28 first counter, and 30 expression frequency dividing ratios are 1/65 second counter, and 31 expression frequency dividing ratios are 1/256 the 3rd counter.

Standard NTSC system composite video signal (as shown in Figure 4) from the outside being inputed to A-D transducer 21; And is 4 times of colored carrier frequency in the NTSC system by this frequency of 14.3MHZ(that is obtained by first counter 29) sampling clock quantizes, and inputs to string-And transducer as 8 Bits Serial data 103 then.This input occurs in timing place (this timing signal is identical with sampling clock 102) of timing signal 104.For the general dynamic memory that can use memory 23 etc., string-And transducers 22 have been adopted.So that the operation rate of the speed of input signal and described dynamic memory etc. adapts.The-And transducers 22 of going here and there become 14 pixels (as 8 * 14 capable signals of) De And with 8 Bits Serial conversion of signals of a pixel.Because a kind of like this conversion, the speed of 23 the data of adding to storage is subtracted become a kind of like this low rate

14.3MHZ/14＝1.02MHZ

Thereby enable to use above-mentioned dynamic memory.

The data 108 of having slowed down are added to storage 23, and then, the commutator pulse 105 according to from the 1.02MHZ of first counter 29 adds to storage 23 to the data 108 of having slowed down, and the capacity of this memory is 112 * 16K.By read 107, and be used to specify the address signal 106 of address, come control storage 23 from second counter 30 from first counter 29.Thereby data are write successively the address of regulation.

The data based address signal 106 of write memory 23 and read 107 " are read " to go out, then Gong Gei And-string transducer 24.

When memory carries out " writing " and " reading " operation, for once " writing " operation, carry out twice " reading " operation, this operation was once done to describe in detail therefore no longer explanation here with reference to figure 3 as basic operation of the present invention.

According to timing signal 110 and 111 Tong Guo And-string transducers 24 the capable conversion of signals of And is become serial data 112, timing signal 111 according to 28.6MHZ, again this serial data is converted to analog signal by D-A transducer 25, the frequency of used here timing signal 111 is identical with sampling frequency.Then, this analog signal is added on the display unit (not drawing among the figure) as the scan video signal 113 that carries out, the horizontal frequency of this signal is the twice of the horizontal frequency in the interlacing scan.

On the other hand, composite video signal 101 also has been added to synchronizing separator circuit 26, and it takes out horizontal-drive signal 114 and vertical synchronizing signal 115 successively.Produce for A-D transducer 21 according to synchronizing signal 114 and 115, go here and there-And transducers 22, the timing signal of memory 23 ， And-string transducer 24 and D-A transducer 25, control signal, address signal etc.These will be described in the back.

In more detail, being input to phase comparator circuit 27 by 26 isolated horizontal-drive signals 114 of synchronizing separator circuit.Than mutually, horizontal interval signal 116 wherein is that the 28.6MHZ signal of VCO28 output carries out after the frequency division resulting through first and second counters 29 and 30 to it these input signals 114 and horizontal interval signal 116.The output signal that obtained by comparative result 117 is added to VCO28 as control signal.So phase-comparison circuit 27, VCO28 and first and second counters 29 and 30 have formed a phase-locked loop, make VCO28 become the oscillator that a frequency of oscillation is 28.6MHZ phase place and horizontal-drive signal 114 couplings.Its output as master clock 118 Jia of 28.6MHZ Dao And-string transducer 24, D-A transducer 25 and first counter 29.

The various signals that produced by first counter 29 are added to A-D transducer 21, string-And transducers 22, memory 23 respectively with And-string transducer 24 as control signal.In addition, obtain by the output signal of VCO28 is carried out frequency division from the signal 119 of first counter, 29 outputs, and second counter, 30 output signal frequency are the twice of horizontal-drive signal 114, and the output signal 120 of second counter 30 is supplied with the display unit (not shown) as horizontal-drive signal.

Now, the address signal 106 that adds to storage from second counter 30 and the 3rd counter 31 is described.

The count value of second counter is 65, and by above-mentioned phase-locked loop, makes regularly coupling of the 65th counter horizontal-drive signal 114.In the count range of second counter, low 6 0～63 count values of being counted are supplied with memory 23 as column address.

On the other hand, the 3rd counter provides the row address of memory 23, the vertical synchronizing signal 115 that the 3rd counter 31 receives from synchronizing separator circuit 26 makes 7 horizontal scanning intervals (i.e. 7 countings in the vertical flyback at interval of composite video signal 101) are just stopped its counting operation.Therefore, the 3rd counter 31 is a vertical scan intervals inside counting to 256, thereby 0～256 count value is supplied with the row address of memory 23 as it.So the column address that the row address that is provided by the 3rd counter 31 and second counter provide has just formed address signal 106.

Second counter 30 gets 0～64 as count value, and when count value is " 0 " and " 64 " (at this moment, as mentioned above, 6 column addresss that are used as memory 23 of low level), the signal in the part of a horizontal scanning interval " is write " thus going into identical address causes absence in the read signal.Yet, so absent signal be with composite video signal 101 in horizontal-drive signal or near the corresponding ， And of the signal this signal and it be useless for vision signal.As mentioned above, this is because the 65th counting of second counter 30 and horizontal-drive signal 114 coupling regularly, therefore count value " 0 " or the signal on " 64 " at second counter 30 is exactly at horizontal-drive signal or near the signal this signal, in composite video signal, sort signal is useless for vision signal.

By receiving vertical synchronizing signal 115,7 bit address signals of the 3rd counter output are added to storage 23 as row address signal.But, also be in this case, signal around vertical synchronizing signal is unworthy as vision signal, (that is, although near the signal the vertical synchronizing signal is absent) can not have problems in the vision signal of taking out yet even the signal around vertical synchronizing signal is written into identical address.

Need not many speeches, the absence of this address is used for the memory capacity of memory 23 is reduced to minimum.

According to aforementioned structure, it is to circulate one-period with 263 horizontal scanning intervals that memory 23 is controlled the address that makes it.For this, semiconductor memory etc. are applicable to makes memory 23, and the address NAD that it has is:

NAD＝（65-1）×（263-7）

＝64×256＝16.384＝16K

In this case, the total capacity C of memory 23 is:

C=14 * 8 * 16K(position)

=14 * 16K(byte)

Therefore, memory can be made by the semiconductor memory of 28 4 * 16 kilobits.

So,, convert the interlaced scanning system television video frequency signal to the needed memory span of scanning system signal that carries out can reduce to the usual means capacity half according to the present invention.

Now, the second embodiment of the present invention is illustrated.As mentioned above, the basic principle of second embodiment is identical with the basic principle of previous embodiments.But, in second embodiment, the operation of memory control carried out improving so that be applicable to the variation of vertical scan intervals and the ratio of horizontal scanning interval.

When the modular system of taking according to input signal, when setting the working method of memory unchangeably, (for example, forming a vertical scan intervals by 262.5 horizontal scanning intervals in the NTSC system) then can not carry out good scan conversion for the vision signal of the system except modular system.

On the other hand, except in atmosphere, receiving the device of television video frequency signal, in video-unit, needn't produce the modular system vision signal.For example, on record in the art, by comparing a vertical scan intervals using playback of video signal in the playback at the video tape recorder (F.F. or the slow-motion replay) process that 255～270 horizontal scanning intervals form with modular system.

Therefore, for the signal that scan converter is come with this video tape recorder reaches best fit, the operation control of memory must be applicable to and be scanned-video signal converted.Consider aforesaid this point, second embodiment described later provides a kind of scan conversion apparatus, the scan conversion that it can be finished the non-standard video signal system that departs from modular system.

Briefly, second embodiment comprises and is used for detecting the vertical scan intervals of interlaced scanning system incoming video signal and the device of the ratio of horizontal scanning interval, and according to the device of the memory of suitably control store video information of described ratio.

Now second embodiment is done definite description.

Fig. 8 is a circuit block diagram, represents the structure of second embodiment.Be characterised in that with reference to figure 8, the second embodiments it provides a control circuit 35, this circuit can receive horizontal-drive signal 114 and vertical synchronizing signal 115 from synchronizing separator circuit 36, so that control circuit 35 is by control signal 125 control address generators 36.Other structure of the present embodiment is similar to embodiment shown in Figure 7 basically, And and represent identical structure member and signal with same reference number.

Now structure shown in Figure 8 is briefly described.

To carry out 2: 1 interleaved television video frequency signals by A-D transducer 21 and convert digital signal 103 to, it will be input in the memory 23 that is made of semiconductor storage unit etc.

Similar with embodiment shown in Figure 7.Memory 23 has N address, so that be stored in the signal on the N bar scan line, supposes that N represents greater than the vertical scan intervals of vision signal 101 and the smallest positive integral of the ratio of horizontal scanning interval.By from counter 29(corresponding to first counter 29 Fig. 7) read 107 of coming and from address generator 36(corresponding to second Fig. 7 and the 3rd counter) address signal 106 that comes, come control storage 23 " writing " to go into and " reading " goes out operation.By the D-A transducer data 112 of reading from memory 23 are converted to analog video signal 113, then with the display unit (not shown) of its supply as CRT.

Also incoming video signal 101 has been added to synchronizing separator circuit 26, this circuit takes out horizontal-drive signal 114 and vertical synchronizing signal 115 from vision signal 101.The input of horizontal-drive signal as phase-locked loop (PLL) circuit 37.This phase-locked loop circuit 37 is made of phase comparator 27 and the described VCO28 of Fig. 7.Another input of phase-locked loop circuit 37 receives the inter-sync signal 116 by address generator 36 outputs.Phase-locked loop circuit 37 controlling level synchronizing signals 114 and inter-sync signal 116 are so that they reach each other is complementary, and its output is as the master clock 118 of this system's fundamental clock.

Master clock 118 is added to counter 29, and it exports above-mentioned read 107 successively.And, the signal 119 from counter 29 outputs is added to address generator 36.This address generator 36 produces above-mentioned address signal 106 and inter-sync signal 116 according to signal 119.Address generator 36 also produces horizontal sweep synchronizing signal 120, and this signal 120 is used for flatly scanning outputting video signal it is added to the horizontal scanning circuit of display unit (not shown).Similar with the embodiment of Fig. 7, the frequency of synchronizing signal 120 is twices of inter-sync signal 116 frequencies.

Narrate control circuit 35 now.It is the feature of the present embodiment.Being added to control circuit 35 by synchronizing separator circuit 26 isolated horizontal-drive signals 114 and vertical synchronizing signal 115.This control circuit 35 is added to address generator 36 Bi ， And with signal 125 according to what synchronizing signal 114 and 115 was calculated vertical scan intervals and horizontal scanning interval, so that come the change of the operator scheme of control storage 23 according to this ratio.By signal 125, address generator 36 changes address signal (will describe with reference to figure 9 and Figure 10 as the back) changes memory 23 with potbellied cycle period.

Fig. 9 represents when the incoming video signal that is transmitted 7 during for 2: 1 interlaced scanning systems of standard, the operation timing of memory 23, and Figure 10 represents when the incoming video signal 7 that is transmitted ' when being off-gauge interlaced scanning system, the operation timing of memory 23.

In the description with reference to figure 9 and Figure 10, vertical scan intervals is 7.5: 1 in modular system vision signal 7 with the ratio of horizontal scanning interval below, and the above-mentioned ratio in non-standard video signal system is 8.5: 1.The content of Fig. 9 and Figure 10 content with Fig. 3 basically is identical, and symbol V is illustrated in a vertical scan intervals in the interlaced scanning system.Symbol H represents a horizontal scanning interval, and symbol HS represents horizontal-drive signal, and symbol VS represents vertical synchronizing signal, the cycle period of symbol T and T ' presentation address." writing " that heavy line has shown memory 23 regularly, and " reading " that dotted line has shown memory 23 is regularly.

According to the vertical synchronizing signal 115 and the horizontal-drive signal 114 of input, calculate the ratio of vertical scan intervals to the horizontal scanning interval.Recently during the ratio of control criterion system (being " 7.5 " in this case), control circuit 35 is supplied with address generators 36 with signal 125 according to this.In view of the above, address generator 36 is set to " N " (in this case greater than the smallest positive integral of the vertical scan intervals of being calculated and the ratio of horizontal scanning interval, " N " is 8), thereby remove control storage 23, make the address cycle of its eight lines, so that each the vision signal of each bar line of the vision signal of input " is write " in turn.So shown in the solid line among Fig. 99, the write operation of memory 23 is performed.

With reference to period T shown in Figure 9 ₀(=1H) will be described " reading " operation of memory 23 below.When during T ₀Interior first by the 1H that 3. represents, (wherein, H: in the time of among the address of a line of video signal information write memory 23 horizontal scanning interval in interlacing scan), in first 1/2H, " read " to go out be write a line the address previous (second) by 2. ' the 1H vision signal of expression, and in next 1/2H the order " reading " go out be by 3. the expression vision signal, this signal is in described period T ₀Interior " writing " goes into.Meanwhile, each speed of " reading " operation above-mentioned to double " writing " is carried out.Memory 23 is controlled like this, and this operation is repeated, thus make signal during T ₁In with 2. '-3.-3. '-4.-4. '-calling over 5..Therefore, the signal on each bar line is alternately read with the time basic compress mode of 1/2H in two fields.Obtained thus the to carry out television video frequency signal of scanning system, scan line is the twice of interlaced scanning system to the field frequencies range of this signal with interlaced scanning system is identical, this is scanning-conversion.

In this case, vertical scan intervals is 75: 1 with the ratio of horizontal scanning interval, is a cycle period and memory 23 is operated by the address setting with 8 lines, by this preferably mode carry out scan conversion.Yet, when the ratio of vertical scan intervals and horizontal scanning interval changes 8.5: 1 into, just can not carry out this scan conversion preferably.Therefore, in second embodiment of the present invention, control circuit 35 is used for detecting according to vertical synchronizing signal 115 and 114 pairs of vertical scan intervals of horizontal-drive signal ratio with the horizontal scanning interval, so that signal 125 is offered address generator 36, making memory 23 is its address of cycle period circulation with 9 lines.

Figure 10 represents to be provided with in the above described manner a state of cycle period, and is the same with Fig. 9, during T ₂In, signal be with 2. '-3.-3. '-4.-4. '-calling over 5., scan conversion is carried out in a better mode.

Describe the 3rd embodiment of the present invention now, provided a scanning converter unit at the capacity that further reduces memory in second embodiment.Wherein have a bit, the 3rd embodiment is different with second embodiment, promptly is similar to the first above-mentioned embodiment, and the stepping of address stops at the near zone of vertical synchronizing signal.

The whole graphic structure of the 3rd embodiment is identical with second embodiment substantially, describes the 3rd embodiment so Fig. 8 also is applicable to.The vertical scan line of tentative standard system image signal 7 is 7.5: 1 to the ratio at the interval of horizontal scanning line, and to off-gauge picture intelligence 7 ', its ratio is 8.5: 1, and then the number of addresses of memory 23 is only required the vision signal of storing 6 lines in the 3rd embodiment.The 3rd embodiment is characterised in that control circuit 35 is a structure shown in Figure 11.

The work of control circuit shown in Figure 11 35 is described by reference Figure 12 and 13 now.

The work of the 3rd embodiment when Figure 12 represents to be input as the modular system vision signal, and the work of Figure 13 the 3rd embodiment when representing to be input as non-standard video signal system.In Figure 12 and 13, represent with identical reference number and symbol with the part that Fig. 9 is identical or corresponding with 10.

Vertical synchronizing signal 115 is input to trigger (T-FF) 41, and it produces pulse 126 one by one with the frame rate of incoming video signal 101.

These pulses 126 are added to first delayed-trigger (D-FF) 42, and the input signal 127 of a D-FF42 is added to and door 23, thereby becomes narrow frame period pulse.The reset signal of these burst pulses as first counter 44.The full value of first counter 44 is 12, and this number is the twice of the number (6) of the horizontal-drive signal 114 that occurred in a cycle period in the continuous operation of memory 23 in the block diagram shown in Figure 8.6H just is that a cycle period of memory 23 carries out stepping to the address with 6H, and this restores counter automatically by one realizes, counter restores when full count status automatically.Before first counter 44 is resetted by reset signal 128, the count value 129 of first counter 44 is stored in the register 45 immediately.Therefore, as Figure 12, under the situation of the incoming video signal 7 shown in 15, horizontal synchronization pulse appears at an image duration in (two vertical scan intervals), so first counter 44 0 when counting to 12 horizontal synchronization pulses, before reset signal 128 resetted to it, it counted 3 then, thereby made register 45 take out count value " 3 ".Further, as Figure 13, the input image signal 7 shown in 17 ' situation in, horizontal synchronization pulse appears at an image duration, so similarly when meter first counter 44 0 during to 12 horizontal synchronization pulses.Before reset signal 128 resetted to it, it counted 5 then, thereby made register 45 take out count value " 5 ".The output of register 45 is with the resulting integer of 2 removal count values " 3 " or " 5 ", i.e. " 1 " or " 2 ", and this is the input of second counter 46.131 zero clearings of second counter, 46 usefulness pulse signals, and pulse signal 131 is identical with second delayed-trigger (the 2nd D-FF) 47 with the vertical synchronizing signal that is produced with door 48 in timing, thereby to horizontal-drive signal 114 countings, till reaching the numerical value " 1 " or " 2 " that is received from register 45, when described number reaches " 1 " or " 2 ", stop its counting operation.During to horizontal-drive signal 114 countings, second counter 46 is output as " 1 " (being high level); After counting was ended, it was output as " 0 " (being low level).In such work, making second counting is a horizontal scanning interval (1H) width of the incoming video signal 7 shown in 12 according to 46 output pulse 132 width that produce; And be produced as incoming video signal shown in Figure 13 7 ' the pulse of two horizontal scanning intervals (2H) width.From the width of second counter 46 output is these pulses of 1H and 2H, further expands 1H by the 3rd delayed-trigger 49 or door 50, thus make from or door 50 outputs be the control signal 125 that the pulse of 2H or 3H constitutes by width.These control signals 125 are added to address generator 36, thereby, make it adjacent domain in vertical synchronizing signal and stop the address stepping of memory 23 during for a 2H of incoming video signal shown in Figure 12 7.And these signals be used to stop memory 23 for incoming video signal shown in Figure 13 7 ' a 3H during the address stepping.So under the situation of Figure 12, the work of memory 23 is with the cycle (T) of 8 lines as a circulation; And under the situation of Figure 13, be with the cycle (T ') of 9 lines as a circulation.Thereby the scan conversion that can realize wishing by a memory that has reduced capacity.

In Figure 12 and Figure 13, " writing " of vision signal and " reading " be with one with Fig. 9 mode identical with Figure 10 be not stop memory 23 the address stepping during in finish.For example, T during Figure 12 ₃And T ₄In, signal respectively with 3.-3. '-4.-4. '-5.-5. ' and 3. '-4. " 4. '-5. "-5. '-6. " call over, and during Figure 13 T ₅And T ₆, signal respectively with 3.-3. '-4.-4. '-5.-5. ' and 3. '-4. " 4. '-5. "-5. '-6. " call over.So, know that what finished is to the scan conversion of the signal of numbering in contiguous.

Under the state that the stepping of the address of memory 23 stops, though having, signal lacks, and near the order of " reading " at this signal or it also may occur unusually, but all these is the signal in the vertical retrace line interval, the same with above-mentioned situation, these are no any value to vision signal, so can not produce any practical problem.

In the above-described embodiment, the stepping of address stops at the neighboring region of vertical synchronizing signal, and can further reduce the memory capacity of storage device by the stepping at the regional halt address of adjacency of horizontal-drive signal.At this neighboring region without any the effective video signal.

Now, by describe the 4th embodiment of the present invention referring now to figs. 14 through Figure 16.

Interlaced scanning system is being transformed in the situation of the scanning system that carries out, the number that constitutes the scan line of a field has doubled, so, in general can obtain the more image of high definition.Yet when the image that is scanned conversion altered a great deal in time, the image by those moment in constantly constitute after 1/60 second image during with standard N TSC was different, so caused the reduction of image quality.

Therefore, added a circuit in the 4th embodiment, it can realize the scan conversion process among the motion of adjusting image.

Figure 14 is the block diagram of expression the 4th an embodiment structure.With reference to Figure 14, number 1/2H delay memory of 51 expressions, the output signal 112 that is used for memory 23 postpones 1/2H(H: in a horizontal scanning interval of interlacing scan); Numbers 52 is an adder, is used for output signal 133 additions of the output signal 112 of memory 23 with 1/2H delay memory 51; Numbers 53 is a coefficient multiplier, be used for adder 52 add the result take advantage of a coefficient 1/2; Numbers several 54 is a selector, is used for alternately selecting the output signal 133 of 1/2H delay memory 51 or the output signal 134 of coefficient multiplier 53; Numbers 55 is a moving detecting circuit, and it obtains differential signal in the frames from the output signal 103 of A-D transducer 21, thereby the image that detects above setting moves.Come the work of control storage 23 by the output of testing circuit 55, thereby remove to control control circuit 56(corresponding to first, second and the 3rd counter 29,30 and 31 among Fig. 7) and as later described selector 54.

Other structure is the same with Fig. 7 and Fig. 8, represents identical part by same reference number and symbol, has omitted description of them simultaneously here.

Now, by being described with reference to Figure 15 the work of the 4th embodiment, Figure 15 is the timing diagram of expression memory 23 work, and Figure 16 is the oscillogram of each output signal of Figure 14

In Figure 15, for the diagram convenience, the same with aforesaid each embodiment, the ratio of the vertical scanning signal same level sweep signal of carrying out 2: 1 interleaved television video frequency signal waveforms 7, be set to 7.5: 1, and each bar scan line of first and second by the numeral of drawing a circle therein.For video waveform 7, represented " writing " operation that memory 23 is carried out by solid line, and represented " reading " operation by a dotted line.

Among this embodiment, (N: natural number, N is " 7 " in the present embodiment) that the field is made of 2N+1/2 root line respectively.For the vision signal of interleaved two dependent field, be converted to the TV signal of the scanning system that carries out with double scan line, memory 23 have be used to store N+1 root scan line (in this situation, the address of signal N=8).Control circuit 56 is used to control the address cycle of 8 lines, so that the vision signal of each every line is one by one write separately address." write " execution of operation and the detection output of moving detecting circuit 55 and have nothing to do, that is to say that no matter how move, performed operation is identical in essence, and " reading " signal operation from memory 23 changes along with moving.

T during in Figure 15 ₁, being illustrated in moving detecting circuit 55 and judging and move under the situation about existing, memory 23 " reading " operation, and not during T the time is illustrated in to make not having to move and has under the situation about judging " reading " operation of memory 23.

Nothing according to moving detecting circuit 55 moves detection, and by " reading " operation that control circuit 56 comes control storage 23, this point is identical with situation in above-mentioned those embodiments.Now, by T during the reference ₂, the mobile detection according to moving detecting circuit 55 is described, come " reading " operation of control storage 23 by control circuit 56.

The read operation of control storage 23 control is performed such T during handle ₂In second vision signal 3. ' write in the process of address of single line, in during first 1/2H, 2. ' " reading " existing (second) vision signal in the address of the preceding single line of adjacent above-mentioned line address gone out, the speed of " reading " to go out is the twice of " writing " speed, then, " writing " speed handle with twice is written in described T during second 1/2H ₂Vision signal during this time 3. ' read.Rely on this control, moving when existing, only use the video signal information of existing (among Figure 15 second) to produce the insertion signal, the time base compression of having carried out simultaneously reading.

Because memory 23 is so controlled, thus in Figure 15 during T ₃In the video signal information 112 read from memory 23 enter into a represented state of Figure 16 (a), and move under the situation about existing when image, only with during T ₁Vision signal in shown existing produces the insertion signal, thereby has reduced the reduction of moving the graphical quality that causes owing to image.

Can directly be added to D-A transducer 25 to the signal shown in Figure 16 (a), so that it is presented on the display unit, and the processing procedure that the present invention who describes later on adopts is in order to improve graphical quality further.

Promptly handle postpones 1/2H(H from the signal shown in Figure 16 (a) that memory 23 is read by 1/2H delay memory 51: a horizontal scanning interval interlaced scanning system, i.e. a capable signal of reading from memory 23) then it is added to an input of detector 54 as signal 133 (Figure 16 (b)).Another input signal 134 of detector 54 shown in Figure 16 (c), it by 53 pairs of signals 112 of adder 52 and coefficient multiplier with 133 Xiang Jia And ask on average and obtain.Control selector 54 by moving detecting circuit 55, make it not select signal 133, select signal 134 according to moving the judgement that exists according to there being the judgement of moving, thus the signal of output shown in Figure 16 (d).Signal 135 is added to D-A transducer 25.It is converted to analog video signal 113, twice with horizontal frequency in the interlaced scanning system, the frequency of vertical scanning scans it with the same frequency of the frequency in the interlaced scanning system, and (not shown) produces a progressive frames in display unit thereby make.So, obtained the average value signal of same adjacent lines, this as during T ₁The insertion signal that produces, thus the improvement of graphical quality further promoted.

In Figure 16, signal 2. '+3. ' the expression signal 2. ' and 3. ' mean value.Because the present embodiment is the digital signal of handling after the A-D conversion, thus can not be by as the numeral in Figure 15 and Figure 16 7, representing video signal information with waveform, and for diagram makes things convenient for, be signal indication analog signal often.

So, according to the 4th embodiment, under the situation that is having image to move, obtained be by among the vision signal in existing and Figure 16 by during T ₁The progressive-scan system TV signal that vision signal in shown this constitutes; And do not having under the mobile situation of image, the progressive-scan system TV signal that is obtained is made up of vision signal in existing and the formed insertion signal of the vision signal in the previous field, so can form the image of high resolution by the reduction that reduces graphical quality.

Now, by reference Figure 17 and Figure 18 the 5th embodiment of the present invention is described.

The 5th embodiment that is provided considered following some: promptly interlaced scanning system is being converted in the device of progressive-scan system, incoming video signal may not be the signal in the interlaced scanning system.For example, under the situation of the graphic image signal that is produced by computer equipment, signal may be formed by progressive-scan system at first.Therefore, except the television video frequency signal of normal 2: 1 interlaced scanning systems, when scan conversion apparatus when computing equipment etc. receives the progressive-scan system picture intelligence, the work of scan conversion apparatus must be adapted to the received signal of these types.

With reference to Figure 17, the feature of the 5th embodiment has provided the discriminator 61 of the scanning system that is used to differentiate incoming video signal 101, thus the work that comes control address generator 36.

Promptly the vertical synchronizing signal 115 that obtains from synchronizing separator circuit 26 is added to an input of discriminator 61; And horizontal-drive signal 114 is added to another input of discriminator 61.Vertical and horizontal- drive signal 115 and 114 according to input, discriminator is decision making, when being the odd-multiple in 114 cycles of horizontal-drive signal (horizontal scanning interval), then be input as interlaced scanning system vision signal 101 when two cycles of vertical synchronizing signal 115 (two vertical scan intervals); And when two cycles of vertical synchronizing signal are the even-multiple in horizontal-drive signal cycle, then judge the vision signal 101 that is input as progressive-scan system.Then, discriminator 61 is added to address generator 36 to the signal 138 of expression incoming video signal scanning system.As describing later on, address generator 36 changes address information by the state of signal 138.

Other circuit that constitute embodiment of the present invention shown in Figure 17 are the same with embodiment shown in Figure 8 with signal, and represent identical or corresponding part by same reference number, omitted description of them here.

Figure 18 is a timing diagram, when the input image signal 101 that expression is judged by discriminator 61 is the signal of progressive-scan system, for the work of waveform input signal 7 memories 23, and address generator is set at second mode that adapts to progressive-scan system by signal 138.In Figure 18, the abscissa express time, the address of ordinate table memory 23, solid line for " writing " regularly, dotted line for " reading " regularly.The same with above-mentioned each embodiment, the NTSC system than present is little significantly to the ratio of horizontal scanning interval for the vertical scan intervals of the convenient set incoming video signal of diagram, is made as 8: 1.Because same reason, the waveform that approaches vertical synchronizing signal is represented in a tangible mode clear, and be illustrated in each bar scan line in first and second by number number of drawing a circle.

In the 5th embodiment, no matter address generator 36 is in first mode that adapts to interlaced scanning system or with the second way, memory 23 " writing " operation is all identical substantially with aforesaid each embodiment.Promptly in order to circulate, " writing " operation of memory 23 is so to carry out, suppose that N representative is greater than the vertical scan intervals of the incoming video signal smallest positive integral (is 8 in this kind situation) to the ratio of horizontal scanning interval, with the address of 8 lines, each the video signal information of every line of incoming video signal " is write ".

On the other hand, in first and second modes, memory 23 is done different work.

For example, when address generator 36 was set to first kind of mode, the work of memory 23 and the description of top Fig. 9 were identical.

Yet when address generator was set to the second way, the work of memory 23 was as follows:

For T during among Figure 18 ₃, T during handle appears at ₃In the 3rd vision signal 2. " when writing the address of single line, 1. " the vision signal that writes on existing (the 3rd) in the previous line address that is close to above-mentioned line address, during T ₃First 1/2H during, " read " to go out to double the speed of writing.Then, write on described during T ₃In video signal information 2. ", during during second 1/2H of T, read to double the speed of writing.Control to memory 23 is repeatedly carried out this operation, so, for instance during T ₄Signal read the order for 1. '-2. '-2. '-3. '-3. '-4. ', and during T ₅Also be with identical order 1. " 2. "-2. " 3. "-3. " 4. " read.That is to say, form the insertion signal by same adjacent lines.Certainly, in this case, be each signal to be read in the mode of time base compression.

For the horizontal frequency of the vision signal of reading in the working method separately twice for its incoming video signal, and vertical scanning frequency is the same with the vertical cycle of incoming video signal, thereby has formed the image of lining by line scan with double scan line.

By reading during address (shown in the dotted line among Figure 18) postpones a 1/2H, can be above-mentioned " reading " operation setting first or second mode at an easy rate, certainly, this variation is simple.

So the 5th embodiment in a better mode, can be applicable to that the vision signal of interlaced scanning system can be applicable to the vision signal of progressive-scan system again, thereby obtain the image of high definition.

Though above-mentioned five embodiments respectively have concrete feature, can realize a scanning converter unit that adapts to the various variations of incoming video signal to the free combination of each embodiment.For example, the 3rd and the 5th embodiment combined be applied to a scanning converter unit, make this device can be applicable to interlacing scan and the input signal of the two kinds of systems of lining by line scan, and the reduction of graphical quality seldom.Both made under interlaced scanning system input signal situation, during visual fast moving, the reduction of graphical quality is also very little.

Now, describe the 6th embodiment of the present invention by reference Figure 19 to 21, this scheme is applicable to a kind of scanning converter unit, and this is a kind of scanning means that is applicable to static graphics playback work.

Figure 19 is the block diagram of expression the 6th an embodiment structure, and the 6th embodiment is characterised in that the setting of mode controller 63.The structure of other structure and Fig. 7 or embodiment shown in Figure 8 is the same, and represents identical or corresponding part with same reference number.

The mode conversion signal 140 that mode controller 63 receives from the outside, control signal 141 and 142 is added to memory 23 and address generator 36 respectively, go to change the address producing method, thereby a scan conversion mode or a static graphics reproduction mode are set.

Figure 20 and Figure 21 are time diagrams, are used to represent embodiment shown in Figure 19, the work of memory 23 in static graphics reproduction mode.Figure 20 is identical with 21 represented also states with Fig. 9 and Figure 10, as below will describing.

The work of the 6th embodiment is described now.

In the scan conversion mode, the mode conversion signal 140 that mode controller 63 receives from the outside, be used to handle the output signal that address generator 36 and memory 23 are worked thereby produce on work timing shown in Figure 9, promptly in the scan conversion mode, the same with above-mentioned embodiment shown in Figure 8, the 6th embodiment is by the work timing work of Fig. 9.

On the other hand, in static graphics reproduction mode, the 6th embodiment is but carried out a special operational shown in Figure 20 and 21.

In more detail, the mode conversion signal of supplying with from the outside 140 is applicable to control static graphics reproduction mode, when signal is added to mode controller 63, and the output signal 141 and 142 of pass-through mode controller 63.Memory 23 is carried out and enter the conversion that static graphics is reappeared mode from the scan conversion mode shown in Figure 20 or 21.

With reference to Figure 20, when having produced signal, go to be controlled at when the static graphics on timing S is reappeared mode in first, memory 23 begins conversion in the following manner from the scan conversion mode:

By horizontal-drive signal the write address that is produced by address generator 36 is temporarily preset.Above-mentioned horizontal-drive signal is at time R ₁Occur after last second vertical synchronizing signal.And stop " writing " operation of memory 23 according to the termination of writing with the video signal information of a corresponding field of circulation of the whole address of memory 23 (the time E in Figure 20).In this case, the stopping just of " writing " operation realized by the storage that stops data (video signal information), and the stepping of " writing " address is to carry out as the endless form of a circulation with 8 lines.

On the other hand, in the field of the 1/2H of phase deviation horizontal scanning period of vertical synchronizing signal (second), be the mid point C that begins the horizontal scanning period of back 1H in end of a period from vertical scanning signal, it is just initial (at the time of Figure 20 R to read the address ₂).And the read operation of video signal information on the same single line that has write shown in Figure 20 reads twice to double the speed of writing, and repeats repeatedly in a looping fashion in the cycle period of memory 23.

Now by with reference to T during among Figure 20 ₄The work of memory 23 is described.Institute's repeated operation is: during T ₂The information that writes 4. ' during T ₂Second 1/2H in be read out, be written in described during T ₂In information 4. ' during T ₃First 1/2H " read " to go out once more.Therefore, be to read information with single line in multiple twice the mode of hanging down.Certainly, in this situation, be to read each signal in the mode of time base compression.

But during the 1H that follows, vertical synchronizing signal VS ' reads for once, in the NTSC of reality system, in the horizontal interval in the adjacent area of vertical synchronizing signal without any effective video signal message (promptly corresponding to vertical blanking interval), so as hereinafter to the description of first embodiment, this operation can not cause any practical problem.

As shown in figure 21, when producing the signal of control static graphics manner of playback on the timing S ' in second, memory 23 begins to change in the following manner from the scan conversion mode:

As can be seen from Figure 21, the execution of memory 23 " reading " operation, the same with above-mentioned situation, so " writing " address that is produced by address generator 36 is by following the horizontal-drive signal that occurs after first the vertical synchronizing signal (at timing R ₂) preset, and memory 23 " writing " operation is (the timing E among Figure 21) that stops according to the end of a period that the video signal information corresponding with 7 lines of memory 23 writes.

On the other hand.As shown in figure 21, the same with the situation of write operation in the field of the phase place of vertical synchronizing signal and horizontal scanning period coupling (first),, preset timing R among this and Figure 20 by the horizontal-drive signal that after vertical synchronizing signal, occurs reading the address ₃The situation difference.To during t ₀To t ₁The read operation of middle writing information for single line, is to double the speed of " writing ", to repeat twice.At t ₁After, repeated repeatedly for the read operation that writes on the vision signal of an effective field in the memory 23.

In the static graphics manner of playback, though only write the video signal information of 7 lines in the situation of Figure 21, this operation can not cause inconvenience yet.This is because do not comprise any effective video signal message (being vertical blanking interval) in followed by the horizontal interval after the vertical synchronizing signal in the NTSC of reality system.This also is suitable for for the situation of Figure 20.When handle assembly only was used in the static graphics manner of playback, the capacity of memory 23 wanted to adapt to the write operation of effective video holding wire number in a field, and read again twice for same writing information.

As mentioned above, the field frequencies range of the video signal information of reading with time base compress mode is identical with the field frequencies range of interlaced scanning system, and the line number of a field pattern shape has doubled, the video signal information of reading is like this reappeared, as the high resolution static graphics of the same position corresponding (being the same position on the display unit) with vertical synchronizing signal.

So, from the time diagram shown in Figure 20 and 21 as can be known, just can realize the conversion of the mode of reappearing from the scan conversion mode to static graphics at an easy rate by the producing method that changes the address a little, further, also be realized that, reappear mode from static graphics and also can carry out in the same way, although omitted detailed description here this to the conversion of scan conversion mode.

In the situation of Figure 21, during t ₀To t ₁In the information of reading in first 1/2H of every line (during the 1H) be t ₀Before, thereby upset the content of instantaneous static image, carried out so the operation of mode conversion is preferably in shown in Figure 20 second.Therefore, preferably as shown in Figure 19, a field recognizer is set separately in the line, so that automatically carry out second still image reproduction.

In addition, can carry out the replay operations of above-mentioned still image discontinuously, make it to realize being called a kind of special effects of stroboscopic action, also can output to recorded information (writing on the information in the memory) on the equipment of photographic means (printer) and so on simultaneously.

, thereby make under the condition that reduces used storage device capacity the good still image of resetting out so according to the 6th embodiment, the displaying contents of still image is that the same locational field pattern that is presented at display screen regularly resembles.

Although described the present invention and done detailed diagram, should know that diagram is an example, can not be as restriction, the spirit and scope of the invention only are subjected to the restriction of claims.

Claims (17)

1, a kind of scan conversion method that is converted to the scanning system video signal that carries out each other with the vision signal of two fields of interlacing scan relation, each is to constitute (N: positive integer) by 2N+1/2 bar scan line in interlaced scanning system, in progressive-scan system, compare with original system, field frequencies range is identical, and number of scanning lines doubles, and above-mentioned conversion method comprises the following steps:

Be equipped with a storage device, the address capability that it had can be stored the useful signal component that is included in the above-mentioned interlaced scanning system vision signal at least;

In each cycle period, assign the address of described storage device with N+1 bar scan line;

One by one write the vision signal of described interlaced scanning system by method of scanning lines in address of each appointment;

To double the speed of writing, twice ground is read and is stored in the signal component that writes in the address, thereby the interlaced scanning system vision signal is converted to the progressive-scan system vision signal.

2, according to the scan conversion method of claim 1, wherein, in the step that is equipped with memory, the address capability of storing described useful signal component is exactly the amount corresponding to the interlaced scanning system vision signal of N+1 bar scan line.

3, according to the scan conversion method of claim 1, the step of wherein said circulation assigned address comprises, with the N+1 bar scan line of described interlaced scanning system vision signal as a cycle period, the step of the address assignment that circulates.

4, the vision signal of two fields that have the interlacing scan relation each other is converted to a kind of scan conversion apparatus of progressive-scan system vision signal, each constitutes (N: positive integer) by 2N+1/2 bar scan line in interlaced scanning system, in progressive-scan system, compare with original system, field frequencies range is identical, and number of scanning lines doubles, and above-mentioned conversion equipment comprises:

A storage device (23), the address capability that is had can be stored the useful signal component that is included in the above-mentioned interlaced scanning system vision signal at least;

Address assignment device (30,31,36) is used for described storage device, and the address of read and write signal is assigned in circulation in each cycle period of being made up of N+1 bar scan line;

Write signal device (29) is used for the interlaced scanning system vision signal " write " to go in the specified address in described storage device of described address designating device (30,31,36) going;

Read signal device (29) is used for the speed write to double, and the signal in the described address of write storage device is read twice.

5, according to the scan conversion apparatus of claim 4, wherein said storage device (23) has the address capability of the interlaced scanning system vision signal that can store N+1 bar scan line.

6, according to the scan conversion apparatus of claim 4, wherein said address assignment device (30,31,36) as a cycle period, is Writing/Reading signal cycle assigned address with N+1 sweep spacing of described interlaced scanning system vision signal.

7, according to the scan conversion apparatus of claim 4, wherein said address assignment device (30,31,36) comprising:

Device (35) is used for the ratio of detection of vertical sweep spacing to the horizontal scanning interval;

Device (35) is set to N+1 according to the testing result of checkout gear (35) greater than the smallest positive integral of detection ratio, thereby is provided with N+1 sweep spacing as the address cycle cycle.

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