CH670335A5 - - Google Patents

Description

DESCRIPTION This invention relates to a method of manufacturing solid-state semiconductor devices, particularly photovoltaic cells, and enables an improved inexpensive method of manufacturing polycrystalline silicon solar cells, the damaged surface layer generated during the hydrogen passivation being used as a coating mask for the metallization of the front surface electrodes becomes. The method according to the invention is defined in patent claim 1, and applications of this method on silicon substrates produced in a certain way are defined in patent claims 5 and 13.

So far, a common manufacturing process for silicon solar cells has involved the steps: Forming a PN junction by diffusing a suitable dopant into the previous5

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the side of a silicon wafer or band, etching an electrode grid pattern in a protective dielectric mask layer which was formed on the front surface, depositing a nickel plating on all silicon which was exposed by the etching, covering the nickel with copper and tin, removing the rest of the dielectric mask layer from the front surface and applying an anti-reflective coating on the re-exposed parts of the front surfaces.

Although such a method is applicable to both single crystal and polycrystalline silicon, cost reasons make it appear desirable to produce solar cells from the latter. However, because of minority carrier losses at grain boundaries, crystal lattice dislocations, and the like, the efficiencies achieved with polycrystalline silicon solar cells are generally worse than those of monocrystalline cells. This fact has already been improved by the introduction of a monovalent element, such as hydrogen, into the structure in order to bind the free values from the lattice vacancies, as a result of which the recombination losses of the minority carriers are minimized.

As is known to the person skilled in the art, an important consideration when designing a cell processing sequence is that the combination of time and temperature in any step after the hydrogen passivation step does not cause the hydrogen introduced into the silicon to re-diffuse out of the passivated substrate. For example, it has been found that a hydrogen passivated cell that is exposed to a temperature of 600 ° C for half an hour loses essentially all of its bound hydrogen and returns to its pre-passivation level, as observed by electron Beam induced current activity has been proven. In this context it should be noted that the transition diffusion process in solar cell production typically requires temperatures in the order of 900 ° C.

It has also been found that hydrogen passivation typically heats the cell to a temperature high enough to cause base metals such as copper to migrate through the junction, causing a "soft" diode or short circuit. As for example by C.H. Seager, D.J. Sharp, J.K.G. Panitz and R.V. D'Aiello in the Journal of Vacuum Science and Technology, Vol. 20, No. 3, pages 430-435 (March 1982), the passivation of polycrystalline silicon can be obtained with a Kaufman ion source used to generate a hydrogen ion beam in the kiloelectron volt energy range. Relatively short exposure times (e.g. between 0.5 and 4 minutes) in an area of high ion energy and high flux (e.g. 1 to 3 milliamperes per square centimeter) appear optimal. Such irradiations generally result in an increase in the temperature of the substrate to at least approximately 275 ° C. if the substrate is carefully connected to a suitable heat sink. Otherwise temperatures above 400 ° C can easily be reached. However, it is important that the temperatures are limited to less than approx. 300 ° C in order to prevent rapid migration of base metals into the silicon matrix. The manipulation of substrate and heat sink to control the temperature during passivation, however, easily becomes the speed-determining factor in high-throughput processes with such ion sources. It is therefore desirable to avoid heat dissipation in order to obtain an inexpensive high throughput process. In addition, the heat dissipation with EFG silicon band, which is economically producible, is difficult to weave surface irregularities.

In addition, hydrogen passivation is most effective when the silicon base surface is exposed. Any "positive" coating mask used to define the front surface electrode grid pattern by covering the intermediate areas between the electrodes on the front surface should therefore not be in place during passivation.

As described in U.S. Patent Application No. 563,061 (U.S. Patent No. 4,609,565), the modified surface layer produced by hydrogen ion beam passivation can be used as a coating mask for subsequent metallization steps which include dip plating a selected metal. be used. A preferred embodiment of the method described in detail in US Patent Application No. 563,061 applied to the manufacture of silicon solar cells includes the following steps, among others: (1) Forming a coating mask of a dielectric material on the front surface of a flat silicon band Junction, leaving those areas of silicon that will later be covered by the front surface electrode free, (2) depositing a thin layer of nickel (or similar material) on the exposed silicon, (3) removing the coating mask, (4) hydrogen passivating the Transition side of the cell, (5) sintering the nickel to partially form a nickel silicide, (6) dip-plating additional nickel onto the metal-covered parts of the cell, (7) electroplating a layer of copper on the nickel, and (8) applying an anti-reflective coating the exposed surface of the silicon. The silicon can then be processed further, e.g. to prepare it for connection to electrical circuits. In an alternative method, heating the sample during passivation provides at least part of the energy for sintering the nickel.

While it is recognized that such a procedure

(1) allows removal of the first coating mask prior to passivation (to enable better passivation) and

(2) passivation before the application of base metals enables it without requiring an additional masking step before metallization (both eliminating the risk of spoiled cells by migration of the base metal during passivation and the production process by eliminating the need for either precise temperature control of the substrate during passivation or simplified for a photolithographic step after passivation), the method can be further improved. Thus, although the temperature control required to prevent base metal migration is bypassed (temperatures preferably below about 300 ° C), there is still a risk of spoiled cells from migration, albeit at slower diffusion rates, of nickel or Nickel silicide is given in the matrix of the substrate.

Furthermore, the method just discussed requires the formation of a coating mask as an additional layer on the substrate, specifically before the first metallization, and therefore requires additional process steps and materials.

It is therefore an object of the present invention to provide a sequence of processes for the production of solid-state semiconductor devices, in particular solar cells, which comprises a hydrogen passivation step after the high-temperature process steps, but before any front surface metallization, in order to migrate prevent base metals and their silicides, such as nickel or nickel silicide, into the matrix of the substrate.

It is a further object of the invention to provide such a sequence of processes which does not require the formation of a coating mask in order to prevent the metallization of the exposed passivated surface after the hydrogen passivation.

A preferred embodiment of the invention

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The process applied to the manufacture of silicon solar cells includes the following steps, among others: (1) Diffusing phosphorus into a P-type silicon ribbon to produce a shallow transition, the diffusion process simultaneously having a layer of phosphorus silicate glass on top of it (2) forming an electrode grid pattern from the phosphorus silicate glass layer by photolithography (using a suitable photoresist and etching) in the form of a “negative” coating mask (ie the phosphorus silicate glass is only left in those regions of the substrate) where it is desired to subsequently apply the front surface electrodes), (3) coating the other side of the silicon tape with an aluminum paste, (4) heating the silicon to alloy the aluminum, (5) hydrogen passivating the transition side of the cell while at the same time in the unbe between the phosphor silicate glass electrode pattern covered silicon substrate, an altered layer is formed, (6) etching away the remaining phosphorus silicate glass and (7) metallizing both the unchanged exposed silicon and the aluminum with a selected metal, e.g. Nickel, by plating. The silicon can then be processed further, for example in order to prepare it for connection to electrical circuits, and can be provided with an antireflection coating.

The term "dip plating" as used here means a process in which an article is plated with a metal without using an external electric field by immersing the article in a plating bath containing no reducing agent, whereby the plating consists of a displacement reaction. Immersion plating differs from electroless plates in that the latter comprises a coating bath which contains a reducing agent.

This production sequence has several key advantages.

By delaying the deposition of the front surface electrodes until after the passivation, any risk of cell deterioration due to migration of the electrode material into the transition during subsequent process steps is greatly reduced. Since the thermal control is less critical during the passivation, the heat dissipation can be omitted. Therefore, the present method allows high throughput ion beam passivation. In addition, by using the glass layer formed as a result of the transition formation process as the body of a negative coating mask, the preferred method eliminates both an etching step (to remove the glass first) and a coating step (to provide material for a coating mask), the glass taking place which is removed in two stages.

Brief description of the drawing

For a fuller understanding of the invention, reference should be made to the following detailed description, which must be seen in conjunction with the accompanying drawing which illustrates a number of steps for the manufacture of solar cells in accordance with a preferred form of the present invention.

Throughout the drawing, the same reference numbers refer to the same structures.

To simplify the illustration, the thicknesses and depths of the various coatings and regions are not shown exactly in their relative proportions in the drawing.

With reference to the drawing, a preferred embodiment of the invention relates to the production of solar cells from EFG-grown P-type silicon tape. The first process requirement is a side (hereinafter referred to as the «front») of a pre-cleaned EFG-P conductivity silicon

band 2 is subjected to a phosphorus diffusion process which is calculated to have a relatively shallow junction 4 (i.e. a junction of between 3000 and 7000 angstrom units depth), an N-type conductivity region 6 and a layer of reasonable thickness (e.g. in the order of magnitude of at least 1500 angstrom units) produced from phosphorus silicate glass 8. As an example, a silicon tape with P-type conductivity, which was produced by the “edge-defined film-fed growth” (EFG) process and has a resistance of approximately 5 ohm-cm, by etching in a solution of 70 % HN03: 49% HF in a ratio of between about 4: 1 and 9: 1 for about 1 to 3 minutes at about 25 ° C. The tape is then subjected to phosphorus diffusion in an oxygen-rich atmosphere. In this example, silicon and oxygen react to form silicon dioxide, react phosphorus and oxygen to form phosphorus pentoxide, react phosphorus pentoxide and silicon dioxide to form a phosphorus silicate glass, and react phosphorus pentoxide and silicon to form phosphorus and silicon dioxide. Alternatively, a phosphorus silicate glass can be used as the phosphor source which is manufactured as described in detail in US Pat. No. 4,152,824.

The next step involves coating the front of the tape with a negative photoresist 10, as is well known. The varnish can be applied in a suitable manner, e.g. by spraying, and then heated to drive off the organic solvents and give the varnish firm adhesion to the phosphorus silicate glass. Typically, this heating is accomplished by heating the photoresist to between about 80 and 110 ° C for between about 35 and about 60 minutes.

The photoresist layer is then covered with a negative mask in the pattern of a multi-fingered grid electrode, e.g. a mask with transparent areas that correspond to the fingers of the desired electrode, which is otherwise impermeable. As an example of a suitable electrode pattern, reference is made to US Pat. No. 3,686,036. The grating mask is then irradiated with ultraviolet light, the intensity and duration being sufficient to cause the illuminated part of the photoresist to polymerize. The photoresist is then developed by treatment with one or more suitable developing agents, for example by contact with toluene and propanol or other suitable solvents. This development process removes those parts of the paint that have not been irradiated and therefore have not been polymerized. Thus, part 10A of the photoresist remains in the pattern of the desired grid electrode configuration. Heating after development to about 140 ° C has been found to improve the resistance of the remaining resist to etching in the following process steps.

Following the exposure and development of the photoresist (and heating after development), the whole is exposed to a buffered oxide etchant, which consists for example of a solution of HF and NH4F, whereby the exposed layer of phosphorus silicate glass 8 is removed. In this way (P20s) x (Si02) y, a phosphosilicate glass, by immersing the substrate in 10 NH4F (40%): 1 HF at a temperature of approx. 25 ° C for a period between approx. 15 seconds and 2 Minutes from the latter. This leaves a layer 12 of phosphorus silicate glass intact in the pattern of the grid electrode configuration which lies under the polymerized non-removed portion 10A of the photoresist.

Next, the back of the substrate is coated with a layer 14 of an aluminum paste. The aluminum paste used to make layer 14 preferably comprises aluminum powder in a volatile form

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organic carrier, e.g. Terpineol, which can be removed by evaporation.

This step is then followed by an alloying step in which the substrate is heated to a temperature of above 575 ° C. for about 0.25 to 2.0 minutes in order to remove all volatile or pyrolyzable organic components of the paste and the aluminum in to alloy the paste with the silicon substrate.

In the alloying step, the aluminum coating 14 alloys with the back of the substrate to form a P + -type region 16 with a depth of approximately 1 to 5 micrometers. The alloying step also serves to remove the remaining photoresist portion 10A by pyrolysis.

Next, the cell is passivated with hydrogen. A preferred method is to expose the front surface of the substrate 2 to the hydrogen ion beam from a Kaufman type (wide beam) ion source which is approximately 15 cm from the substrate. This ion source is preferably at a pressure of between approximately 2.67 and 6.67 Pa (hydrogen), with a hydrogen flow rate in the order of approximately 25 to 40 cm3 (norm) per minute, with a DC voltage of approximately 1700 V between source and substrate and operated with a beam current of between about 1 and 3 milliamperes / cm2 on the substrate. An irradiation time of between approximately 1 and approximately 4 minutes was determined to be suitable both for the recombination losses of the minority carriers, which typically occur in EFG-type silicon cells (and for a passivation zone with a depth of approximately 20 to 80 micrometers or approximately 100 times the depth of the junction 4), while at the same time producing a modified surface layer 18 with a depth of approximately 200 angstrom units on the exposed parts of the substrate 2.

The exact nature of the modified surface layer 18 is not known. However, it is believed that it is a damaged zone in which the crystal structure has been somewhat broken, with the silicon partially forming SiH or SÌH2 with hydrogen from the ion beam, but the material may be amorphous. A small amount of carbon or one or more hydrocarbons appears to be necessary for the formation of the desired modified surface layer. In a first setup, the Kaufman ion source was equipped with a graphite assembly table with a diameter of approx. 5 inches (approx. 13 cm), on which the substrates, typically with a 2x4 inch (5x10 cm) side length, were arranged centrally. In some cases where a silicon assembly table replaced the graphite table, the changed layer behaved less well as a coating mask than in the cases where the graphite table was used. Because of this, it was believed that carbon or hydrocarbon vapor generated by the impact of the hydrogen ion "beam" on the graphite table could promote the formation of a dielectric layer on the surface of the substrate. However, it was found that a modified surface layer 18, which was generated in accordance with this method under acceleration voltages between approx. 1400 and approx. 1700 volts and with short irradiation times such as one minute, is sufficient to prevent subsequent metallization of the exposed modified surface layer 18 if the metallization does so Dip plating with a material such as nickel.

Following the passivation, the remaining layer 12 of phosphorus silicate glass is removed by immersing the substrate in a buffered solution of 10 NH4F (40%): 1 HF at a temperature of between approximately 25 ° C. and approximately 40 ° C. As a result, the front surface of the substrate 2 is now completely exposed. On this exposed surface, the modified surface layer 18 delimits a pattern, in this case unchanged N + conductivity silicon, which has the configuration of the desired front-side electrode structure.

The next step is to metallize the cell. The substrate is dip-plated with nickel, an adhesive nickel deposit on the back forming a nickel layer 22 over the entire surface of the aluminum coating 14, while the adhesive nickel deposit on the front side forms a nickel layer 20 directly on the surface of the substrate only over those surfaces of which the Phosphorus silicate glass had been removed after passivation forms. In this plating step, the modified surface layer 18 of the silicon forms a coating mask on which the nickel does not adhere. The plating of the nickel layers can be carried out according to various dip plating methods. It is preferably carried out in accordance with a dip plating process which is similar or similar to the process described in US Pat. No. 4,321,283 to Kirit Patel et al. In a preparatory step, the cleaned silicon substrate surface is pre-activated with a suitable agent. This preactivation procedure with a suitable agent is desirable because the silicon surface often does not itself support the electroless plating process and therefore everything nickel plated on an untreated surface generally does not adhere to it. Gold chloride is preferably used as the activating agent, although platinum chloride, stannochloride-palladium chloride or other well-known activating agents can also be used, as described, for example, in US Pat. No. 3,489,603. Thereupon both sides of the silicon tape are coated with a nickel layer, preferably by immersing the tape in an aqueous bath as described in said U.S. Patent No. 4,321,283, or in an aqueous bath of nickel sulfamate and ammonium fluoride at pH of approximately 2.9 and at approximately room temperature for a period of approximately 2 to 6 minutes.

After deposition of the nickel, the substrate is heated in an inert or nitrogen atmosphere to a temperature and for a time sufficient to sinter the nickel layers and the nickel layer 20 on the front of the substrate to react with the adjacent silicon to make an ohmic contact of nickel silicide. For this purpose, the substrate is preferably heated to a temperature of about 300 ° C. for between about 15 and about 40 minutes. This forms a nickel silicide layer with a depth of approximately 300 angstrom units at the interface between the nickel layer 20 and the substrate 2. The nickel layer 18 on the back forms an alloy with the aluminum layer 12. The temperature of this sintering step should not significantly exceed 300 ° C., since higher temperatures lead to excessive penetration of the nickel layer 20 into the silicon. The deposition and sintering of the nickel are preferably controlled in such a way that the nickel layer 20 on the front of the substrate has a thickness of approximately 1000 angstrom units.

The nickel of layers 18 and 20 is then preferably etched, for example with nitric acid, and further metallized, such as with a second layer of nickel by dip plating and one or more layers of copper by dip plating and / or electroplating using well known techniques. No masking of the modified layer is required for copper plating because the copper does not adhere to the damaged layer.

Following the metallization, the cell edges (not shown) are trimmed and an anti-reflective layer 24 is applied to the front surface of the cell. This can be done by any of numerous known methods, such as chemical vapor deposition

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or evaporation of TÏO2, for example. Alternatively, an anti-reflection coating 24 can be formed by plasma deposition of silicon nitride at a temperature of approximately 150 ° C., which is also known to the person skilled in the art.

The preferred method of practicing the invention comprises, for example, carrying out the individual process steps as described above in the preferred manner as described in detail for each process step and in the order mentioned.

It could be determined that solar cells, which are produced from EFG-grown tapes according to the previously described method, show between 10 and 20% increase in the average efficiency. In addition, the hydrogen passivation step for this material noticeably narrows the distribution of cell efficiencies, as has also been found.

The present method has a number of advantages. First and foremost, it eliminates the possibility of spoiling junction 4 during passivation by migrating nickel or nickel silicide, as might be the case with shallow junction cells if an initial nickel coating was applied to the front surface prior to passivation. Aside from reducing the likelihood of spoiled cells, this eases the need for strict temperature control (e.g., by heat dissipation) during passivation. This therefore enables an ion beam passivation step within the manufacturing process that has a high throughput rate.

It will be understood that the present invention is capable of modification while remaining within the scope of the disclosure. Thus, it is to be understood that while the front electrode grid pattern is formed in the coating mask by photolithography in the preferred embodiment, it could as well be made by other methods commonly used in chemical milling (e.g. screen printing).

Furthermore, although the preferred method uses the phosphorus silicate glass formed during N + diffusion to form the ion beam mask to limit the pattern of the damaged layer, other materials or methods could be used for the front surface layer. For example, an N + type substrate could be used as the starting material, the transition being formed, for example, by diffusion with boron, thereby providing a layer of borosilicate glass. If the starting material is also provided with a transition but without a glass layer, a suitable layer would have to be provided. It will be appreciated that the intended layer should either be etchable to form a suitable coating mask, or could be applied even in the appropriate configuration.

Furthermore, although the preferred embodiment of the method according to the present invention uses the modified layer formed by hydrogen passivation to prevent subsequent plating on areas other than the already plated nickel, the method can be carried out with metals other than nickel. For example, as will be readily appreciated by those skilled in the art, the starting layer of the front surface electrodes on a flat junction silicon device can be made by plating any of a number of low reactivity materials that is capable (preferably at a lower temperature) of making ohmic contact and act as a diffusion barrier for copper or any other base metal that will be applied at a later time. Suitable metals for use with copper include palladium, platinum, cobalt and rhodium, and nickel. While all of these materials form silicides, a layer of silicide is not essential. However, it is important that the first metal layer adheres perfectly, that it acts as an ohmic contact and that it serves as a migration barrier for any subsequently applied metal and that it itself has no significant migration into the transition. These materials can be applied by dip plating in the same way as nickel.

Still other changes can be made without departing from the principle of the invention, such as (a) forming the rear P + region of the cell by using flame-sprayed aluminum instead of an aluminum paste, or (b) using other methods of applying the second and the following coatings of nickel or other low reactivity material such as palladium, platinum, cobalt and rhodium, or (f) formation of the transition by ion implantation. If no additional mask density is applied over the passivated areas, the layer of nickel (or other low reactivity metal of the type described) must be applied by dip plating, and the additional layers of copper must be applied by electroplating or dip plating.

The process provided by the invention is of course not limited to the production of solar cells from EFG substrates. For example, cast polycrystalline substrates, epitaxial silicon on raw silicon or refined polysilicon layers, which are produced by chemical or physical vapor deposition, are used to form relatively high efficiency solar cells according to an embodiment of the present invention. The method is also applicable to single-crystal silicon and can be used with N-type and P-type silicon.

Furthermore, the method could be used to manufacture Schottky gates, the modified surface layer serving as a mask for the metallization. For such applications, of course, the metal-substrate interface is the transition, and consequently the substrate would not be provided with a transition by means of phosphorus diffusion or the like.

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Claims (16)

670 335 2nd PATENT CLAIMS 1. A method of manufacturing solid-state semiconductor devices, characterized by the successive steps that one (a) providing a silicon substrate having opposed first and second surfaces having a mask in the form of a surface layer having a predetermined two-dimensional pattern on said first surface and through which selected portions of said first surface are exposed; (b> exposing said first surface to a hydrogen ion beam with an intensity and for a period of time sufficient to form a partial surface layer on said selected exposed parts of said first surface to which metals adhere poorly; (c) removing said mask; and (d) subjecting said first surface to metal plating so that a metal layer is formed on all parts of said first surface, except for said selected exposed parts. 2. The method of claim 1 further comprising the step of forming a transition adjacent said first surface before being exposed to the hydrogen jet. 3. The method according to claim 1, characterized in that said devices are photovoltaic elements. 4. The method of claim 3 further comprising the step of applying an anti-reflective coating to cover said first surface. 5. Application of the method according to claim 1 to a silicon substrate, which was produced by (a) provides a silicon substrate with opposing first and second surfaces; (b) forming a surface layer on said first surface of said substrate; and (c) forming a mask in said surface layer by selectively etching a predetermined two-dimensional pattern therethrough, thereby selectively exposing selected portions of said first surface. 6. Use according to claim 5, characterized in that said surface layer consists of a glass layer formed as a result of the diffusion of a transition in said substrate adjacent to said first surface. 7. Use according to claim 6, characterized in that said transition is formed by diffusing phosphorus into said silicon substrate, thereby forming a surface layer of phosphorus silicate glass. 8. Use according to claim 5, characterized in that said mask is produced by photolithography using a photoresist covering said first surface. The application of claim 8, comprising the further steps of applying an aluminum coating to said second surface before the photoresist is removed and then heating said silicon substrate to a temperature and for a time sufficient to ( a) to alloy the aluminum of said coating with the silicon substrate and (ß) to remove said photoresist by pyrolysis. 10. Application according to claim 5, characterized in that the two above-mentioned first and second surfaces are metallized. 11. Use according to claim 5, characterized in that said surface layer is a dielectric. 12. Application according to claim 5, further comprising the The step of applying an aluminum coating to said second surface prior to metallizing said first surface and heating said aluminum to a temperature and for a period of time sufficient to cause the aluminum to alloy with the silicon substrate. 13. Application of the method according to claim 1 to a silicon substrate, which was produced by (a) provides a silicon substrate with opposing first and second surfaces; (b) forming a junction in said substrate adjacent to said first surface and simultaneously forming a layer of glass on said first surface; (c) covering said glass layer with an adhesive coating of a photoresist material; (d) exposing said adhesive coating to radiation energy through a mask defining a predetermined two-dimensional pattern; (e) said adhesive coating is chemically developed so that selected portions of said adhesive coating are removed from the glass layer in accordance with said predetermined pattern; (f) removing those portions of the glass layer that are not covered by said adhesive coating to expose selected portions of said first surface; (g) applying an aluminum coating on said second surface; and (h) heating said silicon substrate to a temperature and for a period of time sufficient to (a) cause the aluminum of said aluminum coating to alloy with said silicon substrate and (ß) removing said adhesive coating Induce pyrolysis; wherein after the treatment with the hydrogen ion beam said glass layer is removed and said first and second surfaces are metallized. 14. Application according to claim 13, characterized in that said first surface is exposed to said hydrogen ion beam with an intensity and for a duration sufficient to reduce the minority carrier losses of said substrate. 15. Use according to claim 13, characterized in that said metallization is carried out with a metal selected from the group of metals comprising nickel, palladium, cobalt, platinum and rhodium. 16. Use according to claim 13, characterized in that said metallization comprises a nickel plating from a bath which has a nickel salt and fluoride ions.