CH641626B - Verfahren zur herstellung von elektronischen uhrmodulen. - Google Patents
Verfahren zur herstellung von elektronischen uhrmodulen.Info
- Publication number
- CH641626B CH641626B CH40980A CH40980A CH641626B CH 641626 B CH641626 B CH 641626B CH 40980 A CH40980 A CH 40980A CH 40980 A CH40980 A CH 40980A CH 641626 B CH641626 B CH 641626B
- Authority
- CH
- Switzerland
- Prior art keywords
- printed circuit
- circuit board
- flexible printed
- chip
- leads
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 238000000465 moulding Methods 0.000 abstract 2
- 230000000717 retained effect Effects 0.000 abstract 1
- 229920005992 thermoplastic resin Polymers 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G17/00—Structural details; Housings
- G04G17/02—Component assemblies
- G04G17/04—Mounting of electronic components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Electric Clocks (AREA)
- Credit Cards Or The Like (AREA)
- Electromechanical Clocks (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP339679U JPS55105991U (de) | 1979-01-18 | 1979-01-18 | |
JP4182079A JPS55134386A (en) | 1979-04-06 | 1979-04-06 | Circuit substrate for electronic watch |
JP4607479A JPS55138847A (en) | 1979-04-17 | 1979-04-17 | Method of fabricating circuit substrate for watch |
JP4806579A JPS55141742A (en) | 1979-04-20 | 1979-04-20 | Circuit board for watch |
JP12258279A JPS5646540A (en) | 1979-09-26 | 1979-09-26 | Manufacture of circuit board for watch |
Publications (2)
Publication Number | Publication Date |
---|---|
CH641626B true CH641626B (de) | |
CH641626GA3 CH641626GA3 (de) | 1984-03-15 |
Family
ID=27518355
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CH40980A CH641626B (de) | 1979-01-18 | 1980-01-18 | Verfahren zur herstellung von elektronischen uhrmodulen. |
Country Status (2)
Country | Link |
---|---|
CH (1) | CH641626B (de) |
GB (1) | GB2042774B (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2545653B1 (fr) * | 1983-05-04 | 1986-06-06 | Pichot Michel | Procede et dispositif d'encapsulation de circuits integres |
EP0347974B1 (de) * | 1988-06-23 | 1994-10-26 | Teikoku Tsushin Kogyo Co. Ltd. | Montage von elektronischen Bauteilen |
DE19841498C2 (de) * | 1998-09-10 | 2002-02-21 | Beru Ag | Verfahren zum Herstellen eines Elektronikbauelementes, insbesondere eines Hallsensors |
-
1980
- 1980-01-18 CH CH40980A patent/CH641626B/de unknown
- 1980-01-18 GB GB8001694A patent/GB2042774B/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
GB2042774A (en) | 1980-09-24 |
CH641626GA3 (de) | 1984-03-15 |
GB2042774B (en) | 1983-04-13 |
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