CH628187A5 - Solid-state ripple-control receiver - Google Patents

Description

The invention relates to a static ripple control connected, which form part of a switching matrix, n -1 lines receivers with the second type mentioned in the preamble of claim 1 form the outputs of the programming field 4,

characteristics. which are connected to inputs of the microcomputer 3.

Ripple control systems are used to switch commands 45 at the intersections of the switching matrix primarily via the electrical supply network via sliding switches 11, which send the n in brackets to all consumer points in the network, be it for one = 3 positions ( 1), (2) and (3), connections

and switching off consumers or for other gen possible between the lines of the first and second type.

Control of switches. In a known manner, no diodes are required for this, since for each sliding

the command point feeds sound-frequency pulses into the network, switch 11 only provides a single line of the first type and the consumer to be controlled has receiver 50. The number n of switch positions can also be greater than that which respond to predetermined commands and which are three, for example 5, since they perform the switching functions seen from the number of contacts. Depends on the various slide switches 11.

the known ripple control systems are based on the customary. The FIG. 3 shows a block diagram of the microcomputer 3

most on the time interval method. In this one is represented, which consists of an input and output logic 13, a

Start pulse on the time axis a sequence of command pulses 55 control unit with clock generator 14, an addressing logic 15,

assigned. The individual manufacturers of the various round a program memory (ROM) 16, a computing unit

Control systems generally turn into several (ALU) 17 with one data memory (RAM) 18 and more

Relationships differing pulse trains. Data lines: address bus 19, data bus 20, 21 and 22 together

Modern static receivers for evaluating such settings. Furthermore, various control lines are present command pulse sequences consist of preferably pluggable 60 den. A first control line 23 leads from the control unit 14 elements which have a filter for selecting the audio frequency to the addressing logic 15, a second control line 24 from the pulse, at least one electronic channel set, an adjustment control unit 14 to the program memory 16, and a third controllable decoding function. Device, command relay and a power supply to and address line 25 from the control unit 14 for data feed supply of the receiver. The ripple control receiver for the evaluation 65 in the opposite direction and a fifth control line 27 can be set by a specific command pulse sequence by means of the decoding precharger 18 and computing unit 17, a fourth control line 26 in the direction. This control unit 14 to the input and output logic 13. The transfer setting can be carried out in various ways. Direction is on each bus, 20, 21 and 22 and on each

Several generations of such static control lines 23 to 27 have already been designated by arrows.

628 187

The pulse train of a ripple control system with a telegram of 50 pulse steps after a start pulse according to FIG. 4 consists of a start pulse part 28, an address part 29 and a command part 30. The start pulse part 28 can consist of a single start pulse, which in FIG 0 5 is referred to, and consist of an associated pulse pause or of several such pulses and pauses. The address part 29 consists of 16 pulse steps and the command part 30 consists of the pulse steps 17 to 50.

The ripple control receiver of FIG. 1 works as follows: The ripple control audio frequency signals picked up from the power terminals 1 are screened out in the filter 2 and converted to square-wave pulses in the pulse shaper of the filter 2, not shown. In order to avoid overloading the filter 2 and the subsequent electronic parts of the ripple control receiver, a limiter, also not shown, is preferably arranged in the filter 2. These pulses are compared in the only channel set for possibly several relays 11 microcomputers 3 with 20 programmed in the programming field 4, generated in this microcomputer 3 20 pulse trains and, if they match, transmitted through the output 8 to the amplifier 9 and as amplified command pulses for the Command execution relay 10 used.

If impulses or pulse pauses that do not match the programmed pulse sequence occur, the 25 microcomputer 3 is reset immediately, so that no non-predetermined pulse sequences or interference pulses arriving at the network terminals 1 come to the execution of commands in the command execution relay 10. Resetting also takes place when the current in the power supply line is switched on and off and when a deviation from the programmed pulse pattern is found.

In the program memory 16 of the microcomputer 3 (see FIG. 3), for the last-mentioned purpose, the temporal sequence of the pulses 35 and pulse pauses, which are relevant for a specific ripple control system, for the start, any address steps and for the execution pulse steps, taking into account the minimum and maximum duration and the correct spacing of the pulses and pulse pauses (pulse grid). Since the ripple control receivers are mass products, this procedure is economically justifiable. The corresponding program can be programmed in the program memory 16 by means of suitable masks during the manufacture of the microcomputer 3.

For the purpose of checking the operational readiness and the correct functioning of the microcomputer 3, a test program can also be stored in the program memory 16, through which the microcomputer 3 periodically checks the functioning at times when no ripple control transmission is expected. In the event of a failure, a test signal can be removed from an output 12.

The microcomputer 3 can be a microcomputer, for example of the MK 3870 type, which is set up for parallel processing of four, or even better, for eight bits. The lower costs of the four-bit computer are in most cases offset by the fact that the eight-bit computer does not require transcoders as the four-bit computer equipped for the lower number of outputs.

The interaction of the microcomputer 3 with the programming field 4 can be seen from FIG. 2. The clock generator built into the 60 microcomputer 3 in the control unit 14 generates the clock pulses which are important for the functioning of the microcomputer and which are divided down in a not shown coaster. The telegram pulse grid that is specific to the ripple control system in question is determined 65 by the program memory 16 in accordance with the pulses with the mains frequency at the synchronization input 6.

This synchronization enables the evaluation of the

Input 7 incoming pulse sequences for the ripple control commands take place with greater precision.

In the program memory 16 of the microcomputer 3, a large number of the pulse sequences provided for the pulse grid in question are also stored. This means that a special mask for evaluating the individual pulse sequences does not have to be produced for each individual ripple control system, as is the case when using integrated circuits of the so-called customer IC type in the evaluation part of the channel set. The pulse sequences generated by the programming in the program memory 16 in the control unit are transmitted to the programming field 4 via the m lines via the m lines after the start pulse 27 has been found to be good by the output logic. The n slide switches 11 of FIG. 2 convert the signals into a specific code and transmit them back on the n -1 lines to the input logic in part 13 of the microcomputer 3. The conversion of the specific code of the programming field 4 into the effective pulse sequence takes place in the microcomputer 3. The arithmetic unit 17 in the microcomputer 3 then carries out the comparison between the pulse trains arriving at the input 7 of the microcomputer 3 and the converted pulse trains. If this comparison is correct, a command signal is emitted at the end of an information block to the output 8 of the microcomputer 3, where, after amplification in the amplifier 9, it controls the associated relay 10 and thus initiates the command execution. As soon as a deviation occurs between the received and programmed pulse sequences, the microcomputer 3 is reset by a signal at the reset input R.

A program field 4 according to FIG. 2 with a total of 12 slide switches 11 with three positions each can be provided for ripple control receivers which operate in the most varied ripple control systems according to the pulse interval method. The assignment of the slide switch 11 for the various parts of the ripple control command pulse code can take place according to the circumstances.

A division into six slide switches 11 for the addresses and two groups of three slide switches 11 for setting the double commands is assumed below. The corresponding pulse diagram is contained in FIG. 4, in which after the start pulse 28 some subsequent pulse steps 29, in this example with a number of 16 steps, and steps 17 to 50 are provided for the command execution. The odd-numbered pulse steps in part 30 for the command execution are each assigned “on” commands and the even steps are assigned to the “off” commands.

If only one address in part 29 and two double commands in part 30 are used, which are assigned to two relays 10 in FIG. 1, then various options for dividing the positions of the slide switches 11 corresponding to the individual codes according to table 1 can be used:

Table 1

Relay control for the first relay

Relay control for the second relay

Address ABCDEF and double command UVW

Address ABCDEF and double command UVW or RST double command UVW (without address)

only address ABCDEF

Address ABCDEF and double command RST no relay control

Double command RST (without

Address)

Address ABCDEF and double command RST

The most varied types of impulse fol

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4th

gene, such only with address, only with double commands or mixtures of both with the slide switches 11 of the programming field 4 and be evaluated with the aid of the microcomputer 3 of FIG. 1. In the case of the commands which only have the address 29, pulse questions are to be understood, which are also known under the name “pulse picture” and wherein each individual “pulse picture” is only intended for a single command. The choice of the variant can be freely programmed by means of solder bridges or further slide switches 11 in the programming field 4.

It is common to use sixteen or more pulse steps when choosing the address steps in part 29 of FIG. secure them against wrong commands with a special code. With a group of 16 address steps, of which only two are sent, a total ('%) = 120 address step combinations can be achieved. All other address step combinations are rejected by the microcomputer as invalid.

Since the permissible address step combinations are limited to a quantity of 120, the address setting can be carried out using six slide switches 11. A six-digit ternary coding appears suitable for their representation, as shown in Table 2.

Table 2

Settings A to F impulse question of the address

111111

1100000000000000

16 impulse steps

111112

1010000000000000

16 impulse steps

111113

1001000000000000

16 impulse steps

122221

0000000000000011

16 impulse steps

The double commands of part 30 of FIG. 4 are set with the aid of slide switches 11, UVW and RST according to table 3.

Table 3

Setting UVW or RST double commands

111

1

112

2nd

113

3rd

331

25th

However, other impulse questions from other ripple control systems can also be evaluated. Since a step combination is selected from a limited number of address step combinations in the programming field 4 by setting a switch combination, a substantial saving in the number n of slide switches 11 and in the number of n-1 input lines for the microcomputer 3 can be achieved in any case if each address step were set individually on programming field 4.

The previously poor exploitation of the possibilities with the usual numbers of pulse steps in the transmitted pulse sequences can be expanded considerably in the sense of increased security of the command execution. The Hamming distance, which was d = 2 for the addressing shown and for double commands and which means a measure of the security of a code, can be increased, for example, by providing improved error detection and even error corrections. Binary codes with additional test steps for Hamming distances d = 3 and d = 4 according to the table are possible for addressing.

Table 4

Number of additional test steps

Address steps d = 3 d = 4

^ 4 3 4

^ 11 4 5

^ 26 5 6

With a Hamming distance d = 3 one error can be detected and corrected, with d = 4 two errors can be discovered and 1 error can be corrected. Since in turn programming field 4 only selects a step combination from a set of permissible address step combinations, consisting of information steps and test steps, such error-detecting and error-correcting address step combinations can be implemented with the same effort without difficulty.

For this purpose, the program of the microcomputer in the program memory 16 contains the instructions necessary for evaluating and implementing the setting on the programming field 4.

The use of addresses with 16 address steps according to FIG. 4 is particularly advantageous. If 11 pulse steps are divided as information steps and 5 pulse steps as test steps, compared to common ('%) codes for the address and assuming a bit error rate of 0.3%, an error probability that is eighty times smaller for incorrectly executed commands can be calculated. In addition, the probability of a correct address selection can be increased from 95.3% to 99.9%. Of course, this also requires the use of a corresponding pulse sequence on the transmitter side. The general tendency is towards increased safety in ripple control, which opens up further areas of application.

In systems with double instructions, the security of the instruction execution can be improved by adding a parity step. Such a step can be provided with a pulse for parity if there is an odd number of "on" commands in each double command. The pulse, however, is omitted if there is an even number of "on" commands. In addition, the "off" steps of the double command steps can also be checked in the same way by means of a second parity step. The parity steps also allow the detection and correction of errors caused by the transmission path.

The ripple control receiver according to the invention also allows the execution of conditional commands in a very simple manner. The individual commands are built into the same pulse sequence. In this case, the command (Z) is only executed if the command (Y) has been given beforehand. Such combined commands can be provided, for example, for (Y) = "low tariff" on "" and (Z) = "storage stove" on "".

The type of evaluation for such commands can be different.

5

10th

15

20th

25th

30th

35

40

45

50

55

60

65

5

Thus, in the microcomputer 3, a first command of the address selected by means of slide switches 11, A to F of the programming field 4 can be evaluated as a command (Y) in part 29 of FIG. 4. As command (Z), a 5 double command selected in section 30 of FIG. 4 by means of slide switches 11 in the UVW or RST group of programming field 4 by means of an AND link in microcomputer 3 between the address and table commands mentioned the lowest variant in Table 1 evaluated. Since the programming of the pulse trains in the ripple control receiver is carried out using the same micro computer, the conditional execution is adhered to even in the event of incorrect transmission.

In a similar way, a command (Y) can be combined,

if a common address in part A to F of programming field 4 and a double command from part UVW are combined by means of an AND circuit in microcomputer 3

628187

the. A command (Z) is created by combining the address from parts A to F with a double command from the RST group following the first double command, also with the help of a further AND circuit according to the top variant in Table 1. In the case of incorrect transmission, In this case, only a conditional execution takes place if the command (Z) is made dependent on the command (Y), for example by the previously mentioned addition of the double commands by a parity step.

The invention thus enables the evaluation of the known and many new pulse sequences according to the pulse interval method in a very simple and economical manner, wherein in the program memory 16 of the microcomputer only a possible adaptation by solder bridges to the individual, different pulse patterns is necessary.

G

2 sheets of drawings

Claims (6)

628187 2 PATENT CLAIMS known ripple control recipients, which differ by the degree of 1. Distinguish static ripple control receivers with an integration evaluation part. In the case of a ripple control in the form of a highly integrated semiconductor module and with a receiver according to the preamble of claim 1, this is a programming field, characterized in that it has progressed to such an extent that there is a single channel set for the evaluation part from a microcomputer (3) for the Parallel 5 several possible command relays executed in LSI technology is processing of at least 4 bits, which is an addressing (LSI: Large Scale Integration). Logic (15), an internal clock generator and converter (14), the invention has for its object, a Rundeine program memory (16), a data memory (18), a control receiver with a particularly high flexibility for the computing unit (17) and connections for Inputs and outputs evaluation of different already existing or new sheep, some of which to create ripple control command pulse sequences which are connected to the programming field (4), and which and that the programming field (4) are low from a matrix of production costs and which is a particularly safe switch to n switch positions, which allows the ripple control commands to be executed with n - 1. Bus lines allowed a connection. The object of the invention is achieved by the 2. ripple control receiver according to claim 1, characterized NEN of claim 1 resolved, characterized in that the micro-computer (3) a Synchroni-15 "The invention is based on the drawings, for example, sieringang (6) for signals with the frequency of the mains voltage explained, showing: owns. 1 shows the block diagram of a static ripple control 3. ripple control receiver according to claim 2, thereby catcher; characterized in that in the program memory (16) of the micro-Fig. 2 is a partial scheme of this receiver, Computer (3) for the ripple control 20- Fig. 3 is a block diagram of the micro-computer and stem relevant pulse grid and a variety of pulse Fig. 4 a pulse train. follow are stored by the addressing logic (15). In FIG. 1, 1 means the terminals of the 4. ripple control receiver according to claim 1, characterized position drawn power line. These are identified by a filter that the programming field (4) of sliding 2, in which there is preferably a limiter and pulse-shaping switches (11) with at least three switching positions, 25 are connected. The output of the filter 2 is a one-chip microcomputer, in the following microcompu serve to set the ripple control commands to be recognized. ter 3, connected, which on the one hand by means of m 5. ripple control receiver according to claim 4, characterized gears and n - 1 inputs with a programming field 4 marked that with the slide switches (11) addresses, bound, which is a programming device for the micro single commands, double commands or combinations thereof 30 computers 3 represents. From the terminal 1, a line can also be optionally formed. 5 to a synchronization input 6 of the microcomputer 3 6. ripple control receiver for a led. Another input 7 is intended for the ripple control signals ripple control system with a telegram to 50 pulse steps. The output 8 of the microcomputer 3 is provided with one and a start pulse, characterized in that nine ', possibly multi-channel amplifiers 9 are connected, and the slide switch (11) is present. 35 controls at least one command execution relay 10 drawn in solid lines. 2 shows the microcomputer 3 and the programming field 4 of the ripple control receiver in more detail. The m outputs of the output logic of the microcomputer 3 are 40 speaking m lines of the first type of the programming field 4