CH622901A5 - - Google Patents
Download PDFInfo
- Publication number
- CH622901A5 CH622901A5 CH1238077A CH1238077A CH622901A5 CH 622901 A5 CH622901 A5 CH 622901A5 CH 1238077 A CH1238077 A CH 1238077A CH 1238077 A CH1238077 A CH 1238077A CH 622901 A5 CH622901 A5 CH 622901A5
- Authority
- CH
- Switzerland
- Prior art keywords
- memory
- addressing
- recording
- counter
- data
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
- G11C11/415—Address circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Dram (AREA)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CH1238077A CH622901A5 (nl) | 1977-10-11 | 1977-10-11 | |
| US05/949,251 US4225948A (en) | 1977-10-11 | 1978-10-06 | Serial access memory device |
| FR7828883A FR2406287A1 (fr) | 1977-10-11 | 1978-10-10 | Dispositif de memoire sequentielle |
| DE2844352A DE2844352A1 (de) | 1977-10-11 | 1978-10-11 | Speicher mit serienweisem zugriff |
| GB7840099A GB2006487B (en) | 1977-10-11 | 1978-10-11 | Serial access memory devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CH1238077A CH622901A5 (nl) | 1977-10-11 | 1977-10-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CH622901A5 true CH622901A5 (nl) | 1981-04-30 |
Family
ID=4382454
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CH1238077A CH622901A5 (nl) | 1977-10-11 | 1977-10-11 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4225948A (nl) |
| CH (1) | CH622901A5 (nl) |
| DE (1) | DE2844352A1 (nl) |
| FR (1) | FR2406287A1 (nl) |
| GB (1) | GB2006487B (nl) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR910005615B1 (ko) * | 1988-07-18 | 1991-07-31 | 삼성전자 주식회사 | 프로그래머블 순차코오드 인식회로 |
| US5535354A (en) * | 1991-03-11 | 1996-07-09 | Digital Equipment Corporation | Method for addressing a block addressable memory using a gray code |
| JP4341043B2 (ja) * | 1995-03-06 | 2009-10-07 | 真彦 久野 | Ｉ／ｏ拡張装置，外部記憶装置，この外部記憶装置へのアクセス方法及び装置 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3665396A (en) * | 1968-10-11 | 1972-05-23 | Codex Corp | Sequential decoding |
| US3851313A (en) * | 1973-02-21 | 1974-11-26 | Texas Instruments Inc | Memory cell for sequentially addressed memory array |
| US3962689A (en) * | 1974-11-21 | 1976-06-08 | Brunson Raymond D | Memory control circuitry |
| US4120048A (en) * | 1977-12-27 | 1978-10-10 | Rockwell International Corporation | Memory with simultaneous sequential and random address modes |
-
1977
- 1977-10-11 CH CH1238077A patent/CH622901A5/fr not_active IP Right Cessation
-
1978
- 1978-10-06 US US05/949,251 patent/US4225948A/en not_active Expired - Lifetime
- 1978-10-10 FR FR7828883A patent/FR2406287A1/fr active Granted
- 1978-10-11 DE DE2844352A patent/DE2844352A1/de not_active Ceased
- 1978-10-11 GB GB7840099A patent/GB2006487B/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4225948A (en) | 1980-09-30 |
| GB2006487B (en) | 1982-02-10 |
| FR2406287B1 (nl) | 1983-05-27 |
| GB2006487A (en) | 1979-05-02 |
| DE2844352A1 (de) | 1979-04-12 |
| FR2406287A1 (fr) | 1979-05-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PL | Patent ceased |