CH617094A5 - Implantable pacemaker. - Google Patents

Description

The invention relates to an implantable pacemaker, in which the operating parameters can be changed and regulated in particular via a remote control.

Pacemakers are often provided with various devices for regulating certain operating parameters. B. is possible to set the pacemaker so that it responds to the patient's body and supplies him with signals according to his personal needs. However, after implanting the pacemaker, it can be very difficult to change certain operating parameters. Such changes can often be necessary, e.g. An improvement or deterioration of the patient's condition, and it may be necessary to make changes in the frequency at which the patient receives stimulation pulses, the width and amplitude of the pulses generated, the refractory period of the pacemaker, the sensitivity compared to naturally generated heart signals and the mode of operation of the pacemaker, which can operate as a demand pacemaker or as a pacemaker with a fixed frequency or the like.

Various suggestions have already been made as to how one could set certain operating parameters in an implanted pacemaker without major surgery. For example, it has been proposed to provide a "magnetic field responsive" switch that can be actuated by a magnet located outside the patient's body, usually when the pacemaker is to be switched from operating as a demand pacemaker to operating at a fixed rate. Furthermore, implantable pacemakers have been proposed which have devices into which surgical needles can be inserted, for example in order to change the resistance value of a resistor or the like.

US Pat. No. 3,805,796 describes an implantable pacemaker in which certain operating parameters can be set and to which a first and a second digital pulse counter belong. The first counter receives a first predetermined set of input pulses and then generates an enable signal to supply subsequent input pulses to the second counter. The second counter has a plurality of outputs, the output signals of which can be used to actuate various switches, each of which is connected in parallel with an associated resistor from a plurality of resistors connected in series, so that it is possible to regulate the input current of a transistor of a multivibrator and thereby its To change time constant. A switch is controlled by means of a further output signal of the second counter, which redirects a part of the drive current to the output amplifier of the pacemaker, in order to thereby regulate the output current.

This known pacemaker responds to an access key value, which is only a sequence of seven pulses. With this pacemaker, seven pulses must appear in a row so that they can be counted by the first counter. If the wearer of such a pacemaker z. B. exposed to a field to which the circuit responds, the circuit may erroneously respond to pulses from the field as well as to the access keyword, and therefore there is a risk that the various parameters regulated by the circuit will subsequently be reset.

Furthermore, this known pacemaker has devices which only make it possible to change the pulse frequency (and incidentally the width) and the output current of the pacemaker, but many of the other important parameters of the pacemaker mentioned at the outset are not taken into account.

Another disadvantage of this known pacemaker is that after counting the access pulses and enabling the second counter, the data pulses supplied to it instantaneously change in the different ones

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Cause output lines. These changes lead to immediate changes in the choice of different timer resistances during the period of data reception. If only the switch for changing the output current, which can be actuated by the last output count result of the counter, is to be actuated, all combinations of timer resistances are therefore activated in succession before finally actuating the bypass switch, which was originally intended to be the only one to be switched .

The invention was therefore based on the object of providing a cardiac pacemaker, which includes devices for regulating certain operating parameters which are to be arranged outside the pacemaker or at a distance from it, and which can be controlled from the outside after the implantation in order to change one or more operating parameters, e.g. B. the width of the stimulation pulses, the amplitude of the stimulation pulses, the stimulation pulse frequency when operating as a demand pacemaker or when operating at a fixed frequency, the refractory period, the sensitivity to heart signals and the operating mode, and in which the selected operating parameters are directly effective without intermediate changes a satisfactory security against response to external signals is guaranteed and the operating parameters can be changed independently of each other.

The inventive solution to this problem consists in the implantable pacemaker characterized in claim 1. Advantageous refinements of the pacemaker according to the invention can be found in claims 2-5.

Exemplary embodiments of the invention are explained in more detail below with the aid of schematic drawings. It shows:

1 shows a block diagram of a pacemaker according to the invention with controllable operating parameters;

2 shows a block diagram of a main circuit for regulating the operating parameters with an access keyword detection circuit, an instruction memory and a circuit for loading the memory with the instruction word;

FIG. 3A in connection with FIG. 3B upd 3C further details of the electrical construction of the main parameter control circuit according to FIG. 2;

FIG. 4 shows the details of the electrical construction of the pulse generator, the amplitude control circuit, the R-wave amplifier and the sensitivity control circuit of the pacemaker according to FIG. 1;

FIG. 5A in conjunction with FIG. 5B shows the details of the electrical construction of the control counter circuit, the circuit for regulating the refractory period, the reset circuit for the asynchronous interval generator, the mode selection circuit, the asynchronous interval generator circuit, the asynchronous frequency control circuit and the pulse width control circuit of the Pacemaker according to Fig. 1;

6A in conjunction with FIGS. 6B, 6C and 6D the electrical structure of an outer control circuit for transmitting the access and parameter values to the main parameter control circuit according to FIGS. 3A, 3B and 3C.

In the various figures, corresponding parts are each identified by the same reference numerals, and the connecting lines between the different parts of the circuit are identified by corresponding letters A, B, C, etc.

1 shows a preferred embodiment of a pacemaker according to the invention in a block diagram and is designated overall by 10. The various individual electrical circuits of the pacemaker according to FIG. 1 are explained in more detail below with reference to FIGS. 2 to 5.

1 there is an electrode connection 11, which is connected to cardiac electrodes in a known and therefore not to be explained manner and then receives cardiac signals and other signals generated in a natural way and emits cardiac stimulation signals.

To make it easier to distinguish between, the operating parameters and components that are not synchronized with the natural heartbeat are identified by the word “asynchronous”.

The pacemaker 10 works in conjunction with a digital clock 12, the clock pulses with a frequency of z. B. 6.82 kHz. The clock pulses of the clock generator 12 are divided by a first frequency divider 13 and fed via a line 14 to an asynchronous interval generator 15 which is connected to an asynchronous frequency regulator 16 via a plurality of outputs TI-T8. Each of the outputs T1-T8 is assigned a different asynchronous interval within the area of interest, and the asynchronous frequency controller 16 selects one of the eight outputs of the asynchronous interval generator under the control influence of a main parameter controller 150.

The selected output signal of the asynchronous interval generator 15 is fed to a pulse width controller 17 which, when triggered by the main parameter controller 150, outputs an output pulse of a predetermined width. This mode of operation is made possible by the fact that the clock pulses appearing in line 14 are fed directly to pulse width controller 17 and a second frequency divider 19, which generates additional clock pulses, the frequency of which corresponds to a partial amount of the frequency of the clock pulses of clock generator 12, and which are fed to pulse width controller 17 so that signals are obtained from which the various widths of the output pulse can be selected.

The output pulses of the pulse width controller 17 are fed to a pulse generator 21 in order to trigger it, so that it outputs an output pulse to the output line 22, which pulse is fed to the electrode connection 11. The amplitude of the stimulation pulse generated by the pulse generator 21 is controlled by an amplitude controller 24, which in turn is also controlled by the main parameter controller 150.

The output signal of the pulse width controller 17 is supplied not only to the pulse generator 21, but also via a NAND circuit 30 to a reset input of the asynchronous interval generator 15. As soon as a predetermined selected counting result is reached in the asynchronous interval generator 15, i. H. thus, when the pulse width controller 17 outputs an output pulse, the asynchronous interval generator is reset to start counting the next asynchronous interval.

The part of the pacemaker according to Fig. 1 described so far operates at a fixed rate, i. H. it generates asynchronous pulses with the natural heartbeats at a frequency which is determined by the selected output signal of the asynchronous interval generator 15. An R-wave amplifier 32 is provided to enable operation as a demand pacemaker. The electrode connection 11 leading to a heart electrode is connected by a line 33 to an input of the R-wave amplifier 32 so that cardiac pulses generated in a natural way can be supplied to it. Other signals, e.g. B. the stimulation pulses generated by the pulse generator 21 and delivered to the line 22 by the cardiac electrodes or other associated circuits received electrical interference signals, but filtering or rejection is carried out in a manner yet to be explained, or it is carried out in the event of occurrence a failure to operate with a fixed

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Frequency passed. The sensitivity of the R-wave amplifier 32 is controlled by a sensitivity controller 35, which in turn is controlled by the main parameter controller 150.

The R-wave amplifier 32 generates an output signal as soon as an naturally occurring R-wave or a stimulation pulse or an interference signal is detected, and this output signal is fed to a control counter 38, to which the clock pulses of the clock generator 12 are also fed via a NAND circuit 40 and, after the reset, output signals are generated at times Tl, T2 and T3. The output signal generated at the time T1 is fed to a reset circuit 41 which generates an output signal which arrives at the asynchronous interval generator 15 via the NAND circuit 30 in order to reset it. Thus, if an R-wave, a stimulation pulse or an interference signal reaches the R-wave amplifier during operation before a signal appears at a selected output of the asynchronous interval generator 15, this generator is reset to start a new counting process; in this case the pacemaker operates in a known manner as a demand pacemaker.

Furthermore, one or the other of the outputs T2 and T3 of the control counter 38 can be selected by a control circuit 43 for determining the refractory period; this circuit 43 is also controlled by the main parameter controller 150. The selected output signal is fed to an inverting NAND circuit 45 in order to arrive at the NAND circuit 40 which controls the passage of the clock pulses from the line 14 and to the reset circuit 41 for the asynchronous interval generator 15, so that a Sets the operating state in which a pulse subsequently generated by the control counter 38 for resetting the asynchronous interval generator 15 is passed. Thus, the circuit 43 for regulating the refractory period brings the reset circuit 41 for the asynchronous interval generator 15 into an “alarm state” after the control counter 38 has reached a predetermined count result for the refractory period, which is determined by the regulating circuit 43. After the alarm state has been brought about, a logic signal is supplied to the input of the NAND circuit 40, which prevents the clock pulses supplied via the line 14 from being passed on in order to end the counting process of the control counter 38. Thereafter, the generation of an output signal by the R-wave amplifier 32 results in the generation of a pulse, by which the control counter 38 is reset and caused to start a new counting process. As soon as the time T1 is reached during the counting, the reset circuit 41 of the interval generator 15, which was previously released by the circuit 43 for regulating the refractory period, generates a reset pulse for deleting the counting result of the asynchronous interval generator 15. Before the “alarm state” is reached however, the pacemaker is in a "control state" in which the arrival of a signal from the R-wave amplifier 32 does not lead to the generation of a reset pulse for the asynchronous interval generator 15; rather, only the control counter 38 is reset to count the preselected refractory period from the beginning.

There is also an operating mode selector 50 which is controlled by the main parameter controller 150. If the mode selector 50 is actuated, it blocks the reset circuit 41 of the asynchronous interval generator 15 so that the pacemaker 10 operates at a fixed frequency. In addition, the mode selector 50 can temporarily with the help of an external device, for. B. an electromagnet or the like, operated to let the pacemaker work for testing purposes in a known manner at a fixed frequency.

The main parameter controller 150, which is described in more detail below, is programmed via an external control signal which is sent to a receiving element 215, e.g. B. a magnetically actuated reed switch or the like is supplied.

The pacemaker 10 has a device for changing operating parameters, which include in particular the stimulation pulse width, the stimulation pulse amplitude, the length of the refractory period, the sensitivity to cardiac signals and the operating mode (operation with a fixed frequency or as a demand pacemaker) and the frequency of the asynchronous pulses . These operating parameters can also be changed after the pacemaker has been implanted in the patient's body. In order to facilitate the regulation of the parameters mentioned, the main parameter controller 150 is provided, the details of which can be seen in FIGS. 2 and 3A to 3C.

As explained below, the main parameter controller 150 responds to an externally supplied input signal, which is generated by a command transmitter to be described, in the form of an introductory access sequence of electromagnetic pulses, after which a further sequence of electromagnetic pulses appears to determine the operating parameters of the pacemaker . The main parameter controller 150 must first recognize the access pulse train before accepting the control pulse train and entering the memory of the main parameter controller. 2, the externally supplied input signal is received by a digital monostable pulse generator 151 which generates an output pulse of controlled amplitude and width for each externally supplied input pulse to avoid the bouncing of the switch to be described to detect the input signal leads to difficulties. The output signal of the monostable pulse generator 151 is fed to a start inhibit circuit 152 and a NAND circuit 156, the output of which is connected to the input of a shift register 165, in which the various outputs are connected to a data detection circuit 172.

At the same time, clock pulses from the clock generator 12 are fed to the monostable pulse generator 151, a reset circuit 155 and a counter 162. Of three output signals of the counter 162 appearing at different points in time, one goes to the shift register 165, another to a search-lock circuit 166 for ending a data search process and the third to a stop-lock circuit 167. The output signal of the NAND- In addition to the input of shift register 165, circuit 156 is also fed to a second NAND circuit 170.

The output signal of the data detection circuit 172 and the output signal of the search disable circuit 166 pass to a NAND circuit 174, the output signal of which is fed to the input of an enable circuit 176, the output signal of which is sent to another input of the NAND circuit 170 and to an AND Circuit 180 arrives. The output signal of the stop-lock circuit 167 is fed to a further input of the AND circuit 180 and a reset input R of the start-lock circuit 180 and a reset input R of the start-lock circuit 152. The output signal of the NAND circuit 170 is fed to the input of a data counter 182, the outputs of which are connected to a data memory 184. The output signal of the AND circuit 180 reaches a control input of the data memory 184.

If an input signal is supplied from the outside to the digital monostable pulse generator 151, the start / lock circuit 152 is actuated by the reset circuit 155

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to be actuated so that actuation of the shift register 165, the search inhibit circuit 166, the enable circuit 176, the stop inhibit circuit 167 and the data counter 182 is initiated. In addition, actuation of the start inhibit circuit 152 causes the counter 162 to begin counting. As explained below, the counter 162 generates three output signals, the frequencies of which correspond to the clock frequency after each division by a specific factor.

From the monostable pulse generator 151, the data representing pulses then pass through the NAND circuit 156, which has been enabled by the output signal of the start-inhibit circuit 152 to pass the data pulses, to the shift register 165, which is the data detection circuit 172 is connected upstream. The first seven data bits are input to the shift register 165 at a frequency which, in the exemplary embodiment described here, corresponds to the frequency of the clock generator 12 divided by 32. The data are continuously transferred from the shift register 165 into the logic data recognition circuit 172, which only delivers an output signal when a specific recognition keyword appears in the shift register. At the same time, the search blocking circuit 166 is actuated to end the data search by another output signal of the counter 162, the frequency of which corresponds to another partial amount of the frequency of the clock generator 12, e.g. B. 1 / 2S6 of the clock frequency, d. H. the time required to input the first seven data bits to the shift register 165. The enable circuit 176 is actuated by the output signal of the search disable circuit 166 when it is fed to the NAND circuit 174 together with the output signal of the data recognition circuit 172. Therefore, the parameter data pulses appearing at the output of the NAND circuit 156 are then fed through the NAND circuit 170 to the data counter 182 and from there to the data memory 184.

As soon as the parameter data pulses have been completely input to the memory 184, the stop-lock circuit 167 is triggered in order to generate a signal which is fed via the AND circuit 180 to the control input ST of the data memory 184. At the same time, the output signal of the stop-lock circuit 167 reaches the start-lock circuit 152 in order to bring it back to its initial state and thereby prevent further transmission of data pulses.

The data pulses from the external command transmitter are now read out from the data memory 184 in order to change the operating parameters of the pacemaker.

The main parameter controller 150 of FIG. 2 for receiving the command pulses is shown in further detail in FIGS. 3A to 3C. According to FIG. 3A, the clock generator 12 includes an astable multivibrator 200 which emits an oscillator output signal on a line 201 in order to supply clock pulses to the other parts of the circuit arrangement. There is also a frequency divider 13, to which a J-K main servo flip-flop 203 belongs, to which a divided frequency output signal of the astable multivibrator 200 is fed via a clock input; there is also a D-type flip-flop 204 to which the Q output signal of the J-K flip-flop 203 is supplied via a clock input. The Q output signal of the D flip-flop 204 is applied to the D input so that the output signal alternates between a high or H and a low or L value on successive clock pulses to divide the clock frequency by two. The Q output signal of the D flip-flop 204 is discharged via a line 208 which continues from the point BB in FIG. 3A to the pulse width controller 17 according to FIG. 5B. Since the Q output signal of the astable multivibrator 200 has half the frequency of the oscillator frequency, the Q output signal of the D flip-flop 204 corresponds to the clock frequency divided by four. The set and reset inputs of the D flip-flop 204 and the J-K flip-flop 203 are connected to a line 190 which carries an L signal in order to ensure that the two flip-flops operate continuously.

The VSS connection, the positive trigger connection + T, the outer reset connection ER and the repetition trigger connection RT of the clock generator 12 are kept at L-voltage level, while the astable connection Ä, the negative trigger connection —'T and the VDD connection be kept at an H voltage level. The integrated circuit 200 of the clock generator 12 thus works as an astable multivibrator, the output signal of which appears in line 201, signals with half the frequency being supplied to the J-K flip-flop 203 in the manner described via line 210. Thus, the output signal on line 201 forms the primary clock frequency, the output signal on line 14 at point AA forms the first partial frequency generated by frequency divider 13, and the output signal on line 208 at point BB forms the second partial frequency generated by frequency divider 19 Clock frequency. The frequency of the clock generator 12 is determined by the electrical values of the capacitor 211 and the resistor 212, which are connected to the capacitor connection C, the resistance connection R and the common RC connection of the astable multivibrator 200. The frequency can be adjusted by changing the resistance value of the resistor 212. In the exemplary embodiment shown, the resistor 212 has a resistance value of approximately 2 megohms and the capacitor has a capacitance of approximately 100 pF, so that the clock frequency can be set to approximately 6.82 kHz. A Zener diode 213 is located between the capacitor connection C of the multivibrator 200 and ground, so that the oscillator frequency does not decrease as the battery voltage decreases.

The data transmitted by the outer command transmitter described below are received according to FIG. 3A by a magnetically actuable reed switch 215 and fed to the digital monostable pulse generator 151, which ensures that each pulse picked up by the reed switch 215 has the correct shape and width to pass through the remaining parts of the circuit can be processed; the monostable pulse generator 151 includes two flip-flops 220 and 221 of the D type, a binary rapid transfer counter 222 and an AND circuit 223. The data pulses are supplied to the clock input CL of the D flip-flop 220, whose D input is at H Voltage is maintained. The Q output signal of the D flip-flop 220 arrives at the D input of the D flip flop 221, and the Q output signal of this D flip flop 221 is applied to the reset inputs R of the D flip via the AND circuit 223 -Flops 220 and 221 fed. In addition, the AND circuit 223 is supplied with the primary clock pulses appearing on line 201 to synchronize the resetting of the D flip-flops 220 and 221. The Q output signal of the D flip-flop 220 reaches a reset input R of the counter 222. The clock input CL of the counter 222 is connected to the line 201 so that the primary clock pulses are supplied from there. The output of counter 222 is e.g. B. removed via the output Q6 and fed to the clock input CL of the D flip-flop 221.

If a data pulse arrives at the reed switch 215, this therefore serves to get the H signal present at the D input to the Q output of the D flip-flop 220 and from there to the D input of the D flip-flop 221 allow. If the Q output signal assumes an H value, then it goes

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returns the Q output signal to L, thereby canceling the H reset signal at counter 222, whereupon this counter can begin counting the clock pulses supplied to it via line 201. If an H output signal appears at the output Q6 of the counter 222, within 26 times the clock frequency divided by two in seconds, the H signal present at the D input of the D flip-flop 221 becomes the associated Q output passed to be fed to an input of AND circuit 223. When the next clock pulse appears on line 201, the H signal is fed to the reset inputs of D flip-flops 220 and 221 in order to bring them back to their initial state. Thus, the pulse appearing on the output line 230 will have a constant width determined by the time during which the signal appearing at the output Q6 of the counter 222 can have an H value after the pulse arrives at the reed switch 215. The amplitude of the output pulse on line 230 will of course be constant and correspond to the H voltage level.

The output signal of the digital monostable pulse generator 151 is fed to the start-lock circuit 152 according to FIG. 3A. The start-lock circuit 152 includes a J-K main servo flip-flop 235, the clock input CL of which is supplied with the output signal of the monostable pulse generator 151. The K input of J-K flip-flop 235 is held low and the J input is connected to the Q output. Therefore, a constant H signal is maintained at the Q output after the arrival of the first clock pulse until the J-K flip-flop 235 is reset. The reset input R is connected to the stop-lock circuit 167 described below with reference to FIG. 3B. From the Q output, the output signal of the JK flip-flop 235 arrives at an input of a NAND circuit 15.6, and the in FIG Data pulses appearing on the output line 230 of the monostable pulse generator 151 arrive at the other input of the NAND circuit. The output signal of the NAND circuit 156 is fed to the shift register 165 according to FIG. 3B and to an input of the NAND circuit 170 according to FIG. 3C, in order to arrive at the data counter 182 in a manner still to be explained.

3B, the Q output signal of the J-K flip-flop 235 arrives at the reset circuit 155, which includes two D-type flip-flops 240 and 241. The D input of the D flip-flop 240 is held at high voltage and the output signal of the start blocking circuit 152 which appears on line 239 is supplied to the clock input CL. Thus, if an H signal appears on line 239 instead of an L signal, the H signal is passed on from the D input to the Q output of the D flip-flop 240 so that it is at the D input of the D flip -Flops 241 appears. Primary clock pulses appearing on line 201 are supplied to the clock input CL of the D flip-flop 241. Thus, when the start inhibit circuit 152 is actuated, the H signal is passed on from the D input of the D flip-flop 240 at the same time as a clock pulse to the Q output of the D flip-flop 241, so that in the output line 243 an H reset signal appears which, in a manner still to be explained, the reset input R of the D flip-flop 240, the shift register 165, the enable circuit 176 (FIG. 3C), the stop-lock circuit for the data search (FIG 3C) and the data counter 182 (FIG. 3C). However, the duration of the reset pulse is automatically limited, i. H. it disappears as soon as it appears at the reset input R of the D flip-flop 240 after the next primary clock pulse has been supplied via the line 201.

3A, the Q output signal of the J-K flip-flop 235 is fed to the reset inputs R of the counter circuits of the counter 162 in FIG. 3B. The counter device 162 includes two binary rapid transfer counters 258 and 259 and an AND circuit 260. The two counters 258 and 259 are reset by the Q output signal of the J-K flip-flop 235 of the start-inhibit circuit. If the J-K-FIip-Flop 235 is actuated, the reset signal normally present at the reset inputs R of the counters 258 and 259 is thereby canceled in order to cause the counting device 162 to start a counting process.

The primary clock pulses appearing on line 201 arrive at the clock input CL of counter 259, and the output signals appearing at outputs Q5, Q9 and Q12 are applied to shift register 165 (FIG. 3B), search block circuit 166 (FIG. 3C). and supplied to the clock input CL of the counter 258. Thus the outputs of counter 259 appear on line 201 at a frequency corresponding to part of the clock frequency; if e.g. B 'the clock frequency is about 6.82 kHz, so that the clock signals have a period length of about 0.1466 ms, the period of the pulses appearing at output Q5 is about 4.69 ms, the period of the output signals at output Q9 is about 75 , 07 ms and the period of the output signals at the output Q12 is about 600.58 ms.

The output Q1 of the counter 258 is connected to one input of the AND circuit 260, and the output Q4 of the counter 258 is at the other input of this AND circuit. Since the counter 258 receives its clock pulses via the output Q12 of the counter 259, the signals of the outputs Q1 and Q4 of the counter 258 appearing at the output of the AND circuit 260 alternate between an L- and an H- with a period of 5405.28 ms. Value. As will be explained, the data pulses arriving at the reed switch 215 are received at the output Q5 of the counter 259, the period length being 4.69 ms. Therefore, the signal state changes at the output of AND circuit 260 when 1152 data pulses have appeared after the counters have been enabled to perform a count to actuate stop-lock circuit 167, which is described below with reference to FIG. 3B becomes.

In operation, the circuitry first looks for a pulse train corresponding to the access keyword, which is supplied via the reed switch 215. A data detection circuit 270 shown in FIG. 3B with a shift register 165 and a data detection NAND circuit 172 serves this purpose. The output Q5 of the counter 259 is connected to the clock input CL of the shift register 165. The one according to FIG. 3A is due to the monostable pulse generator 151 generated data pulses are supplied to the data input D1 of the shift register 165 via the NAND circuit 156. These data pulses are input to shift register 165 at the frequency of the pulses appearing at the Q5 output of counter 259. If the pulses transmitted to the circuit do not have the same frequency as those appearing at the output Q5 of the counter 259, then these data pulses are not properly input to the shift register 165 and are provided by the data detection NAND circuit described below 172 not recognized. This necessity to maintain a clock frequency therefore means that a certain frequency must be observed for the data pulses to be entered, in addition to the other requirements, in particular the sequence of H and L signals, which reduces the statistical probability of incorrect operation of the main parameter controller is further reduced.

If the data pulses are input to the shift register 165, they appear at the associated outputs Q1 to Q7, which are connected to the inputs of the NAND circuit 172. If necessary, certain outputs

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of the shift register 165 can be provided with inverters 272 and 273, so that there is the possibility of clearly coding the required detection pattern of the circuit.

The NAND circuit 172 generates an L output signal only if all of them carry H signals at the same time. Thus, the output signals of shift register 165 only change the state of the output of NAND circuit 172 if they correspond to a predetermined access keyword. The output of NAND circuit 172 is inverted by an inverter 274 to then be applied to an input of NAND circuit 174 of FIG. 2.

After a period of time passes to detect the access data pulses, the circuit is blocked by the search inhibit circuit 166 (FIG. 3C) to prevent the data search from continuing. The search blocking circuit 166 includes a J-K main servo flip-flop 276, to which the output signal of the counter 259 is supplied as a clock signal. The K input of the J-K flip-flop 276 is held on an L voltage lever, while the J input receives the signal appearing at the Q output. Thus, when a clock pulse arrives at the clock input, the signal at output Q transitions from its normal L value to an H value, which it maintains until the J-K flip-flop 276 is reset. Output Q is connected to the other input of NAND circuit 174 to prevent further transmission of signals from data detection circuit 270. Since the clock signal of the J-K flip-flop 276 is taken from the output Q9 of the counter 259, the search inhibit circuit 166 is actuated as soon as approximately 37.55 ms have elapsed after the actuation of the start inhibit circuit 152. This corresponds to a period which comprises eight data bits which are transmitted at the frequency determined by the signal at the output Q5 of the counter 259. Thus, if the search for the access keyword is started and if the access keyword is not recognized within the first eight pulses, the circuit ends the search and does not accept any further data pulses until the time required for a complete programming cycle has expired.

If the access keyword is recognized, immediately before the search inhibit circuit 166 is actuated, the output signal of the data recognition circuit 270 is forwarded via the NAND circuit 174 and, as shown in FIG. 3C, is supplied to the enable circuit 176 to which a main JK servo -Flip-flop 280 is heard, the K input of which is kept at an L voltage level, and whose output Q is connected to the J input. The signal coming from the data detection circuit 270 is fed to the clock input CL. As soon as the release pulse sequence is recognized, the release circuit 176 thus makes an H signal appear at its output Q, which remains until the J-K flip-flop 280 is reset. The Q output of J-K flip-flop 280 is connected to an input of NAND circuit 170 to control the transmission of the data pulses passing through NAND circuit 156. In addition, the output Q of the JK flip-flop 280 is connected to an input of the AND circuit 180 so that the signal in question can be compared with the output signal of the stop-lock circuit 167 in the manner to be described with reference to FIG. 3B . As soon as the state of the enable circuit 176 changes when the access pulse sequence is recognized, the data pulses are thus fed from the J-K flip-flop 280 according to FIG. 3C to the data counter 182.

The data counter 182 includes a rapid transmission counter 291. The data pulses are fed from the monostable pulse generator 151 according to FIG. 3A to the clock input CL of the counter 291. When the data pulses are entered into the counter 291, the signal states at the outputs Q1 to Q10 correspond to the number of pulses received. It should be noted that the output signal appearing at outputs Q1 to Q10 is the binary equivalent of the number of pulses received via the clock input,

where the most significant bit appears at output Q10.

The data pulses appearing in lines Q1 to Q8 of counter 291 are fed directly to data memory 184 according to FIG. 3C. The data memory 184 includes a data latch circuit 195 and two D-type flip-flops 290 and 292 for storing the supplied signals. The various outputs Q1 to Q8 of the counter 291 are connected to the various data inputs of the data blocking circuit 295, the control input ST of which is connected to the output of the AND circuit 180 which, as mentioned above, receives the input signals according to FIG. 3B from the outputs the stop-blocking circuit 167 and, according to FIG. 3C, are supplied by the release circuit 176. The outputs Q9 and Q10 of the counter 291 are connected to the associated D inputs of the D flip-flops 290 and 292. The Q outputs of the D flip-flops 290 and 292 make two further control data signals appear at the points EE and FF.

According to FIG. 3B, the stop-blocking circuit 167 includes two flip-flops 300 and 301 of the D type. The primary clock pulses appearing on line 201 arrive at the clock input CL of the D flip-flop 301, and the outputs Q1 and Q4 of the counter 258 are connected in the manner described to the clock input CL of the other D flip-flop via the AND circuit 260. Flops 300 connected. An H signal is present at the D input of flip-flop 300, and output Q is connected to input D of D flip-flop 301. The output Q of the D flip-flop 301 is connected to one of the inputs of the AND circuit 180 and to the reset input R of the D flip-flop 300.

If all data pulses have been received which are received by the circuit arrangement within the time period which is determined by the change in the temporal coincidence of the state changes at the outputs Q1 and Q4 of the counter 258, the stop-blocking circuits 167 and the generate according to FIG. 3C Enable circuit 176 a signal which is fed to the control input ST of the data blocking circuit 295 in order to enter the data pulses appearing at the data inputs. Thereafter, these data pulses remain stored in the data latch circuit until another set of signals, including the correct access keyword, is applied to the circuit. The signals picked up by the data blocking circuit 295 are then available to be supplied to various circuits by means of which the operating parameters of the pacemaker to which the described circuit belongs can be changed.

FIG. 4 shows further details of the circuit of the pulse generator 21 according to FIG. 1. This pulse generator, which operates as a voltage multiplier, includes two npn transistors 310 and 311. The collector and the emitter of the transistor 311 switch one side of a capacitor 313 via a further capacitor 314 in series with output line 22. A resistor 316 connects the base of transistor 311 to a negative voltage terminal 190, and another resistor 322 connects the collector of transistor 311 to ground 191 to connect the collector-base junction of transistor 311 in to bias the opposite direction.

The side of the capacitor 313 connected to the emitter of the transistor 311 is also connected to the negative voltage terminal 190 via a resistor 318. The other side of capacitor 313 is with the collector of transistor 310 and through a resistor 320

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connected to ground 191. The emitter of transistor 310 lies directly at the negative voltage connection 190. If the transistors 310 and 311 are in their normal non-conductive state, then the capacitor 313 according to FIG. 4 is caused by the voltage between the negative voltage connection 190 and ground 191 via the resistors 318 and 320 charged.

If the transistor 310 is biased in a manner yet to be explained in order to be made conductive, the negative voltage present at its emitter is applied to the previously charged capacitor 313, whereby the ground-related voltage at the emitter of the transistor 311 is multiplied . In addition, this increased negative potential biases the base-emitter junction of transistor 311 in the forward direction, so that the transistor becomes conductive and supplies the voltage multiplied in the manner described to output line 22.

Between the output line 22 and ground 191 there is a zener diode 324 for protection against defibrillation voltages and other potentially undesirable high voltages.

As described above, the generation of stimulation pulses is controlled by supplying a base current to transistor 310. This base current is generated in an ohmic conduction path that runs between the base of transistor 310 and the output of a NAND circuit 327. The input signal to NAND circuit 327 is taken from the output of pulse width control circuit 17 of FIG. 1 in a manner to be described.

The resistance of the conduction path and thus also the base current of the transistor 310 is determined by the amplitude control circuit 24, to which the three resistors 326, 329 and 330 belong. The resistors 329 and 330 are connected in parallel, and they are also connected in parallel with the resistor 326 via binary switches 332 and 333, to which digital actuation signals are supplied from the data blocking circuit 295 of the main parameter controller 150 according to FIG. 3C via the lines II and JJ . Thus, if a logic signal "00" is present on lines II and JJ during operation, the entire resistance value of resistor 326 is applied to determine the base current of transistor 310. If the logical signal “01” appears in lines II and JJ, switch 332 is closed, so that resistors 329 and 326 connected in parallel determine the resistance of the line path. The appearance of the logic signal "10" on lines II and JJ causes the switch 333 to be closed in order to bring the parallel-connected resistors 330 and 326 into effect in the base circuit of the transistor 310. Finally, the appearance of the logic signal "11" on lines II and JJ causes both switches 332 and 333 to be closed in order to connect all three resistors 329, 330 and 326 in parallel. Thus, the collector-emitter current of transistor 310 is determined by the logic signal appearing on lines II and JJ, respectively.

The extent to which transistor 310 is made conductive by the logic signal appearing on lines II and JJ determines the amplitude of the output pulse delivered to output line 22. In other words, the voltage drop between the collector and emitter determines the voltage that is added to the voltage previously applied to capacitor 313.

The output line 22, via which stimulation pulses are emitted from the pulse generator 21 in the manner described, also serves to supply heart pulses generated in a natural way to the detector part of the pacemaker 10 via the line 33 according to FIG. 1. 4

a resistor 340 and a capacitor 341 are connected in series in line 33, and this line is connected to a non-inverting input of an operational amplifier 343. Resistor 340 and capacitor 341 serve to supply the signal to the input of the operational amplifier, and at the same time act as a low frequency filter, capacitor 341 providing a high resistance to the low frequency components of the signal appearing on line 22. A diode 344 is connected between resistor 340 and capacitor 341 and is connected to ground 191 in order to limit the amplitude of the stimulation pulse to an acceptable voltage so that amplifier 343 is not overloaded.

A resistor 346 is connected in series with a capacitor 347 between ground 191 and the inverting input of operational amplifier 343. A feedback resistor 349 is located between the output of amplifier 343 and its inverting input. Resistor 346 and capacitor 347 also act as a low-frequency filter with respect to the signal appearing at the output of operational amplifier 343. There is also a forward compensation capacitor 350 to determine the upper frequency cut-off point at the upper level of 3 db. Finally, the non-inverting input of amplifier 343 is connected to a voltage divider, which includes two resistors 352 and 353 connected in series between negative voltage terminal 190 and ground 191. An offset trimming resistor 355 lies between ground 191 and an offset connection of amplifier 343. The output of amplifier 343 is connected to the control electrode of a field effect transistor 356 in order to control the source-drain current. Thus, upon arrival of a naturally generated cardiac pulse or other signal with similar frequency characteristics, amplifier 343 generates an output voltage to control field effect transistor 356. The extent to which the field effect transistor 356 becomes conductive naturally depends on the level of the output voltage of the amplifier 343, which in turn is determined by the amplitude of the signal received by the line 22.

The sensitivity of the pacemaker 10 for signals generated by the R-wave amplifier 32 is determined by the sensitivity control circuit 35 according to FIG. 1, to which according to FIG. 4 belongs a NAND circuit 358, the inputs of which to the output GG of the data storage / data blocking circuit 295 (Fig. 3C) are connected. The output of the NAND circuit 358 is connected to the control input of a binary switch 359 to which a Schottky diode 361 is connected in parallel.

Another output HH of the data blocking circuit 295 (FIG. 3C) is connected to a second binary switch 362, to which a silicon diode 364 is connected in parallel. The anode of Schottky diode 361 is connected to ground 191 and the cathode of silicon diode 364 is connected to the source of field effect transistor 356. A resistor 365 is located between the drain electrode of this transistor and the negative voltage connection 190, so that there is a current conduction path from ground 191 via the diodes

361 and 364, the source and drain electrodes of the field effect transistor 356 and the resistor "365 extends to the negative voltage terminal 190. Since the Schottky diode 361 and the silicon diode 364 have forward resistances of the order of 0.2 and 0.7 ohms, the current that flows through resistor 365 when transistor 356 is conductive can be determined by one or the other of binary switches 359 and

362 or none of these switches is actuated, or that both switches are actuated. Appears e.g. B. the logical signal

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"00" at the connections GG and HH, the switch 359 is actuated, while the switch 362 remains ineffective, so that a current conduction path from ground 191 runs via the switch 359 and the diode 365 to the source electrode of the transistor 356. When the logic signal “Ol” appears at the connections GG and HH, both switches 359 and 362 are actuated, so that the two diodes 361 and 364 are bridged in the current conduction path between ground 191 and the source electrode of transistor 356. A logic signal “10” appearing at the connections GG and HH switches off both switches 359 and 362, so that the current conduction path from ground 191 via the two diodes 361 and 364 to the source electrode of transistor 356. Finally, when a logical signal “11” appears at the connections GG and HH, the switch 359 is switched off and the switch 362 is switched on, so that a current conduction path from ground 191 extends via the diode 361 and the switch 362 to the source electrode of the transistor 356. By supplying appropriate logic signals to the terminals GG and HH, it is thus possible to change the potential applied to the source electrode of the field effect transistor 356 as required in order to determine the voltage level at which the transistor 356 is switched on. When this happens, a voltage appears at the resistor 365, which is fed to an input of an arrangement with two inverters 370 and 371 in order to arrive at the control counter 38 according to FIG. 1.

The control counter 38, the refractory period controller 43, the reset circuit 41 of the asynchronous interval generator 15, the interval generator 15 itself, the asynchronous frequency control circuit, and the pulse width control circuit 17 of Fig. 1 are shown in further detail in Figs. 5A and 5B. The arrangement according to FIGS. 5A and 5B are supplied via line 14 with pulses which correspond to the primary clock pulses of the clock generator 12 after their first division by 4. "

5A is fed to the reset input 2 of the control counter 38 via the line connection Z, so that the control counter receives a reset signal as soon as a corresponding signal is detected by the R-wave amplifier 32. The clock pulses divided for the first time from the line 14 are fed to an input of the NAND circuit 40, the output of which is connected to the clock input CL of the control counter 38, which is a rapid transmission counter which emits signals to its various outputs which each correspond to a predetermined number of clock pulses supplied by its clock input. As mentioned, the main task of the control counter 38 is to determine a refractory state or a control interval during which the arrival of a naturally generated heart pulse does not lead to a reset, and after the arrival of such a pulse the generation of a reset pulse causes, which indicates that the heart is working properly. The control counter 38 has two output lines to choose from, one of which is connected as a line 373 to the output Q9 and the other as a line 374 via an AND circuit 376 to the outputs Q7 and Q10. The signals appearing on lines 373 and 374 represent a change in state which corresponds to 256 clock pulses (29: 2) or 576 clock pulses (210 + 27: 2).

The pulses appearing in line 14 with a length of approximately 0.587 ms generate state changes in lines 373 and 374 after 150.15 and 337.83 ms, respectively. There is thus a choice between the times of the state changes in lines 373 and 374 for determining the refractory period of the pacemaker. The

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The choice between the signals in the two lines is effected by a multiplexer 377. Line 373 is connected to input 0 and line 374 to input 1 of multiplexer 377. The input A of the multiplexer is connected to the output Q8 or the connection NN of the data blocking circuit 295 (FIG. 3C), so that the relevant signal is fed to the multiplexer. The value table of multiplexer 377 is such that when a 0 signal is fed to input A, the signal fed to input O is fed to output line 379. The supply of a 1 signal to input A causes the signal from input 1 to be fed to output line 379. Thus, the signal appearing at output Q8 of data latch circuit 195 (FIG. 3C), which represents the refractory control signal, determines whether the refractory period of the circuit is 150.14 ms in length or in accordance with the signal in line 373 line 374 should have a length of 337.83 ms. The output signal of the multiplexer 377 is fed via the output line 379 to an inverting NAND circuit 45, the output of which is connected to the reset circuit 41 of the asynchronous interval generator 15 and to one of the inputs of the NAND circuit 40 on the input side of the control counter 38. As soon as the control counter 38 is reset during operation, it starts counting the clock pulses supplied to its clock input via the NAND circuit 40. When the predetermined counting result on the selected output line 373 or 374 is reached, an output signal is output to the output line 379, which leads to the inverting NAND circuit 45, so that in the output line 382 the NAND circuit instead of the normally present H signal an L signal occurs. As soon as this happens, the NAND circuit 40 is blocked, so that no further clock pulses are supplied to the control counter 38 and the counting process is ended. Thus, the control counter 38 only continues to count when it is reset by a pulse subsequently supplied to it via the R-wave amplifier 32.

In addition to the output signals appearing at the outputs Q9, Q7 and Q10, an output signal appears at the output Q4 of the control counter 38, which is fed to the switchback 41 of the asynchronous interval generator 15 in the manner described below.

5A includes two D-type flip-flops 384 and 385. The D input of the D flip-flop 384 is held high and the Q output is connected to the D input of the D flip-flop 385. The output Q of the D flip-flop 385 is connected to the reset input R of the D flip-flop 384, and at the output Q of the D flip-flop 385 the output signal of the reset circuit 41 appears, which is an input to FIG. 5B NAND circuit 30 is to be supplied. The output signal of the NAND circuit 45, which represents the signal for the selected refractory period, is fed via line 382 to the clock input CL of the flip-flop 384. The output signal appearing at the output Q4 of the control counter 38 arrives at the clock input CL of the second D flip-flop 385. If the control counter 38 is reset during operation, it starts a counting process in which it achieves a first count result in order to obtain an output signal via the Output Q4 and thereby pass on the H signal at input D of D flip-flop 384 to input D of D flip-flop 385. When the control counter 38 then reaches the count result on the selected output line 373 or 374, a clock signal is supplied to the clock input CL of the flip-flop 385 in order to cause a change in state at the outputs, so that an H instead of an L signal at output Q Signal and on off 9

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gang Ö an L signal appears instead of an H signal. The transition of the output signal at the output Q from H to L, which acts on the NAND circuit 30 according to FIG. 5B, forms the reset signal which is fed to the asynchronous interval generator 15 according to FIG. 5B in order to reset it.

If a reset signal arrives at the reset input R of the control counter 38 before the counting result corresponding to the selected output line 373 or 374 has been reached, the control counter is reset so that a completely new counting process is started without the D flip-flop 385 emits an output pulse. This reset state can be extended as long as z. B. an interference signal is caused to constantly reset the control counter 38 within the refractory period determined by the main parameter controller 150. As soon as the predetermined counting result has been reached, however, the D flip-flop 385, which has previously been prepared by the output signal of the control counter 38 supplied to it via the output Q4, generates a reset signal at its output Q.

At this point it should be noted that the generation or non-generation of a reset signal with the aid of the asynchronous generator reset circuit 41 controls the demand operation of the entire pacemaker 10. Is z. B. generates no reset signal, the asynchronous interval counter 15 can continue the counting process continuously to generate stimulation signals with the selected predetermined frequency.

5A, there is a NAND circuit 387, the output of which is connected to the reset input R of the D flip-flop 385. One input of this NAND circuit is connected to inverter 216 (FIG. 3A). The other input of NAND circuit 387 (FIG. 3C) is connected to output Q of D flip-flop 292 via connection FF. 3A, for example by closing a magnet for test purposes or the like, the NAND circuit 387 generates an H output signal so that the D flip-flop 385 is continuously supplied with a reset signal to the Disable generation of reset pulses and cause pacemaker 10 to operate asynchronously. In addition, the presence of an O signal at the Q output of the D flip-flop 292 via the FF terminal also results in the generation of a constant reset voltage at the output of the NAND circuit 287 to force the pacemaker 10 to run asynchronously or at a fixed rate work.

The signal supplied to the NAND circuit 30 from the asynchronous generator reset circuit 41 in the manner described is fed according to FIG. 5B via a line 388 to a reset input of the asynchronous interval generator 15, which is designed as a fast transmission counter and via line 14 and its clock input CL Clock pulses are fed to let output signals appear at the various outputs. In the exemplary embodiment shown, the output signals are output via the outputs Q6-Q12. These output signals are logical combinations of selected output signals, wherein one signal can be selected in each case in order to determine the asynchronous interval frequency of the pacemaker 10. More precisely, the signals of the counter 15 which are output to the outputs Q7, Q9 and Q10 are combined with one another by an AND circuit 390 in order to bring about a change in state after approximately 489.41 ms. The output signal of the AND circuit 390 is fed to the input 7 of a multiplexer 391. The output signals of the outputs Q6, Q8, Q9 and Q10 are combined by an AND circuit 393, so that the output signal is changed after approximately 544.29 ms. The output of the AND circuit 393 is connected to the input 6 of the multiplexer 391. The exit

QU of the counter 15 is connected directly to the input 5 of the multiplexer by a line 394 and carries a signal, the state of which changes after approximately 600.58 ms. The output signals of the terminals Q8 and QU are linked by an AND circuit 395, the output of which is connected to the input 4 of the multiplexer 391 and at which a change in state occurs after approximately 675.66 ms. The output signals of the outputs Q9 and QU are linked by an AND circuit 396, the output of which is connected to input 3 of the multiplexer and at which a change in state occurs after approximately 750.73 ms. The signals of the outputs Q8, Q9 and QU are through an AND circuit

397 linked, the output of which is connected to input 2 of the multiplexer, and at which a status change occurs after approximately 825.81 ms. The output signals of the outputs Q8, Q10 and QU are through an AND circuit

398 linked, the output of which is at input 1 of the multiplexer, and at which a change in state is caused after approximately 975.96 ms. Finally, the output Q12 of the counter 15 is connected directly to the input 0 of the multiplexer by a line 399, and here a change in state occurs after approximately 1201.17 ms.

The control connections A, B and C of the multiplexer 391 are connected via the connections KK, LL, MM to the (FIG. 3C) outputs Qs, Q6 and Q7 of the data blocking circuit 295. The control signals that determine which of the inputs 0-7 of the multiplexer 391 is connected to the output line 400 are shown in the table of values below.

A B C on

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Thus, the time after which an output signal appears in one of the various lines of the multiplexer is chosen by supplying a logic signal to the inputs of the multiplexer, and therefore the asynchronous frequency of the pacemaker 10 can be selected

that you choose one of the periods mentioned above.

The output signal of the multiplexer 391 output on the line 400 is supplied to the pulse width control circuit 17 in the manner shown in FIG. 5B as follows: The pulse width control circuit 17 includes two JK main servo flip-flops 402 and 403. Am Input J of JK flip-flop 402 has an H signal level, while an L signal level is present at input K. The outputs Q and Q of the J-K flip-flop 402 are connected to the inputs J and K of the J-K flip-flop 403. The Q output of the JK flip-flop 403 is connected to the reset input R of the JK flip-flop 402, and the Q output of the JK flip-flop 403 forms the output of the pulse width control circuit 17. The signal on the output line 400 of the multiplexer 391 forms the clock signal for the JK flip-flop 402 which, when a clock signal occurs, causes an H signal to appear at the Q output and an L signal at the Q output. The output signal of a multiplexer circuit to be described for determining the pulse width is fed to the clock input CI of the J-K flip-flop 403 in order to pass on the input signal at the inputs J and K to the outputs Q and Q. More specifically

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For the first time, the multiplexer 405 is supplied with divided clock pulses from line 14 via input 0. In addition, this multiplexer receives twice divided clock pulses at its input 1 with a second partial frequency from the D flip-flop 204 (FIG. 3A) via the line 208 and the connection BB. The signal from the output Q of the D flip-flop 290 (FIG. 3C) is fed to the control input A of the multiplexer via the connection EE for regulating the pulse width. Depending on whether the signal at control input A is an H or an L signal, either the input 0 or the clock signal present at input 1 is output via output line 406 to clock input CL of J-K flip-flop 403. The selection of the clock pulses with the lower frequency leads to a longer change in state at the output Q of the JK flip-flop 403 than the selection of the clock pulses of higher frequency at the input 0 of the multiplexer 405, so that there is a possibility of changing the width of the stimulation pulses of the pacemaker to regulate. A line 408 is connected to the output Q of the J-K flip-flop 403 so that a drive signal can be fed to the pulse generator 21 (FIGS. 1 and 4). From the output Ö of the J-K flip-flop 403, the output signal is also fed to an input of the NAND circuit 30, so that this signal forms an additional reset signal for the asynchronous interval generator 15. Thus, when an asynchronous signal is generated, the asynchronous interval generator is reset so that it starts measuring the next asynchronous interval.

The outer, generally designated 500, command generator for generating and transmitting the access keyword and the pulses for determining the parameters of the pacemaker 10 is shown in FIGS. 6A to 6D. The connections between the individual figures are designated by corresponding letters. In contrast to the implanted pacemaker 10 described with reference to FIGS. 1 to 5, the circuit arrangement according to FIGS. 6A to 6D is designed such that the ground potential is a logic O or L signal and the voltage + V is a logic 1- or H signal corresponds.

The outer command transmitter 500 includes four main parts, each of which is enclosed in dashed lines in the drawing. A clock pulse generator 501 shown in FIG. 6B supplies the remaining parts of the command generator with clock pulses. An access keyword generator 502, also shown in FIG. 6B, generates a certain sequence of pulses to make the main parameter controller 150 (FIGS. 1 and 3A to 3C) accessible. 6C, there is a parameter keyword generator 503 that generates a controllable number of pulses, each number corresponding to a particular set of selectable pacemaker parameters. Finally, there is a pulse transmission circuit 504 shown in FIG. 6D which generates electromagnetic pulses which are transmitted to the main parameter controller 150 in accordance with the signals of the access keyword generator 502 and the parameter keywords generated by the parameter keyword generator 503.

6B, the clock pulse generator 501 is started by closing the start switch 507 (FIG. 6A). If the start switch 507 is moved from its upper position (contact 508) to the lower position (contact 509), a transition from an L signal to an H signal is brought about on the output line 510 of an anti-bounce circuit, designated 512 as a whole. When the start switch 507 returns to the upper position (contact 508), an L signal appears on the line 510 instead of an H signal, and this triggers a monostable multivibrator 515, which is connected to the in a manner yet to be explained

Line 525 outputs a reset signal for the various circuit elements of the command transmitter and then a start pulse.

Bounce prevention circuit 512 also includes two NAND circuits 516 and 517, and monostable multivibrator 515 is switched such that it can no longer be triggered after it has received a first trigger signal.

An input of the NAND circuit 516 is connected via a resistor 519 to a positive voltage connection 520, so that an H signal is normally present here. This input is also connected to the contact 508 of the start switch 507. The other input of NAND circuit 516 is connected to the output of NAND circuit 517. Accordingly, an input of the NAND circuit 517 is connected via a resistor 521 to the positive voltage connection 520 and to the contact 509 of the start switch 507. The other input of NAND circuit 517 is connected to the output of NAND circuit 516. The output of the NAND circuit 517 forms the output of the anti-bounce circuit 512 and is connected to the monostable multivibrator 515.

The monostable multivibrator 515 is triggered by a negative going pulse edge that changes from H to L. When such a change of state occurs, an H signal appears at the output Q instead of an L signal, which is retained for a time determined by the resistor 523 and a capacitor 524, which is between the RC connection and the C connection of the multivibrator 515 lies. The R terminal is connected to the positive voltage terminal 520. The positive trigger input 4- Tr is connected to the output Q so that the monostable multivibrator 515 can be triggered by the negative going pulse edge so that it cannot be triggered again.

If a negative going signal is fed to the negative trigger input —Tr of the multivibrator 515, an H signal appears at the output Q instead of an L signal, during which a reset signal is fed to the various circuit elements via line 525 in the manner described below to determine an output state in these circuit elements. After the H signal has been present at the output Q of the multivibrator 515 for the time which depends on the time constant determined by the capacitor 524 and the resistor 523, the H signal changes to an L signal. This change in state triggers a second monostable multivibrator 527 (FIG. 6B), which outputs a signal to a J-K main servo flip-flop 528 serving as a start blocking circuit.

The monostable multivibrator 527 is connected in a similar manner to the monostable multivibrator 515, so that it is triggered by a negatively directed pulse which is supplied to the negative trigger terminal -Tr for a period of time which, after the RC time constant, is applied to the terminals RC and C connected capacitor 530 and a resistor 531 connected to the connections R and RC. In addition, the R terminal is connected to the positive voltage terminal 520. The positive trigger input + Tr is connected to output Q so that the monostable multivibrator 527 cannot be triggered again.

The J and K inputs of the J-K flip-flop 528 (FIG. 6B) are held at the L voltage level together with the clock input CL. Set input S is connected to the output of monostable multivibrator 527 and the output signal is taken from output Q. The reset input R is connected to the output of a monostable multivibrator 532 serving as the main stop circuit5

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sen that generates a pulse in a manner yet to be explained when the command generator 500 ends the pulse generation process. The signal output to the output Q of the J-K flip-flop 528 is fed via line 534 as an enable signal to the clock pulse generator 501.

The clock pulse generator 501 includes a 14-stage binary high-speed transfer counter serving as an oscillator, which is referred to below as the oscillator counter 536, a decade counter 537 and three NAND circuits 539, 540 and 541. The oscillator counter 536 and the decade counter 537 are Reset inputs R connected to the aforementioned reset line 525. Input 0 for clock signals and input i> for inverted clock signals are connected to one another via a capacitor 543 and a fixed resistor 544 connected in series therewith and a variable resistor 545. A second fixed resistor 547 is connected on the one hand to the node between the capacitor 543 and the resistor 544 and on the other hand to an input of the NAND circuit 539. The other input of NAND circuit 539 is connected via line 534 to output Q of start inhibit circuit J-K flip-flop 528. The output Q8 of the oscillator counter 536 is connected to an inverting NAND circuit 540 to supply clock pulses to the access keyword generator 502 to be described.

The clock signals appearing at the output Q9 of the oscillator counter 536 have a frequency which corresponds to the inner clock frequency of the pacemaker, with which the received pulses of the access and parameter keywords are input to the various registers. These inner clock signals are tapped (FIG. 3B) at the output Q5 of the counter 259.

The output Q9 of the oscillator counter 536 is connected to the clock input CL of the decade counter 537 and an input of a NAND circuit 541. The output of NAND circuit 541, at which signals appear which represent clock pulses at output Q9 of oscillator counter 536, is connected (FIG. 6C) to an input of a NAND circuit 577 and to the clock input CL of counter 558. The output 6 of the decade counter 537 is connected to the enable clock input so that the decade counter is blocked when the counter reading 6 is reached. The output 6 of the decade counter 537 is also connected to a further input of the NAND circuit 541 and to the various set and reset inputs of the parameter keyword generator 503, which will still be described with reference to FIG. 6C.

During operation, the clock pulse generator 501 generates pulses as long as an H signal is present on line 534. However, as soon as an L signal is present on line 543, no change can occur at clock input 0 of oscillator counter 536, so that the generation of output pulses is ended. The decade counter 537 is used to

after generating the access keyword and issuing it via the output, to switch from the output of the access keyword generator 502 to the parameter keyword generator 503 (FIG. 6C), so that its output signal is output. This is done with the aid of the NAND circuit 541, which serves to choose between the output signal of the access keyword generator and the subsequent pulse sequence of the parameter keyword. Before the decade counter 537 reaches the counter reading 6, an L signal is thus fed to the input of the NAND circuit 541 via the output 6 of the decade counter 537, so that the transmission of the clock pulses from the output Q9 of the oscillator counter 536 is blocked. Therefore, the input signal to the NAND circuit 555 maintains an H signal due to the parameter keyword, so that only the access keyword generated by the access keyword generator 502 is output via the output line 556. As soon as the decade counter 537 reaches the counter reading 6, the clock pulses appearing in the line Q9 of the oscillator counter 536 can pass the NAND circuit 541 in order to pass via the output line 556 and the NAND circuits 577, 578 (FIG. 6C) and 555 ( 6B) to be delivered. The H signal present at the output 6 of the decade counter 537 constantly acts as a reset signal on the JK flip-flop 551 of the access keyword generator 502, so that an H signal is constantly present at the associated output Q, so that the parameter keyword pulse sequence in the way to NAND circuit 555 described below.

The access keyword generator 502 includes three main J-K servo flip-flops 550, 551 and 552. The J and K inputs of the J-K flip-flop 550 are connected to the Q output of the J-K flip-flop 552. Outputs Q and Q of JK flip-flop 550 are connected to inputs J and K of JK flip-flop 551, and outputs Q and Q of JK flip-flop 551 are connected to inputs J and K of JK -Flip-flops 552. The reset inputs R of the JK flip-flops 550 and 552 and the set input S of the JK flip-flops 551 are connected to the reset line 525. The set inputs S of the JK flip-flops 550 and 552 and the reset input R of the JK flip-flops 551 are at the output 6 of the decade counter 537. The output signal of the access keyword generator 502 is via the output Q of the JK flip-flop Taken from flops 551. Thus, during operation, the J-K flip-flops 550 and 552 are actuated by the signal supplied via the reset line 525. When clock pulses from the clock pulse generator 501 arrive, the logic sequence 1000010 appears at the output Q of the JK flip-flop 551 with a frequency which corresponds to half the frequency of the signal at the output Q8 of the oscillator counter 536 and is equal to the signal frequency at Q9 is.

The output Q of the J-K flip-flop 551 is connected to an input of the NAND circuit 555. Assuming that an H signal is present at the other input of this NAND circuit, which, as explained below, is the case until the decade counter 537 reaches the counter reading 6, the output signal inverted to 1000010 appears on line 556, that is inverted again by the transmitter coil described below.

As mentioned, the monostable pulse generator 151 of FIG. 3A, which belongs to the main parameter controller 150, only generates an output pulse if an H signal appears at its input instead of an L signal. Therefore, the keyword generated by the pulse generator 151 in response to a transmitted digital signal of the form 0100010 takes the form 1000010. This is exactly the key word that is recognized by the access key word detection circuit 270.

The parameter keyword generator 503 of FIG. 6C includes a 12-stage fast transfer counter 558, four binary decimal decimal decoders 559, 560, 561 and 562, two inverting NAND circuits 564 and 565, a NAND circuit 566 with at least six inputs as well a JK main servo flip-flop 567. Clock 55 is supplied to counter 558 from the output of NAND circuit 541 (Fig. 6B); this is the clock frequency of the oscillator counter 536 divided by 29. The reset line 525 is connected to the reset input R, and the outputs Q1-QII are connected to an externally controllable parameter selection circuit described below. The output Q12 is connected to the monostable multivibrator 532 (FIG. 6B) serving as the main stop circuit

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bound, which is used to turn off the oscillator counter 536 after the parameter keyword counting has ended. The outputs Q1 and Q2 of counter 558 are connected to inputs A and B of decoder 559. The inputs C and D of the decoder are grounded so that an L signal is present at them. 6C, there is a switch 570 with four switch positions, the switch contacts of which are connected to the connections 0.1, 2 and 3 of the decoder 559. The movable contact of switch 570 is at one of the six inputs of NAND circuit 566.

The outputs Q3 and Q4 of the counter 558 are connected to the inputs A and B of the decoder 560, at whose inputs C and D there is an L signal, since these are grounded. The outputs 0, 1, 2 and 3 of the decoder 560 are connected to the corresponding switch contacts of a four-position switch 571, the movable contact of which is connected to a further input of the NAND circuit 566. The outputs Q5-Q8 of the counter 558 are at the inputs A, B, C, D of the decoder 561. The outputs 0-7 of this decoder are connected to the associated switch contacts of a switch 572 with eight switch positions, the movable contact of which is also connected to an input is connected to the six input NAND circuit 566. The output Q9 of the counter 558 leads to the input A of the decoder 562, whose inputs B, C, D are grounded, so that an L signal is present here. The outputs 0-3 of the decoder 562 are connected to four associated switch contacts of a switch 573, the movable contact of which is connected to a further input of the NAND circuit 566. The output Q10 of the counter 558 is connected to an input of an inverting NAND circuit 564, which is shown schematically only as an inverter, and to a switch contact of a switch 574. The output of the NAND circuit 564 is connected to the other switch contact of the switch 574. The movable contact of switch 574 is connected to another input of NAND circuit 566. The output QU of the counter 558 is connected to the inputs of an inverting NAND circuit 565, also shown only as an inverter, and to a switch contact of the switch 575. The output of the inverting NAND circuit 565 leads to the other switching contact of the changeover switch 575. The movable contact of this switch is connected to the sixth input of the NAND circuit 566.

The output of the NAND circuit 566 is connected to the clock input of the JK main servo flip-flop 567, at whose input there is an L signal and whose K input is an H signal, and whose output Q is connected to an input of the NAND circuit 577 is connected.

The output Q12 of the counter 558 is connected to the multivibrator 532 (FIG. 6B) of the main stop circuit.

In operation, the various switches 570 to 575 are set according to a predetermined set of operating parameters of the pacemaker. For example, in the present case, switch 570 is associated with the sensitivity parameter of the pacemaker and can be set to each of the four outputs of the associated decoder 559. Similarly, switches 571, 572, and 573 are associated with the outputs of decoders 560, 561, and 562 to determine the pacemaker's pulse amplitude, pulse rate, and refractory period. Switches 574 and 575 can be adjusted to determine the pulse width and mode of the pacemaker. If a signal corresponding to a selected decimal number is present at each of the outputs Ql-Qll of counter 558, namely 0-3 for switch 570, 0-3 for switch 571, 0-7 for switch 572, 0-3 for the switch 573, the on or off state of the switch 574 or the on or off state of the switch 575, an H signal is present at all inputs of the NAND circuit 566, so that an L signal appears at the output of this NAND circuit . Since the clock signals appearing at the output Q9 of the oscillator counter 536 (FIG. 6B) are supplied to the output line 556 via the NAND circuits 577, 578 and 559, pulses which correspond to a decimal number appear in the output line 556. When the next clock pulse occurs, the states of the outputs Q1 to QU do not match the selected parameters, which are determined by the positions of the switches 570-575. Therefore, the output signal of the NAND circuit 566 changes from an L signal to an H signal, so that an L signal appears at the output Q of the JK flip-flop 567, which is fed to the NAND circuit 577 by the to prevent further transmission of the clock pulses from the output Q9 of the oscillator counter 536. Therefore, the number of pulses delivered to line 556 corresponds to a unique combination or set of desired pacemaker operating parameters.

As soon as the counter 558 reaches the counting result, in which it outputs an H signal at the output Q12, the monostable multivibrator 532 (FIG. 6B) of the main stop circuit is triggered in order to make a reset signal appear at its output Q, which corresponds to the reset input of the start -Lock circuit flip-flops 528 is supplied. When the reset signal appears, the signal at the output Q of the J-K flip-flop 528 changes from an H signal to an L signal, as a result of which the oscillator counter 536 blocks further operation. The monostable multivibrator 532 is connected to be triggered by a positive going pulse edge to produce a pulse the width of which is determined by the electrical values of the capacitor 580 between the C and RC terminals and the resistor 581, at the other end an H signal is applied to this resistor. The output Q of the multivibrator 532 is connected to the negative trigger input, so that triggering by means of a positive going edge prevents a new trigger.

According to FIG. 6D, the access keyword and the parameter keyword are fed in succession via line 556 to two pairs of transistors 583 and 584 forming Darlington circuits in order to be amplified; and fed to a coil 586 for generating an electromagnetic field. The voltage applied to the coil 586 is regulated by a voltage regulator circuit 587 and the associated outer circuit elements. For use, coil 586 is placed near the body of the pacemaker wearer. If the start switch 507 (FIG. 6A) is actuated, the access keyword and the subsequent parameter keyword are generated and fed to the coil 586 in succession, so that the latter generates a corresponding electromagnetic field, which is generated by the reed switch 215 according to FIG. 1 and 3A is detected and is used to control the pacemaker 10 in the manner described above.

6B, an npn transistor 589 is connected between a line 590, which can carry a positive voltage taken from the voltage regulator circuit 587, and ground, in order to ensure proper operation of the command generator 500. A light emitting diode 592 and a collector resistor 593 are connected in series between the positive line 590 and the collector of the transistor 589. The emitter of transistor 589 is grounded and the base of the transistor is connected to the Q output of J-K flip-flop 528. When the signal at the output Q of the J-K flip-flop 528 changes from an L signal to an H signal

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thus, the base-emitter junction of transistor 589 is biased in the forward direction so that a current flows through light emitting diode 592 to visually indicate that the command transmitter is in operation.

The circuits described above can be constructed from the circuit elements mentioned below. Of course, it is obvious to any person skilled in the art that this is only exemplary information and that other circuit elements could also be used.

Integrated circuits (type RCA)

Circuit element number

200 CD 4047

203,235, 276, 280, 402, 403, 528, 550,

551, 552, 567 CD 4027

s

6 sheets of drawings

Claims (5)

617 094 PATENT CLAIMS 1. Implantable pacemaker with several selectable operating parameters and a pulse generator (21) for generating stimulation pulses and delivering them to an electrode in contact with a heart, characterized by a receiver (215; 151; 220-223) for receiving a sequence of Data pulses, the number of which corresponds to a defined combination of pacemaker parameters; data pulse counting means (182; 291) for counting the received data pulses and for generating a binary signal representing the number of data pulses in the sequence; a memory (184; 290, 292, 295) for storing the binary signal; a counting circuit (162, 167, 180) connected to the memory (184; 290, 292, 295), which is set up in such a way that it outputs a notification signal for the input of the binary signal from the data pulse counter (182, 291) into the memory (184 ) only delivers when the complete data pulse sequence has been received; and by control circuitry (16, 17, 24) connected to the memory (184) for selecting the operating parameters from the parameter combinations for controlling the pulse generator (21; 310, 311) of the pacemaker. 2. Pacemaker according to claim 1, characterized in that the receiver (215; 151; 220-223) for receiving one of a pulse transmitter (500, 501, 502, 503, 504) at a location remote from the pacemaker (10) Pulse train is set up, with the pulse transmitter, the number of pulses generated can be selected according to a defined combination of pacemaker parameters. 3. Pacemaker according to claims 1 and 2, characterized in that the pulses are electromagnetic pulses, and that the receiver includes an electromagnetically actuated reed switch (215). 4. A pacemaker according to claim 1, characterized by a blocking circuit arrangement (30; 32, 38, 40, 41, 45) which is connected to the electrode for detecting pulses passed through the electrode and is set up in accordance with the pulse generator (21) block these impulses, and a control circuit arrangement (16, 17, 24; 35; 43, 50) which are connected to the memory (184) for controlling an asynchronous pulse frequency, in which the heart is supplied with impulses without synchronization with the natural heartbeats , the pulse width and the pulse amplitude of the stimulation pulses generated by the pulse generator and for controlling the sensitivity, the refractory period and the operating mode of the blocking circuit arrangement in accordance with the stored operating parameter data. 5. Pacemaker according to claim 1, characterized by a blocking circuit arrangement (152, 165, 166, 170, 172, 174, 176, 180) to which the data pulse sequence is applied and which is set up to block the counting device (182) generating the binary signal until the blocking circuit arrangement one has received a specific coded access pulse sequence, the blocking circuit arrangement comprising a data recognition circuit (165, 172; 270) for recognizing a particular access keyword which contains at least one inverted pulse.