DE2826330A1 - PLANTABLE PACEMAKER WITH SELECTIVELY CHANGEABLE CHARACTERISTICS - Google Patents

Description

282633Q ₁ Andrejewski, Honke, Gesthuysen & Masch patent attorneys

Physicist Dr. Waiter Andreevsky Graduate engineer Dr.-lng. Manfred Honke Graduate engineer Hans Dieter Gesthuysen Physicist Dr. Karl Gerhard Masch

Lawyer files: 43 Essen 1, Theaterplatz 3, Postf

52 079 / Fm "th June 13, 1978

Patent application

Medcor, Inc.

5920 Rodman Street

Hollywood, Florida 33023 / USA

Implantable pacemaker with selectively changeable features.

The first pacemakers used in human medicine were fairly straightforward in their function, as they were generally were working at a steady, fixed speed or frequency. If using a Such a pacemaker could easily achieve success for a number of years, this design became practical replaced by a further developed version, which

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referred to as a "demand" pacemaker. Such demand pacemakers can emit trigger impulses if no natural impulses occur within a specified period of time. As a result, the demand pacemaker will only generate pulses when a natural heartbeat is not occurring. The pacemaker then works as long as there are no natural heartbeats and generates trigger pulses with a fixed one Minimum rate or frequency.

It goes without saying that in determining a minimum rate or frequency suitable for operating a demand pacemaker many considerations to take into account. In addition, there are other not so obvious parameters, which must be matched to a single carrier. For example, the sensitivity of the facility to the The occurrence of natural heartbeats in one patient may be very different from that in another. In the same way it can It may be necessary to change the energy strength emitted by each impulse for the individual situations.

Until now, most of these parameters were set before the pacemaker was implanted in a patient. In recently, however, the need has emerged to be able to use certain work characteristics to adjust the pacemaker without removing the implanted device from the patient's body and without the need for surgical measures. Accordingly, it has already been proposed to take a step

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to train maoher in such a way that he responds to signals which transmitted to it either magnetically or electromagnetically through the body tissue. So is US patent 3 9 ^ 5 387 suggested the operating frequency of a Modify the pacemaker by taking a series of signals through the mechanism of a magnetically operated reed switch is entered. An electromagnet is typically placed on the patient's skin and this magnet alternates de-energized to open and close the switch. In this way, a meter section of the system becomes a Pulse train supplied and selected an operating rate which is determined by the number of pulses received. If also Such a proposed solution is to be seen as a step in the right direction, but it is separate Encoders and decoders are required for each function, so the complexity of the system increases very quickly if more than one Parameter is to be changed.

Another system in which a switch is magnetically opened and closed to generate pulses in a pacemaker, is described in U.S. Patent 3,805,796. Here creates a Binary decoder a combination of "high" and "low" outputs, which correspond to binary digits. The binary digits in turn represent the number of impulses which the System can be fed through the magnetic switch. Other digital control schemes have been developed, such as in the U.S. Patents 3,833,005 and 3,718,909 while in the latter signals from a giver to an implanted receiver in one

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Pacemaker system can be forwarded, one leaves still look to binary decoders to generate one representative of the number of pulses entered into the system, composite signal.

A problem with the arrangements described above is that one relies on the absolute number of pulses to determine the operational characteristics to determine. While it seems simple enough in principle to count the pulses received while the one to be applied If the number of pulses is to be changed as required, the facility actually has no way of determining whether too few impulses were received or too many replies were made, for example in the case of environmental influences Noise or noise or other error signals can occur. Also, due to the nature of binary digits, a relative insignificant change in the number of pulses received, e.g. 15 instead of 16, a fundamentally different one Group of output signals are generated. In the last-mentioned case, for example, those corresponding to item 15 would result binary output signals the number group 01111, while corresponding to a count of l6 pulses the generated binary signals resulting in the number group 10000. Hence when looking to control the state of various circuit elements relies on these binary signals, the omission or addition of a single counted pulse results in one completely different mode of operation than intended.

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Furthermore, in the case of implantable pacemakers, it is of great interest to be able to monitor the operation of the pacemaker, and especially the condition of its battery. This takes place quite generally through the body tissue of the patient, whereby the pacemaker pulses are "picked up" after they have passed through the body tissue. This is usually done through electrodes and the like. Which are brought into contact with the patient's skin. Even if this solution has been used for some time Having successfully applied it, it is clear that in the transmission of impulses through body tissues certain Signal weakening must occur. It is also possible to attach one or more electrodes to a patient for monitoring purposes The operation of an implanted pacemaker is relatively uncomfortable and also time consuming.

It would therefore be very desirable if one could create an implantable pacemaker in which several parameters at As required can be changed by a doctor, naturally one with a much less error-prone data and Information transfer method usable system is required, which also generates signals which are necessary for the operation of the pacemaker are representative and can be recorded directly by the pacemaker itself.

The invention is therefore based on the object of providing an implantable To create pacemaker, which is a signal receiving system further comprises a signal generator and generator system for controllable change in his work characteristics, which also

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encodes a signal reflecting an operating parameter and and which finally emits a variable number of internal pulses corresponding to a fixed number of received pulses Can generate control signals.

The invention is illustrated below with reference to one in the figures preferred embodiment explained in detail; it shows

Fig.l is a functional drawing of a data processing and Control system for an implanted pacemaker;

2 shows a circuit diagram of a preferred embodiment from Fig.l; and

3 shows a time diagram to explain certain aspects the mode of operation of the system from FIG.

A demand pacemaker with a pulse generator 10, a battery 11 and a catheter 12 is coupled to a memory 1J>. The state of the various outputs of the memory, for example indicated by their voltage levels, determines the mode of operation and / or the working characteristics of the pulse generator 10. The state of the memory I ^ is in turn controlled by a system which has a shift register 14, which is in this memory collects storing signals.

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The pacemaker is used to transmit control signals to an implanted pacemaker without surgical measures provided with a receiving antenna 15 which is coupled to a receiver and demodulator stage 16. The demodulated Signals pass through an OR gate 17 and are from processed by a decoder 18, then fed to the shift register 14, to control the state of the various shift register outputs. There is also a reed switch on the OR gate 19 coupled. A signal from the reed switch or decoded signals from detector 16 are used to detect a Start transmitter 20, which signals the operation of the pacemaker system to a transmitter or transmitter antenna

21 passes. The transmitter works when it receives either a stimulus from the pacemaker or alternatively a switching pulse generated by a natural pulse from the pacemaker. The latter signals are passed through the gate

22 processed and forwarded to the encoder 20. The pacemaker pulses are also used to reset the illustrated system including the shift register 14 via a gate 27> and a reset flip-flop 24. A controller 29 for fixed speeds is connected to the reed switch 19 and the end-of-word stage 25 (EOW) via an OR gate 30. A reduction in the pulse width of the pacemaker is provided by applying a signal from the charge enable flip-flop 26 to a reduced pulse width controller 31. Finally, an output of the end-of-word flip-flop 25 passes through an AND gate 27 to enable the load instruction stage 28 in accordance with an output from the load-enable flip-flop 26

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In practice, the data register part 14a of the shift register 14 comprise a series of interconnected flip-flops. The data register 14a and the elements 25 and 26 can then viewed as part of a single shift register 14 will.

In operation, the pacemaker works in the typical demand mode and generates pulses of a specified height and duration, as long as none naturally occurring trigger pulse is detected in a specified period of time. This time span therefore determines the Minimum pulse rate of the pacemaker. Like everyone As is known in the art, electrical pulses are applied through a catheter 12 having an electrode at the extreme end. Traditionally this electrode is implanted in the heart tissue to stimulate the heart. There is a miniature battery in the pacemaker case 11 to ensure the required power supply.

The actual working characteristics of the pacemaker are determined by the state of various output terminals of memory Ij5. The memory output is typically digital, i.e. its output terminals only have two electrical states. Typically these states are either "low" or "high" voltage levels. By applying voltages to electronic Devices with high impedance such as analog gates, field effect transistors or the like. The electrical features of a given segment of the pulse generator circuit can be changed. As a result, those stored in memory I3 control

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Data as indicated by the state of its output terminals directly the mode of operation of the pulse generator.

The control system described can be operated in two ways. In one mode of operation, a magnet is placed near the reed switch I9. The operation of the reed switch actuates the controller 29, which automatically sets the pacemaker (against the need) to operation at a fixed speed implements. By closing the reed switch, a release or start signal is also transmitted to the transmitter 20. Of the Encoder enabled in this way responds to the presence of pacemaker pulses and as a result generates signal clusters, which reflect the duration of the pacemaker pulse. The resulting signal can then be sent from the transmitter antenna 21 can be detected and emitted, and the pulse width and period of operation of the pacemaker can thus be monitored will. As is known to anyone skilled in the art, the intervals between pacing pulses are related to the charge of the Battery 11 so that the condition of this battery can be determined.

In the second operating mode, a signal is transmitted to the receiving antenna 15 via suitable devices such as a transmitter or transmitter arranged near the implanted pacemaker. This signal passes through the detector 16 and, whether modulated or not, the OR gate YJ, and gives rise to an enable signal at its output terminal.

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As in the first mode of operation, the gate 22 supplies an opening signal to the transmitter or transmitter 20, which causes the latter to operate emits reflective output signals from the pacemaker.

As will be explained in detail, the Introducing a data word of the required length into the shift register 14 through its end-of-word flip-flop 25 emits a signal, by which the fixed speed controller 29 is excited. In this way, the transmission of a data word to the pacemaker can cause it to do so will be able to work at a fixed speed. The pacemaker then ignores the occurrence of naturally generated ones Trigger pulses and works at a predetermined fixed speed.

By suitable encoding of the last bit of the data word in addition, the output of the charge-enable flip-flop is of the shift register are placed 14 to 26 to assume a low digital state and, accordingly, releasing the control ~ $ l for reduced pulse widths. In this way, the width or duration of the pulses emitted by the pacemaker can be substantially reduced in order to test the sensitivity of a patient to pulse widths and, consequently, to check whether there is actually a sufficient margin of safety with regard to the amount of energy used to stimulate tissue.

By modulating the 10 kHz carrier frequency, the shown System data are transferred and stored in memory IJ

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are saved to the operating characteristics of the pacemaker to modify. Accordingly, a received signal is demodulated and fed to a decoder 18, and the resulting decoded data is input to the shift register 14. The decoded data is also input to the reset flip-flop 24, however, since there is no release signal, the flip-flop speaks 24 not on.

According to a preferred embodiment, pulse width modulation is used of the transferred data is used. In order to distinguish between short and long data bits, the data at the same time the clock terminal (CLK) of the first stage of the shift register and fed to the decoder 18, which consists of a monostable circuit. The state of the decoder 18 at the end of the pulse at the CLK terminal determines the type of shift from stage 26 to the subsequent stages of the shift register transmitted data.

The next output line is activated with each subsequent pulse of the shift register 14a is energized. When the last bit of data is received, it reaches each of the output lines a state which reflects the nature of a corresponding data bit. If the data bit received first is the lowest When reaching the output of the shift register connected to the memory, the output of the end-of-word flip-flop reflects 25 shows the state of the charging release stage 26 at the end of the data reception process. In other words, the original output or the rest position of the flip-flop 26 is determined by the register

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pushed through in front of the received data and finally remains in the end-of-word stage 25. This stage then responds by actuating the controller 29 and the operation of the pacemaker changes from the on-demand to the fixed speed.

If the output lines of the shift register 14a are also excited, the memory 13 can only accept the information offered, when its charging clamp is released. This is achieved by the charging stage 28. The charging level is determined according to the Actuation of the end-of-word flip-flop enabled and by a signal from the load-enable flip-flop 26. The last-mentioned signal reflects the last or η th bit of the received data. Accordingly, by controlling the state of the last Data bits either enable or prevent the loading of data into memory. Provided that the last Data bit (in the illustrated embodiment, the fifth bit) results in the corresponding output signal, the AND gate 27 gives the Load order level 28 free. When the next pacemaker pulse arrives, it is passed through gate 22, and its leading edge actuates the load command stage 28. The Memory I3 takes the new data immediately after the leading edge of the pulse as a replacement for the previously saved operating data.

The trailing edge of the pacemaker pulse leaving gate 22 actuates the reset gate 23. The latter generates a first jerk partial pulse which is passed through the OR gate 45 is coupled to the reset terminals of the data register of the shift register 14 and through the AND gate 46 to the reset

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position clamp of the Plip-Plop 26. The other input of the AND gate 46 is connected to the flip-flop 25. In this way, the flip-flop 26 can only be reset by the first reset pulse when the flip-flop 25 is reset in turn, so that the pacemaker continues to work with a reduced pulse width.

In order to use the To fully initialize the system, a reset pulse is transmitted. The timing of this last-mentioned pulse is reversed delayed a period of time which is greater than the set period of time of the pacemaker, so that between receiving the last bits of the data word and the receipt of the reset signal pulse, a pacemaker pulse can always occur. When the reset signal, in the present case the sixth bit transmitted, is received, it will be the same as the five previous bits are used to reset the flip-flop 24. However, due to the state of the flip-flop 25 the flip-flop 24 is now released so that the reset pulse can reset the flip-flop 25 via the flip-flop 24 and also the rest of the shift register 14 via the gates 45 and 46. These are held in reset until the the next trailing edge of the pacemaker pulse arrives. This resets the flip-flop 24, causing the reset taken out of the shift register 14a and the system is initialized.

In a preferred embodiment, when a load release data bit is received, a load release stage

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the latter causes a signal to be emitted by which a controller J51 for operation with reduced pulse width is actuated so that the pulse width generated by pacemaker 10 is reduced by a factor such as $ 50. This gives a doctor the opportunity to test a patient's sensitivity to pulse width reduction, and there is a guarantee that the pulse width just programmed contains a sufficient safety margin.

FIG. 2 illustrates a preferred embodiment of the system from FIG. 1 and shows in detail a circuit for performing the functions of the same. The operation of some of the elements of Fig. 2 can be more easily understood with the aid of the various waveforms of Fig. 3. A 10 kHz carrier frequency, which is modulated to reflect the presence of pulse-width-modulated signals P ₁ to P ^, is picked up by the antenna 14 and demodulated by a group detector, which has a diode Dg *, a resistor R ₁ , a transistor Q ₁ and a capacitor C ₁ . The collector of transistor Q ₁ is coupled to a bias voltage source V. through a holding resistor R _1. The detected and filtered signal is then fed to an input of a NAND gate 32, the output of which is connected to the decoder 18, here a 20 ms monostable circuit, and the clock (CLK) terminals of a group of flip-flops J> K bis 39 is connected. These flip-flops are connected to a shift register which has a number of outputs that reflect the states of the outputs of the individual flip-flops. This arrangement corresponds to the shift register from Fig.l. With the outputs of the sliding

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registers, as Pig.2 shows, a memory 13 is connected. One of the outputs of the flip-flop 34, referred to as a load-enable flip-flop, is connected to a load flip-flop. The last flip-flop of the shift register chain, the so-called end-of-word (EO) flip-flop 39, generates a first output Q which is fed directly to the pulse generator circuit. The Q output of the flip-flop 39 is connected to a reset circuit _{via a diode D 1 -.} Another diode D ^ ₅ connects the Q output of the flip-flop 39 to its input, so that the flip-flop 39 is locked in the "high" state.

The loading flip-flop 40 generates an output which is applied to the CLK terminal of the memory 13 so that it accepts the outputs of the flip-flops 35 to 38. This operation takes place in accordance with a clock signal from an OR stage, which is formed by the NOT AND gates 48 and 50. This signal is also applied to the base of an output transistor Qp which is connected to a transmitting antenna 21. The current flows to the collector of Q ₂ via a resistor Rp which is connected to the output of the NAND gate 32. The same input of the NAND gate 50 is grounded via a capacitor Cp and also connected to an input line of the NAND gate 48 via a diode Dh.

Signals output from the monostable circuit 18 are fed to a reset flip-flop 52 via an RC combination Rh, C. Via a resistor R ₁ - is an input of the flip-flop 52 with one point of the bias potential V,

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tied together. The initialization signal received from NAND gate 48 for the pacemaker is fed through a capacitor C ^ to the flip-flop 52 and to an input of the NAND gate 5β passed.

The mode of operation of the circuit according to FIG. 2 will be described below with appropriate reference to the flow chart of FIG explained. First of all, it is assumed that a magnet is brought close to the reed switch 19. This matches with a situation in which a doctor or technician wants to obtain operational information from the pacemaker circuit without the The working characteristics of the pacemaker are to be changed.

In the rest position, both inputs of the NAND gate 32 are fed with a voltage corresponding to a digital "1", so that a low output (digital "θ") is generated. When switch 19 is closed, however, the output of the NAND gate goes high, corresponding to a digital "1". As a result, a bias voltage is applied to the monostable circuit 18 as well as to the CLK terminals of the flip-flops y \ to 39 and the collector of the output transistor Q ₂ through the resistor Rg. At the same time, a relatively low voltage, approximately equal to ground potential, is applied the pulse generator stage of the pacemaker is applied via the diode D ₁ (see Fig.l). This is used to inevitably design the pulse generator for operation at a fixed frequency, for example by inputting an "o" signal to one input of a logic element in the pulse generator, by taking a bias potential from one

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analog gate element or by any other of a number of other methods which can be used to make the pulse generator to operate at a fixed frequency as opposed to an existing need.

The pulse A (FIG. 2) represents a clock pulse generated within the pacemaker 10, while the pulse B represents a signal which results from the actual pulse sequence of the pacemaker. With natural sinus rhythms (NSR) only Α-pulses are generated. Conversely, when the pacemaker generates pace or trigger pulses, B-pulses also occur. The emergence of any type of these two pulses acts on the base of the transistor Q ₂ in the forward direction and causes the oscillator 70 to radiate a concentration of 5 MHz via the antenna 21.

By monitoring the signal emitted by the antenna 21, the fixed frequency pulse rate of the Pacemaker monitored along with the width of the pulses generated thereby. In this way, the working method of the pacemaker and the condition of the pacemaker battery using an appropriate capture and demodulation system to be determined. One such system is in copending US application ....... discloses, albeit using various forms of sampling and demodulation systems for this task can be.

A modulated

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10 kHz signal of the receiving antenna 15 are transmitted. The carrier wave is then fed to an input of the NAND gate 32 so that the presence of the carrier wave causes the gate to assume a "high" output, the modulations (interruptions in FIG. 1) of the carrier wave leading to a "weak" output signal, such as this is represented by the "detector signal" waveform. In a successfully tested embodiment, a form of pulse width modulation was used in which the signal pulses were distinguished in terms of their duration or width, while the total period of each pulse interval remained the same. In a preferred embodiment, a period of 40 ms was used, so that the leading edges of each signal pulse were 40 ms apart from the next. The width of each pulse has either a first short duration of 10 ms or a second longer duration of 30 ms. This shows the first line of FIG. 3 "modulated signal", in which modulations of a 10 kHz carrier wave appear as interruptions of the same for intervals of 10 or 30 ms. When checked by the diode Dp and amplified by the transistor Q ₁ ^ negative pulses corresponding to the widths are generated by the NAND gate 32, as shown as pulse P- to Pp in the second line of FIG. The negative leading edge of each pulse triggers the 20 ms monostable circuit 18, while the trailing edge (positive) of each pulse is used to activate the CLK terminals of the flip-flops 3 ^ to 39. By forwarding the output of the monostable circuit 18 to the D input of the first flip-flop 3 ^ the latter is made to emit a signal which reflects the state of the monostable circuit.

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Let us now consider the Pall, in which a short (10 ms) pulse occurs. The monostable output is low, corresponding to a digital "θ" (line 3 from Fig.3) j when the Cycle is running. The monostable signal then appears at the Q output of the flip-flop 3 ^ and is sent to the input D of the next Flip-flops 35 applied in the usual shift register manner.

When the shift register 14 is in its initialized state, the flip-flop J> k is in a "high" (Q = I) state, while the other stages of the register show "low" (Q = O) states.

After the first pulse P has elapsed, the output of the flip-flop 35 then reflects a digital "1" which represents the original wavefront. The wavefront always represents a digital "1" and is shifted forward through the shift register before the first pulse P received. When a second pulse Pp is received, the process is repeated. In the case shown, the pulse P- is long, ie it is 30 ^ms . At this point, the output of the monostable circuit 18 is terminated and the circuit returns to its rest position, with a high value when the clocking process passes through the positive Edge of the pulse is caused. At this point the pulse P ^ remains in the flip-flop 3 $, as can be seen from the high output of the latter. The second pulse P ₂ now remains in the flip-flop 35 > the first pulse P in the flip-flop 36 and the original wavefront signal "1" in the flip-flop 37 ·

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In this way a total of five pulses are transmitted as a complete word. At the end of the fifth pulse, it is stored in the flip-flop 34, while the pulses P to Pp. Remain in the flip-flops 35 to 3 ^. The digital "l" representing the state of the flip-flop y \ before the reception of the data remains in the end-of-word flip-flop 39 Word, ie after five pulses have been received, the end-of-word flip-flop 39 can reach a "high" output state. As a result, the end-of-word flip-flop 39 then goes high at the end of each data word, regardless of the type of pulses making up the word. Accordingly, the output of the digital "1" is taken by the flip-flop 39 as a signal for the end of a received word and the flip-flop output is connected to a corresponding point within the pacemaker pulse generator to operate it at a fixed frequency to switch. This can actually be the same point to which the reed switch yo is connected via the diode D ,. In addition, the output digital "1" of the flip-flop 39 is fed back to its input through the diode D ^, UiU to lock the latter in its high state.

As shown, flip-flop 39 also produces a complement or Q output which shifts to a digital "ü" when a full five-bit word is received. In its high state, the Q signal holds the reset terminal R of the load flip-flop 40 high, thereby blocking the flip-flop. The diode Dg blocks the reset ^{pulse to the flip-flop 3 2} I-- When the ^ output goes low, the charging flip-

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Flop ho enabled and can respond to clock signals derived from the pacemaker pulses. At the same time, the type of the fifth pulse P ₁ -, which remains in the flip-flop 34, determines the probable state of the loading flip-flop 4o, since its complement is fed to the D terminal of the flip-flop. When the pulse is Pf- long, meaning that no reprogramming of the memory is desired, the first or Q output of flip-flop 34 is a digital "1". Accordingly, the complementary Q output of flip-flop 34 is a digital "θ". The next time the load flip-flop 40 is actuated, the signal applied to the CLK terminal of the memory Ij5 is a digital "θ" and is consequently ineffective for entering the received data into the memory. In this case, the memory I3 continues to supply the previous control signals to the pulse rate generator.

On the other hand, as shown in Figure 3, if the fifth pulse Pp- is short (digital "θ") the load enable flip-flop 34 may go low, making its complement or Q output digital "l" is. If, in this case, the charging flip-flop 40 is clocked by the next pacemaker pulse, it can emit an enable signal to the memory I3, whereupon its outputs assume states which correspond to the outputs of the flip-flops 35, 36, 37 and 38. In this way, the operation of the pacemaker pulse generator can be modified to reflect the data encoded _{in pulses P 1 through P 2.}

The manner of operation of the load flip-flop 40 is shown in FIG Interest, since its timing depends on the way the step-

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machers and independent of the time the data was received is. A “shortest pulse "circuit is constructed as shown in FIG and can receive signal pulses A and B. The signal pulse A, which is sometimes referred to as the "reset" pulse, is used generated in an on-demand pacemaker in the event a natural heartbeat is detected or the tissue stimulating signal occurs. This signal pulse is from longer duration than pulse B.

The pulse B gives an actually transmitted pacemaker pulse again, which is used to stimulate body tissues. Each of the two aforementioned pulses can transfer data to the Load memory 13. Both signal A and signal B result a positive charge command pulse 60, the leading edge of which forms a clock signal to which the previously prepared charge flip-flop 40 replies. If, as explained above, the loading flip-flop 40 has not previously been enabled (by removing a digital signal "1" from its reset terminal and the installation of a digital "1" to its D terminal), the charging flip-flop responds not on the load command pulse.

Regardless of whether the data is being loaded or not, each time a pulse occurs, the system shown becomes at least partially initialized. The gates 48 and 50 are designed to respond to the shorter of two pulses so that when the pacemaker initiates a pacing or provides trigger impulse, and impulses A as well as impulses B arise, only the B impulse is processed by the system.

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If the Q output of the flip-flop 39 is a digital "1", the A or the B pulse has no effect on the loading flip-flop HO, although the other flip-flops are reset. The reset is carried out by the trailing edge of the charge command pulse, which the capacitor C ₂ . and the monostable circuit 52 and the NAND gate 56 is fed. In response to the negative ramping edge, the NAND gate 56 resets the flip-flops 35-38. The end-of-word flip-flop 39 continues to output a signal of the digital "θ" to the reset terminal of the loading flip-flop ² K). The Voral twiderstand R ^, which is between the NAND gate 56 and the reset terminal of the charging flip-flop 4o and the set terminal of the charge-release flip-flop 34, prevents the latter from changing its state.

The system cannot be initialized before a last jerk signal and a signal pulse have been received (A or B) occurs. In the present case, this signal consists of a pulse P ^, which only after a minimum time im Connection to the transmission of the final pulse of the data word, here thus the impulse P, -, can be transmitted. The minimum time which can elapse between the end of the transmitted word and the transmission of the reset pulse is longer than the working period of the pacemaker. This ensures that a charge command (pacemaker) pulse always occurs occurs during the interval between the end of the word and the reset pulse. Correspondingly, as shown in Fig.3 9 shows that the trailing edge of the pacemaker pulse causes the flip-flops 35 to 38 of the shift register 14 to be reset Zero.

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It goes without saying that the 3 output of the flip-flop 39 is in a digital "1" state until a complete data word has been received. Accordingly, a digital "1" is maintained at the input of the reset flip-flop 52, via a bias voltage D ^. While a data word is being received, negative pulses are continuously transmitted to this point from the ionostable circuit Ib via an RC circuit with the resistor Ru and the capacitor C-. Due to the impedances, however, the input is held at a digital "1".

As already mentioned, the Q output of the flip-flop 39 is a digital "1" when the data word expires. At the same time, the Q output of this flip-flop falls to the digital "ü" and thereby switches the diode D ₁ - back. As a result of the bias voltage applied to the input of the reset flip-flop 52 through the series resistor Rc-, a digital signal "1" appears continuously at the input of the flip-flop. One then speaks of the fact that the flip-flop is enabled.

If then a reset pulse Γ, - is received, the monostable circuit Ib outputs a negative pulse again, which R ^., C-, passes through. However, since the diode D ₁ - is switched back (baci; biased), the negative signal is used to set the reset flip-flop ¹ Jd. The latter then gives a reset signal to the flip-flop 39 and to the NAND gate 56, whereby the flip-flops 3 ^ kis J5 ° are reset. The circuit is then completely reset and remains in this state until a pacemaker pulse occurs, which

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Andrejewski, Honke, Gesthuysen & Masch, patent attorneys in Essen

ensures that all registers are initialized. VJenn a wrong word or only part of a word was received, for example a word consisting of only four pulses, if the next following pacemaker pulse occurs, the trailing edge of the load command pulse is used to flip-flops 3 ^ to reset to 39. Since the full complement of bits was not received, the flip-flop 39 remains in its original condition. The diode Dg is blocked, so that Reset signal the flip-flops 3 ^ to 38 can reset. A provision of the Sys. terns such as a bit Pg is then no longer required.

On the other hand, if signals are received which make up an excessively long word, such as a series of noise signals, the excess pulses automatically reset and synchronize with the trailing edge of the pacemaker pulse an initialization of the circuit without the signals being loaded into memory I3.

It can therefore be seen that variables such as the pulse rate, The pulse width and the sensitivity of the pacemaker can be changed as needed by changing the width of a appropriate pulse of the first four of the five pulses forming a transmitted word is modulated.

In contrast to the teachings of the technical world that have hitherto been recognized as correct, according to the invention the memory I3 is provided with a constant Number of pulses addressed, the state of the memory being the characteristics of a single one of the transmitted

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Andrejewski, Honke, Gesthuysen & Masch, patent attorneys in Essen

- 2Y & - -

reflecting impulses, equip, as previously assumed, to be correct was, their total worth. In this way, for example, the first transmitted pulse P, the pulse width, reflects the Pulse Pp the sensitivity, the pulses P-, and Pn the frequency and so on. Therefore, in the case of the pacemaker according to the invention, to increase the performance of the system by also further You need to be able to control touch maker parameters in the shift register to provide only one or more additional flip-flops and to enlarge the memory 13 by corresponding elements. By transmitting a word with a measurably larger number of pulses, a additional information is transmitted. As a result of the relatively short period of time which the pulse train requires, can in the available time span, which corresponds to the time span between the impulses of the pacemaker itself, one convey a considerable amount of information.

Naturally, the invention is not limited to the special ones Details of the exemplary embodiments shown, but rather further modifications that are readily known to any person skilled in the art or applications are possible, which, however, should not be explained in detail here.

809881/0911

Claims (1)

Andrejewski, Honke, Gesthuysen & Masch, patent attorneys in Essen Patent claims: IJ Implantable pacemaker, in particular cardiac pacemaker, with selectively variable features, characterized by a detector (16), a register (14a) connected to the same for collecting received signals and for generating electrical outputs corresponding to these received signals, one connected to the register and its output signals storing memory (Ij5) and a connected to this memory and the state of the same corresponding trigger pulses to the body tissue emitting pulse generator (10). 2. Pacemaker according to claim 1, characterized in that a charging stage (28) is provided through which the memory (13) can be released for receiving data from register (14). 3. pacemaker according to claim 2, characterized in that the charging stage (28) is designed in such a way that the memory (Ij5) can be released when a trigger pulse occurs. ^. Pacemaker according to claim 1, characterized in that a responsive to the presence of the received signal transmitter or transmitter (20) is provided, via which a Working characteristics of the pacemaker reflective signal can be emitted. Andrejewski, Honke, Gesthuysen & Masch, patent attorneys in Essen 5. pacemaker according to claim 1 with a received signals Pulse generator changeable in its operating characteristics, thereby characterized in that the detector (16) is designed in such a way that the received signals can be demodulated by him, that a This demodulated signals decoding decoder (10) is provided and with this a shift register (14) for the recording the decoded signals is connected one after the other that with the pulse generator (ÜO) the same with electrical Signals for the determination of at least one of its operating characteristics affecting memory (13) is connected that with the memory a loading stage (28) is connected, through which the acceptance and storage of signals leaving the shift register in the Memory can be achieved if the shift register has an end-of-word stage (25) which, when η signals are received, the loading stage releases that with the charging stage on pacemaker pulses responsive gate (22) which actuates the loading stage for data transmission from the shift register to the memory is provided is, and that with this gate a reset arrangement (24) is connected, through which when a pacemaker pulse occurs at least a part (25) of the shift register is divisible. 6. Pacemaker according to claim 5, characterized in that the shift register (14) is a responsive to the decoded signals Has stage (26), through which the charging stage (28) can be released. HÜ9881 / 091 i Andrejewski, Honke, Gesthuysen & Masch, patent attorneys in Essen 7. A pacemaker according to claim 6, characterized in that a pulse generator (10) for the delivery of trigger pulses with a fixed frequency causing control (29) is provided, which can be actuated by the shift register (14). 8. pacemaker according to claim 5 »characterized in that to reset the shift register (14) according to the A reset circuit (24) is provided for decoding a reset pulse following the decoding of the η signals. 9. pacemaker according to claim 6, characterized in that to reduce the pulse width generated by the pulse generator (10) a control (3I) is provided and with this one Part (26; 34) of the shift register (14) is connected in such a way that the control can be switched on according to a decoded signal. 10. pacemaker according to claim 5 * characterized in that a transmitter (20) is connected to the detector (16) and the gate (22), through which, when a Receive signal and a pacemaker pulse for the Pacemaker pulse representative signal can be emitted. 11. Pacemaker according to claim 10, characterized in that the detector (10) has a receiving antenna (15) and the received signal having demodulating demodulator and a switch (19) responsive to an existing magnetic field. 0 9 8 8 1/0911 Andrejewski, Honke, Gesthuysen & Masch, patent attorneys in Essen 12. Implantable pacemaker with a pulse generator for generating trigger pulses to be delivered to a body tissue, in which at least some operating features of the pulse generator can be determined by received signals, characterized by a ge-stored signals to the pulse generator (10) emitting memory (13), collecting received signals and to the Memory-transmitting shift register (14) with a load enable stage (26) at the input and a word end stage (25) at the output, further by a radio frequency signal with a a constant number of modulated data signals receiving detector (16), a decoding the received signal and the pass the decoded data signals one after the other to the shift register Decoder (18), the shift register for receiving the fixed, constant number of data signals is designed and its end-of-word stage so on the reception of the η th of the data signals responds to the fact that a release signal can be output to the charging release stage, furthermore by a connected to the memory and causing the same to accept new shift register data load instruction stage (28), with which the load enable stage of the shift register is connected in such a way that the load command stage has an enable signal the charging enable stage is enabled, and finally by a gate responsive to the generation of pacemaker pulses (22), by means of which an actuation signal can be supplied to the load command stage, so that data signals collected in the shift register can be transmitted to the memory when a pacemaker pulse is generated, and thereby at least some operating features of the pulse generator (10) can be determined. 8Ö9881 / 0Ö11 Andrejewski, Honke, Gesthuysen & Masch, patent attorneys in Essen IJ). Satellite maker according to Claim 12, characterized in that the received signal consists of a modulated carrier signal which reflects the presence of the η pulses, the modulation assuming a first and a second state. 14. Pacemaker according to claim 1J>, characterized in that the modulation is a pulse width modulation. 15 · pacemaker according to claim 12, characterized in that with the word end stage (25) of the shift register (14) and the Gate (22) a reset circuit (24) is connected, whereby following the collection of the η data signals in the shift register at least a part of the shift register can be reset in accordance with the generation of a pacemaker pulse. 16. Pacemaker according to claim 15 *, characterized in that the reset circuit (24) is further connected to the decoder (18) and responds to an η + actual received signal. 17 · Pacemaker according to claim 12, characterized in that with the detector (16) and the gate (22) a transmitter (20; 70) is connected and a release circuit is provided for this is by which the transmitter can be triggered in accordance with a detected signal in such a way that it receives a pacemaker pulse corresponding signal can be emitted. 18. A pacemaker according to claim 17 , characterized in that the transmitter (70) can generate a concentration of radio frequency oscillations with essentially the duration of a pacemaker pulse of the same duration. 609881/0911 2B2633Q Andrejewski, Honke, Gesthuysen & Masch, patent attorneys in Essen --5J5- 19 · Implantable pacemaker, by means of which one signals relating to the operating state of the pacemaker can be transmitted to external receivers, characterized by a Arrangement (15> 16) for setting the signals, a tissue-stimulating one Pulse-delivering pulse generator (10) and one the operating features of the pacemaker only when plagued the signal that emits the received signal but does not work at any other time (20; 70, 21). 20. A pacemaker according to claim 19 *, characterized in that the transmitter (70, 21) comprises an antenna (21), an oscillator (70) connected on the output side to the same and a gate (Q ₂ ) controlling the oscillator output in such a way that the transmitted signal is a signal concentration at the oscillator frequency with pulse duration and / or pulse interval related to the operating characteristics of the pacemaker. 21. A pacemaker according to claim 20, characterized in that the oscillator (70) can only be activated by the detector (16) is, whereby the signal concentration can be generated via the gate and thus the energy requirement of the encoder can be reduced. 22. A pacemaker according to claim 21, characterized by a circuit which is responsive to second received signals and through which the pulse generator can be switched to a fixed frequency and the oscillator can be activated. äO988i / oäi1