DK151935B - IMPLANTABLE, HEART-PACEMAKER WITH EXTERNALLY SELECTABLE FUNCTION PARAMETERS - Google Patents

Description

DK 151935 B

The invention relates to a cardiac pacemaker, which can be briefly described as an implantable pacemaker which can be programmed to change the pacing pulse interval, pacing pulse width, pacing pulse amplitude, pacing sensitivity, refractory interval, and mode of function (need function or asynchronous function).

The pacemaker contains an asynchronous frequency control circuit which is controlled by a digital clock generator to start the cardiac pacing pulses. Any naturally occurring heart pulses are detected by a frequency-sensitive R-wave receiver to reset the count in the asynchronous interval generator if a naturally generated heart pulse is received after a refractor interval. There is a main parameter control circuit for changing selected parameters in the pacemaker in accordance with a control signal applied from the outside. Connected to the main parameter control circuit, there is a sensitivity control circuit to enable selective change of the R-wave amplifier sensitivity, a refractory interval control circuit and a refractory interval control counter to produce several different available refractory periods, a signal switched off to form a function switch of a natural heart wave to enable the circuit to operate asynchronously or in need function c Er * asynchronous frequency control circuitry is arranged to provide a number of selectable asynchronous intervals which can be selected to initiate the produced cardiac pacing pulse, a width control which ensures that pacing cardiac pacing can be produced. selectable width and an amplitude control circuit which makes it possible to optionally change the amplitude of the pulses produced by the pacemaker.

Furthermore, there is an external control unit which produces successful sequences of pulses, the first row of which is an opening code to be detected by an opening code detection circuit within the main parameter control before the following parameter code can be accepted for changing the pacing parameters. The parameter code generated after the opening code i determines the selected range of pacing parameters and can be selected by external control means in the external maneuver unit. j

Within the master parameter controller there are means in identifying the opening code to enable the main path parameter controller circuit to accept the selected parameter code and that the entire parameter code is received before changing the pacemaker parameters according to the unique parameter code received.

The invention relates to cardiac pacemakers and especially pacemakers of a type in which the function parameters can be varied and remotely controlled. |

Cardiac pacemakers are often equipped with various means j to control selected function parameters, so that the pacemaker e.g. can be set to respond to and output signals to one

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3 patient according to his individual needs. After the pacemaker is started, making changes to a particular function parameter can become a difficult problem.

Such changes are often required e.g. by improving or worsening the patient's condition, which may require certain adjustments, e.g. the rate at which the pacing pulses are delivered to the patient, the pulse width and the amplitude of the pulses delivered, the refractory interval displayed by the pacemaker, the sensitivity to naturally produced heart signals, and the pacemaker's behavior, e.g. function as required, function with fixed frequency and similar modes of operation.

Various proposals have been made in the past to make changes to selected cardiac pacemaker parameters for an implanted cardiac pacemaker without major surgical intervention. It has e.g. have been proposed to provide a coupler which can be affected by a magnetic field and which can be activated by a magnet outside the patient, typically for changing the pacemaker from demand operation to fixed frequency operation. Furthermore, pacemakers with recipient organs have been proposed for receiving invasive surgical needles which can be inserted into the patient for adjustment of e.g. the value of a resistor or similar part.

Terry, Jr., et al., In U.S. Patent 3,805,796, disclosed an implantable cardiac pacemaker having certain adjustable function parameters. The circuit according to Terry includes a first and a second digital pulse counter. The first counter receives a first predetermined set of input pulses, after which it generates an opening signal that passes subsequent input pulses to the second counter. The second counter includes multiple outputs for activating different couplers, each running in parallel with a corresponding resistor in a plurality of series-connected resistors for controlling the input current of a transistor in a multivibrator to change its time constant. A second output on the second counter controls a coupling that directs a portion of the drive current outside the output amplifier of the pacemaker to control its output current.

The circuit according to Terry, as described above, responds to a password that is merely a sequential series of seven pulses. A requirement for the circuit according to Terry is that seven pulses occur in series to enable the first count of the pulses to be counted. Thus, if the cardiac pacemaker carrier, e.g. should be exposed to a field to which the circuit responds, the circuit may incorrectly detect the field pulses as the password and, more importantly, then set the various parameters regulated by the circuit.

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Furthermore, according to Terry, the circuit only provides means for changing the pulse rate (and thus the width) and the output current produced by the pacemaker, without regard to many of the other essential pacemaker parameters discussed above.

Another disadvantage of the circuit according to Terry is that once the access pulses have been counted and the second counter opened, the input data pulses will produce immediate changes on the various output lines. These j changes will produce immediate changes in the selection of the different time resistors over the time the data is received. If only the output, current changing coupling activated by the last output counter of the counter is desired to be activated, all combinations of time resistance connections will in fact be activated before the final activation of the bypass coupler, which was originally desired to be changed.

In view of the above, it is therefore an object of the invention to provide a digital cardiac pacemaker, which includes means outside or remote from the pacemaker for adjustable modification of selected pacemaker functional parameters.

It is desirable to provide a digital cardiac pacemaker which, after implantation, can be regulated outside the user to change any selected or arbitrary selected of the following functional parameters: the width of the pacing pulse, the amplitude of the pacing pulse, the frequency of the pacing pulse in demand operation and in fixed operation. speed, refractory period, j the heart signal sensitivity and the mode of operation. j

It is further desirable to provide a digital heart cardiac pacemaker, which includes a repository for storing signals that determine the pacemaker's operating parameter, which signals can be completely inserted into the repository prior to execution.

It is also desirable to provide a digital cardiac pacemaker and controllable means for modifying its functional parameters including a circuit for recognizing a unique password to ensure that the function parameter determining signals are not inadvertently decoded.

It is further desirable to provide a circuit for use in a digital cardiac pacemaker to control the sensitivity over | in for heart rate signals.

Finally, it is desirable to provide a digital cardiac pacemaker where the function parameters can be varied independently.

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These and other objects, features and advantages will become apparent to those skilled in the art from the detailed description set forth below when read in conjunction with the drawings and claims.

In broad terms, the invention provides an implantable digital cardiac pacemaker with externally selectable functional parameters. The pacemaker includes an external instructional means adapted for transmitting a train of parameter selection pulses. The pacemaker includes means for receiving the train of pulses and generating a digital signal under the influence of the train. In the pacemaker, according to the invention, there are storage means for storing a number of function parameter control signals prior to their exercise for controlling the independent setting means and means connecting the storage means to the setting means for exercising the function parameter signals in the storage means so that the function parameters are controlled by these signals. In another aspect of the invention, an implantable cardiac pacemaker includes externally controllable means for changing selected functional parameters including sensitivity, refractory period, pacing pulse amplitude, pacing pulse frequency, pacing pulse frequency, and mode of operation; demand or fixed frequency operation.

In one embodiment of the invention, there are means for detecting an externally generated password which includes a digital signal which includes at least one zero logic state to allow reception of a later transmitted series of pulses to control the cardiac pacemaker's operating parameters.

The invention will now be described in more detail by way of example with reference to the schematic drawing, in which Fig. 1 shows a block diagram of a cardiac pacemaker according to the invention with various controllable parameters; 2 is a block diagram of the circuit of the main parameter control circuit including a circuit for recognizing the password, instruction store and circuit for inserting the instruction code into the storage according to a feature of the invention; FIG. 3A, 3B and 3C are a detailed electrical schematic diagram of the main parameter control circuit of FIG. 2, FIG. 4 is a detailed electrical schematic diagram of the pulse generator and amplitude control circuits as well as of the R-wave amplifier and sensitivity control circuits of the cardiac pacemaker of FIG. 1, FIG. 5A and 5B are a detailed electrical schematic diagram of the control counter circuit, refractor control circuits, reset circuit for the asynchronous generator, function control circuit, generator circuit for asynchronous interval, control circuit for asynchronous frequency and FIG. 6A, 6B, 6C and 6D are a detailed electrical schematic diagram of an external control means for use in transmitting access and parameter codes to the main parameter control circuit of FIG. 3A, 3B and 3G.

In the various figures of the drawing, similar reference numerals are used to indicate similar parts. Furthermore, the interconnections between the various circuits in the drawing are indicated by corresponding letters (A, B, C etc.).

A cardiac pacemaker 10 according to a preferred embodiment of the invention is shown in block diagram form in FIG. 1. The various electrical circuits | in the cardiac pacemaker of FIG. 1 is illustrated and described below in detail; with particular reference to FIG. 2-5.

Referring to FIG. 1, the cardiac pacemaker 10 receives naturally generated heart signals and other signals from and delivers stimulation signals to a terminal 11 adapted for a connection with cardiac electrodes, such connections being a prior art.

The cardiac pacemaker 10 operates in conjunction with a digital clock transmitter 12 which produces clock pulses with a frequency of e.g. 6.82 kHz. Pulses from the clock sensor 12 are divided by a frequency divider 13 and delivered to a line 14 to an asynchronous interval generator 15 having multiple outputs T1-T8 connected to an asynchronous frequency control circuit 16. Each of the outputs T1-T8 represents a different asynchronous interval within the considered range, and the control circuit 16 for asynchronous frequency selects one of the outputs T1-T8 from the asynchronous interval generator 15 controlled by a main parameter controller 150.

The selected output of the asynchronous interval generator 15 is connected to a width control circuit 17 which produces an output pulse of the selected width controlled by the main parameter controller 150. This option is activated by the clock pulses on line 14 which is fed directly to the width controller 17 and to a frequency divider 19 which produces clock pulses having a sub-multiple of the frequency transmitter 12's frequency for supply to the width control circuit 17, thereby providing signals from which the different widths of the output pulse can be selected.

The output pulses from the width control circuit 17 are applied to trigger a pulse generator 21 to produce an output pulse on the output line 22 for transmission to the cardiac terminals 11. The amplitude of the pulse generated by the pulse generator 21 is controlled by an amplitude control circuit pair 24, which in turn is controlled

The output of the width control circuit 17, in addition to the connection to the pulse generator 21, is connected through a NAND circuit 30 to a reset 7.

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Thus, when the asynchronous generator 15 reaches a predetermined selected number upon generating an output pulse from the width control circuit 17, the asynchronous interval generator is reset to begin counting the subsequent asynchronous interval.

The above-described part of the cardiac pacemaker serves as a so-called fixed-frequency pacemaker, which produces pulses asynchronously at a frequency controlled by the selected output of the asynchronous interval generator 15. To provide the demand-pacemaker operation, an R-wave amplifier 11 is provided by a cardiac transducer 32. line 33 connected to an input of the R-wave amplifier 32 for conduction of naturally occurring heart pulses to the R-wave amplifier 32.

Other signals, such as stimulation pulses produced by pulse generator 21 on line 22 and interfering electromagnetic noise which can be detected by the cardiac electrodes or other associated circuits, can also be detected on line 33 but filtered or rejected or enable noise drift or fixed frequency operation is shown in the following. The sensitivity of the R-wave amplifier 32 * is controlled by a circuit 35 for sensitivity control, which is again controlled by the main parameter controller 150.

The R-wave amplifier 32 produces an output signal by the detection of a naturally generated R-wave, a stimulation pulse or a disturbance signal, for output to a control counter 38. The control counter 38 also receives clock pulses from clock generator 12 through a NAND circuit output 40 and T ^, and after being reset. The output signal formed at that time is applied to a reset circuit 41 for the asynchronous generator which produces an output signal which is output through the NAND circuit 30 to reset the contents of the asynchronous interval generator 15. If an R-wave, a stimulation pulse, or a disturbance signal when the pacemaker is in operation is received by the R-wave amplifier 32 before the time when a signal appears at a selected output of the asynchronous interval generator 15, it is reset to begin the count again at a way known in the art as demand operation.

Furthermore, one or the other of the control counter outputs or of a refractory regulator circuit 43 is controlled by the main parameter circuit 150. The selected output is connected to an inverting NAND circuit 45 and thence to NAND circuit 40 for controlling the passage of the clock pulses on line 14. and to the reset circuit 41 of the asynchronous generator to produce a state therein which permits the reset pulse of the asynchronous generator generated hereinafter to be generated from the control counter 38. Thus, the effect of the circuitry is to produce a "readiness state" of the reset circuit 19 in the reset state 8 | after the control counter 38 has reached a predetermined refractory count determined by the refractory control circuit 43. After generating the readiness state, a logic state is applied to the input of the NAND circuit 40 which closes the passage of the clock pulses on line 14, thereby terminating The control counter 38 counts. The generation of an output pulse from the 'R-wave amplifier 32 then produces a pulse which resets the regulation counter 38 and in turn enables it to begin counting.

When the count has reached time T1, the asynchronous generator reset 41, previously opened by the refractory control circuit 43, produces a reset pulse to reset the count of the asynchronous interval generator.

However, before the pacemaker reaches the "standby state", it is in a "control state" during which reception of a signal from the R-wave amplifier 32 does not produce a reset pulse for the asynchronous interval generator, but where the control counter 38 is simply reset to the pre-counted refractory period from the beginning.

Furthermore, there is a circuit 50 for controlling the mode of operation, which circuit is controlled by the main parameter controller 150. When the mode of form controller 50 is activated, it interrupts the function of the reset circuit 41 of the asynchronous generator, thereby causing the pacemaker circuit 10 to operate in a fixed frequency function. In addition, the function mold controller 50 can be operated by a temporary external regulator, such as an electromagnet or similar device, to cause the circuit to operate in a fixed frequency operating mode for testing purposes, as is well known in the art.

The main parameter controller 150, described below in more detail, is programmed by means of an external control signal applied to a receiving element 215, such as a magnetically activated reed coupler or similar element, as described below.

As indicated, the cardiac pacemaker 10 of the invention includes equipment for changing the function parameters, namely, the width of the pacing pulse, the amplitude of the pacing pulse, the refractory period, the heart signal sensitivity and mode of operation (i.e., fixed frequency or demand operation), and the asynchronous pulse generation. Furthermore, these operating parameters can be changed after the pacemaker is implanted in the patient's body. To facilitate this parameter control, the main parameter control circuit 150 is used.

Circuit 150 is shown in block diagram form in FIG. 2 and in more detail in Figures 3A-3C.

As will be seen, the main parameter control circuit 150 responds to an internally supplied input signal from an instructional means as described below. The instruction means provides an initial access sequence of the electromagnet! - 9

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pulses are followed by a sequence of electromagnetic pulses to determine the pacemaker's operating parameters. The control circuit 150 must first recognize the access sequence before the control sequence will be accepted and entered into the control circuit's storage. More specifically, the externally applied input signal as shown in FIG. 2 and fed to a single-pulse type digital pulse generator 151 which produces a controlled amplitude and width output pulse for each externally input input pulse to overcome interference problems with the signal pulse detection coupler (described below). The output of the single-pulse digital generator 151 is applied to a start lock circuit 152 and a NAND circuit 156. The output of the NAND circuit 156 is fed to the input of a switch register 165, the various outputs of which are connected to a pattern recognition circuit 172.

At the same time, clock pulses are applied from clock generator 12 to digital pulse generator 151, a reset circuit 155, and a counter 162. Three output signals on the counter 162, which appear at various different times, are fed to a shift register 165, a pattern search stop 166, and a stop circuit 167. Furthermore, the output of the NAND circuit 156 is led to an input on the shift register 165, as well as to another NAND circuit 170.

An output of the pattern recognition circuit 172 and an output of the pattern search stop 166 are fed to a NAND circuit 174. The output of NAND circuit 174 is fed to the input of an activation lock circuit 176 and its output is fed to a second input of NAND circuit 170 and to a NAND circuit 180. The output of the stop circuit 167 is led to a second input of the NAND circuit 180 and to a reset terminal of the start lock 152. The output of the NAND circuit 170 is fed to the input of a data counter 182 and the outputs of the data counter 182 are passed. to a data storage memory lock 184. The output of NAND circuit 180 is connected to the "lock-in terminal" of lock circuit 184.

Briefly explained, during operation, the start lock 152 is activated after supplying the externally applied input signal to the digital single pulse generator 151. The start lock circuit 152 activates reset circuit 155 which initializes shift register 165, pattern search stop 166, activation lock 176, stop lock 167, and data counter 167 as well as data counter 167. start lock 152, counter 162 to begin counting. The counter 162, as explained in more detail below, produces output signals that are submultiply of the clock frequency.

The data from the single pulse type digital pulse generator is then fed through the NAND circuit 156 (which is opened to pass the data due to the output signal from the start lock 152) to the pattern recognition switch register 165. The first seven data bits are entered into the switch register 165 by

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10 is a frequency that is a sub-multiple of the clock frequency 160 (1/32 thereof in the exemplified embodiment). The data in the shift register 165 is continuously applied to the combination logic pattern recognition circuit 172 which produces an output signal when and only when the predetermined recognition code occurs in the shift register 165. At the same time, the pattern search stop 166 is activated by a second output of the counter 162 by a second sub-multiplier clock. e.g., 1/256 of the clock frequency, the time required to input the first seven data bits in the shift register 165). The output signal from the pattern search stop circuit 166 activates the activation lock 176 when applied together with the output signal from the pattern recognition combination circuit 172 to the NAND circuit 174.

Therefore, the data appearing at the output of the NAND circuit 156 is supplied by the NAND circuit 170 to the data counter 182, and thence to the data storage circuit 184.

At a time when the data is completely entered into the data store 184, the stop latch 167 is activated to produce a signal applied to a "storage terminal" of the data storage circuit 184 through the AND circuit 180. At the same time, the output of the stop latch 167 is applied to the reset latch 152 for reset. of this to an initial state to preclude further transmission of data into circuit 150.

At this point, the data of the external instruction organ is stored in the data storage circuit 184 to change the pacemaker circuit's operating parameters. j The control pulse receiving circuit of FIG. 2 is shown in more detail in FIG. 3A-3C. More specifically, the clock generator 12 (Fig. 3A) includes an astable multivibrator 200 which provides an oscillator output signal on a line 201 for transmitting clock pulses to the remaining portion of the circuit. Further, there is a frequency sub-circuit 13 including a J-K master slave tilt coupling 203 to which a split frequency output of the astable multivibrator 200 is applied to the clock input; and a D-type toggle switch 204 to which the Q output of the J-K toggle connector 203 is guided to a clock input thereon. The Q output of the flip switch 204 is connected to the D input, whereby the output switches between high and low state at successive clock pulses to divide the clock frequency by two. The output of the D-tilt coupling 204 is passed from the circuit along a line 208 (the connection continues from point BB to the width control circuit 17 in Fig. 5B). Since the Q output signal from the astable multivibrator 200 has half of the oscillation frequency formed, the output signal j from the D-tilt coupling 204 will be the clock frequency divided by four. Set and reset the exploration terminals of the D-tilt coupling 204 and the J-K tilt coupling 203 are connected to a low state 190 to ensure continuous operation of the corresponding tilt couplings.

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A trigger, the external reset, and the gene trigger terminals on the clock generator 200 are connected to low; and the astable, negative trigger and connected high. Therefore, integrated circuit 200 acts as an astable multivibrator, the output of which is provided on line 201 and a frequency of a halved submultiplier appears on line 210 connected to flip-flop 203, as indicated above. Thus, the output of line 201 is the primary clock frequency; the output of line 14 (point AA) is the result of the first division of the primary clock frequency produced by the division circuit 13; and the output of line 208 (point BB) is the result of the second division of the clock frequency produced by the division circuit 19. The frequency of the clock generator 12 is determined by the values of a capacitor 211 and a resistor 212 connected between capacitor and resistor terminals respectively and the common RC. terminal of the astable multivibrator 200. The frequency can be adjusted by changing the resistance value of the resistor 212. In the illustrated embodiment, the resistance is about 2M ohms and the capacitor is about 100 pf; the clock frequency can therefore be adjusted to be around 6.82k Hz. A zener diode 213 is connected between the capacitor terminal of the multivibrator 200 and ground to cause the oscillator frequency to decrease with decreasing battery voltage.

The data of the external instruction means (described below) is received by a magnetically activated reed coupler 215 and fed to the single pulse digital generator 151 (Fig. 3A). The pulse generator 151 ensures that the pulse received from the reed coupler 215 is of correct shape and width for processing in the remaining portion of the circuit and includes two D-type flip couplings 220 and 221, a binary counter 222 of the type is referred to as "ripple -carry counter", and an AND circuit 223. The data is fed to the clock input of a D-tilt coupling 220, the D input thereof being connected to high. The output Q of the flip-flop 220 is connected to the D input of the D-flip-flop 221, and the Q-output of the D-flip-flop 221 is passed through the AND circuit 223 to the reset terminals of the flip-flops · 220 and 221. The primary clock pulses that occur at line 201, is also applied to AND circuit 223 to synchronize reset of D-tipping couplings 220 and 221. The Q output of D-tipping coupling 220 is connected to a reset terminal of counter 222. Counter 222's clock terminal is connected to line 201 to receive primary clock pulses. from here. The output of counter 222 is taken from e.g. the output and supplied to the clock terminal on the D-tilt coupling 221.

Thus, when a data pulse is received from the coupler 215, it serves to enter the high state of the D-terminal to the Q output, and therefore to the D input of the flip-flop 221. When the Q output assumes a high state, Q-12 assumes

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the output low state, thereby removing the high reset state from the counter 222 so as to enable it to begin counting the clock pulses supplied thereto on line 201. When output line Q assumes high state (at 6 ^ 2 times the clock frequency divided by two, seconds), the high state of the D input of the tilt coupling 221 will be clocked through to the Q output thereof for supply to an input of the AND circuit 223. Upon arrival of the next clock pulse on line 201, the high state will be applied to the reset terminals of the tilt couplings. 220 and 221 and return these to their initial state. Thus, the pulse occurring on the output line 230 will have a constant width established at the time the output signal Q 1 from the counter 222 is to assume a high state from the time the pulse is received from the coupler 215. The output pulse amplitude on the line 230 will be constant. equal to the amplitude of the high state.

The output of the digital single pulse generator is applied to the start lock circuit 152 (Fig.3A). The start lock circuit 152 includes a J-K master-slave toggle switch 235 to whose clock input the output of digital single pulse generator 151 is applied. The K input 235 of the coupling 235 is connected to; low, and the .T input is connected to the Q output. Therefore, the Q output is high continuously after receiving the first clock pulse until the tilt coupling 235 is reset. The reset terminal is connected to the stop lock circuit 167 (Fig.3B), which is described below. The Q output of the flip-flop 235 is connected to one input terminal of a NAND circuit 156 and the data generated on the pulse generator 151's output line 230 is fed to the other input terminal. The output signal of the NAND circuit 156 is applied to the switch register 165 (Fig. 3B) and one input terminal of the NAND circuit 170 (Fig. 3G) for transmission to the data counter 182 (Fig. 3C), as described below.

The Q output of J-K flip-flop 235 is applied to reset circuit 155 (Fig. 3B), which includes two flip-flops 240 and 241 of the D type. The D-input of the flip-flop 240 is connected to high and the output of the line 239 |

from the start lock circuit is connected to the clock input. When the condition of the cord I

239 thus switching from low to high, the high state is transmitted on the D input | to the Q output of flip-flop 240 to appear on the D-input of flip-flop 241. The clock terminal of flip-flop 241 is connected to receive \ primary clock pulses appearing on line 201. Upon activation of the start in locking circuit 235, the high state of the flip-flop is applied. 240's D input, | by the occurrence of a clock pulse, through the Q output of the tilting coupling 241 to produce a high reset state on the output line 243 which! is connected to the reset terminals of the tilt coupling 240, the shift register j 165, the activation lock circuit 176 (Fig. 3C), the pattern search stop lock 166 (Figs.

3C) and the data counter 182 (Fig. 3C), as described below. Reset pulse 13

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however, is of self-limiting duration and terminates when it appears on the reset terminal of the tilt coupling 240 after the occurrence of a subsequent primary clock pulse on line 201.

The Q output of the starter latch switch 235 (Fig. 3A) is connected to the reset terminals of the counter circuits in the counter 162 (Fig. 3B). The counter 162 includes a binary counter 258, the type known in English as a "ripple-carry counter", a corresponding binary counter 259, and an AND circuit 260.

Both counters 258 and 259 are reset by the Q output of the start lock switching switch 235. Thus, when the start lock circuit 235 is activated, it is usually removed at the reset terminals of counters 258 and 259, and counter 162 is initiated.

The primary clock pulses on line 201 are connected to the clock input of counter 259, and those on leads Q1, Qg and developed output signals are applied to the shift register 165 (FIG. 3B), pattern search stop latch 166 (FIG. 3C), and counter 258's clock terminal, respectively. . Thus, the output signals from counter 259 appear as submultiples of the clock frequency of line 201; for example, since the clock frequency is about 6.82 kHz (with a period of about 0.1466 milliseconds), for example, the pulses on line Q have. a period of approximately 4.69 milliseconds, the output signals of the line Qg a period of approximately 75.07 milliseconds, and the output signals of the line a period of approximately 600.58 milliseconds.

The output of the output terminal of the counter 258 is connected to one terminal of the AND circuit 260, and the output of the line is connected to its second input. Since the counter 258 receives its clock pulses from the Q ^ output of counter 259, the output signals and from the counter 258 at the output of the AND circuit 260 will shift from low to high state for a period of about 5,405.28 milliseconds. The data received at coupler 215 will be received with a frequency period appearing at output terminal Q1. for the counter 259, or 4.69 milliseconds. Therefore, the change in the state of the output of the AND circuit 260 will be 1152 data pulses after the counters have been allowed to begin their count, for activating the stop lock circuit 167 (Fig. 3B), as described below.

In operation, the circuit first seeks a password pattern in the pulses received by the input switch 215. For this purpose, there is a pattern recognition circuit 270 (Fig. 3B) including a shift register 165 and a pattern recognizing NAND circuit 172. The output signal of the counter 259 is applied to the clock input. the shift register 165. The data generated by the single pulse generator 151 (Fig. 3A) is supplied through the NAND circuit 156 to the "data" input of the shift register 165. The data is entered into the shift register 165 14

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with the frequency of the pulses produced at the terminal of the counter 259. Thus, it appears that if the pulses transmitted to the circuit are not of the frequency produced on the line of the counter 259, the data will not be properly entered into the shift register 165, and they will not be recognized by the pattern recognition circuit 172 described below. Therefore, this clock condition imposes a frequency requirement on the input data, in addition to the other conditions j (especially the pattern of high and low states), thereby increasing the statistical security against inadvertent activation of the parameter determining code circuit.

When the data is entered into the switch register 165, it appears on the output terminals Q ^, Q2, Q3, Q ^, Q5, Qg and Q7 · The output terminals 165 of the shift register 165 are connected to the input terminals of the NAND circuit 172. If desired, various of the shift register 165's output lines can be inverted, e.g., by inverting circuits 272 and 273, thereby providing the opportunity for unambiguous encoding of the required recognition pattern for the circuit.

The NAND circuit 172 produces a low output signal only when all the input signals thereto are coincident. Thus, only at the time when the output signals from the switch register 165 correspond to the predetermined password will they produce a state change on the output terminal of NAND circuit 172. The NAND in the circuit IVlfs output signal is inverted by the inversion circuit 274 and an input to the NAND circuit 174 is applied.

After a sufficient period of time to recognize the access pattern, the circuit is cut off to continue its access pattern search by a pattern search stop lock 166 (Fig. 3C). The pattern search stop circuit 166 includes j a J-K master slave toggle switch 276 which receives the clock input signal from the count! in the clay 259's output Qg. The K input 276's K input is connected to low, and: The J output is connected to the Q output. Thus, upon receiving a clock pulse at the clock input, the Q output signal will change from normally low to high state, where it will remain until the tilt coupling 276 is reset. The Q output is connected to the second input of the NAND circuit 174 to prevent further transmission of signals from the pattern recognition circuit 270 therethrough. As the clock input 276's clock input signal is derived from the output switch 259's output

pedestrian terminal QOJ, the pattern search stop will be activated approximately 37.55 y y I

milliseconds after the start lock 152 has been activated. This corresponds to a j period which includes 8 data bits transmitted at a rate determined by the output Q ^ of j counter 259. Thus, once the access pattern search has begun, you will, if it is not recognized within the first 8 pulses, discontinue its search and will not accept additional data until the time required for a complete program cycle has elapsed.

Immediately prior to the activation of the pattern search lock 166, the output 15

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the signal from the pattern recognition circuit 270, if the access pattern is recognized, is applied through the NAND circuit 174 to activate the locking circuit 176 (Fig. 3C), which includes a JK master-slave flip switch 280. The flip switch 280's K input is connected to low and the Q output is connected to the J input. The signal from the pattern recognition circuit is applied to the clock input. Thus, once the activation pulse pattern is recognized, the activation lock produces a high state output signal at its Q output terminal, which continues until reset. The Q output terminal of the flip-flop 280 is connected to one input of the NAND circuit 170 for controlling transmission of the data transmitted through the port 156. The Q-output of the flip-flop 280 is further connected to an input of the AND circuit 180 for comparison with the output signal. from the stop lock circuit 167 (Fig. 3B), as described below. Thus, once the activation lock 176 changes state upon recognition of the access pattern, the data from the flip switch 230 is thus applied to the data counter circuit 182 (Fig. 30).

Data counter 182 includes a counter 291 of the kind referred to in English as a "ripple-carry counter". The data from the pulse generator 151 for single pulses (Fig. 3A) is applied to the clock input of the counter 291. As the data is entered into the counter 291, the output states Q ^ -Q ^ q thus reflect the number of pulses received. It should be noted that the output signal produced at the terminals is the binary equivalent to the number of pulses received at the clock input with the most significant digit located on line Q ^ q.

The data on the wires Q1 -Qg1a counter 291 is connected directly to the data storage circuit 184 (Fig. 3C). The data storage circuit 184 includes a locking circuit 295 and two D-type flip couplings 290 and 292 for storing associated signals. The different outputs Qj "Qg of the counter 291 are connected to the various data inputs of the lock circuit 295, whose storage terminals are connected to the output of the AND circuit 180, which, as described above, receives its input signals from the outputs of the stop lock circuit 167 (FIG. 3B) and the activation lock circuit 176 ( The Qg and Q1 Q outputs of the counter 291 are connected to the respective D inputs of the flip couplings 290 and 292, respectively. The flip couplings 290 and 292's Q outputs provide two additional control data states in points EE and FF.

The stop lock circuit 167 includes two flip-flops 300 and 301 of the D-type. The primary clock pulses on line 201 are fed to the clock input of the tilt coupling 301, and the Q ^ and Q ^ outputs of the counter 258 are connected as indicated above through the AND circuit 260 to the clock input of the second tilt coupling 300.

The tilt connector 300's D input is connected to high and the Q output is connected to the D input of the tilt connector 301. The tilt connector 301's Q output is

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16 is connected to one of the input terminals of the AND circuit 180 and to the reset terminal of the tilt coupling 300.

Thus, when all the data received by the circuit within the time period defined by the change in state of coincidence at the outputs Q and Q of the counter 258 is received, the stop lock circuit 167 and the activation lock circuit 176 (Fig. 3C) produce a signal to the "storage terminals" on the locking circuit 295 (Fig. 3C), thereby entering the data appearing on the data terminals thereto. The data will then be stored in the locking circuit until another signal set including a correct password is then supplied to the circuit. The output signals obtained on the locking circuit 295 are then available in

for transfer to various modification circuits for changing function I

the parameters of the cardiac pacemaker in connection with which the circuit is used.

The schematic electrical diagram of the pulse generator 21 (see FIG. 1) is shown in detail in FIG. 4. The pulse generator 21 acts as a voltage multiplier circuit and includes two npn transistors 310 and 311. The transistor 311's collector and emitter series connect one side of a capacitor 313 to the output line 22 through a capacitor 314. A resistor 316 connects the base of transistor 311 to a negative terminal. 190, and a resistor 322 connects transistor 311 collector to ground terminal 191 to reverse the bias of transistor 311 collector base transition.

The side of capacitor 313 connected to the emitter of transistor 311 is further connected to a negative potential of terminal 190 through a resistor 318. The opposite plate of capacitor 313 is connected to the collector of transistor 310 and to a ground potential 191 through a resistor j 320. The emitter of transistor 310 is directly connected to negative terminal 190. Thus, when transistors 310 and 311 are in their normally non-conductive | condition, capacitor 313 is charged as indicated by the voltage between | in negative terminal 190 and ground terminal 191 through resistor 318 and>

320. I

When the transistor 310 is biased in state as indicated below, the negative potential of its emitter is series connected to the previously charged capacitor 313, thereby multiplying the voltage developed between the emitter and ground of transistor 311 . In addition, this increased negative potential biases the base-emitter transition of transistor 311 in the through direction and causes it to conduct so that the multiplied voltage is delivered to output line 22, as described above. j

A zener diode 324 is connected between the output line 22 and ground 191 in order to protect against defibrillation and other undesirably high voltages that may occur. come.

DK 151935 B

17

The generation of the stimulation pulse is as indicated above controlled by the supply of a base current to the transistor 310. This base current is provided in a resistive path in series between the base of the transistor 310 and the output of the NAND circuit 327. The input signal of NAND 327 is derived from the output of the width control circuit 17 (see Fig. 1), as described below in detail.

The resistance of the resistive path and, as a result, the base current of the transistor 310 is controlled by an amplitude control circuit 24. The amplitude control circuit 24 includes three resistors 326, 329 and 330. The resistors 329 and 330 are connected in parallel with the resistor 326 by bilateral couplers 332 and 333 respectively. Couplers 332 and 333 receive digital function signals on the wires II and JJ, respectively, which are derived from the output of the data storage circuit 295 in the main parameter control 150 (see Fig. 3C). In operation, the presence of a logic signal 00 on the respective terminals II and JJ results in the full magnitude of the resistor 326 being presented to control the base current of the transistor 310. The presence of a logic signal 01 on terminals II and JJ will cause coupler 332 to close to produce the resistive value of the parallel connection of resistors 329 and 326 in the base circuit. The presence of logic signal 10 on terminals II and JJ will cause coupler 333 to close to form the parallel coupling of resistors 330 and 326 in the base circuit. Finally, the presence of a logic signal 11 on terminals II and JJ will cause both couplers 332 and 333 to close to form the parallel connection of all three resistors 329, 330 and 326 in the base circuit. The collector-emitter current of transistor 310 is thus controlled by the logic value presented at terminals II and JJ.

The degree to which transistor 310 is biased to a line, as controlled by the logic state of terminals II and JJ, determines the amplitude of the output pulse delivered to output line 22. I.e. the voltage drop between collector and emitter determines the voltage that occurs in series with the voltage previously applied to capacitor 313.

Output line 22 serves, in addition to providing stimulation pulses from pulse generator 21, as described above, also to conduct naturally generated heart pulses on line 33 to the detection portion of cardiac pacemaker 10. A resistor 340 is connected in series with a capacitor 341 for a non-inverting input. on an operational amplifier 343. The resistor 340 and capacitor 341, in addition to coupling the signal to the input, serve as a low frequency filter, the capacitor 341 presenting a high impedance to DK 151935 B! The low frequency components of the detected signal on line 22. A diode 344 is connected from the common point between resistor 340 and capacitor 341 to a ground terminal 191 for fixing the amplitude of the stimulation pulse to an acceptable voltage to prevent the control of amplifier 343.

A resistor 346 is connected in series with a capacitor 347 between a ground terminal · 191 and an inverting input to an operational amplifier 343.

A feedback resistor 349 is connected between the output of the amplifier 343 and its inverting input. Resistor 346 and capacitor 347 also serve as a low frequency filter against the signal produced at the output of operational amplifier 343. A forward compensation capacitor 350 is provided to determine the high 3dB frequency waste point. Finally, the non-inverting input of amplifier 343 is connected to a voltage divider comprising two resistors 352 and 353 connected in series between a negative terminal 190 and an earth terminal 191. An offset balance resistor 355 is connected between the ground terminal 191 and an offset balance terminal of the amplifier 343. to the grid of a field power transistor 356 for controlling the source-drain current therethrough. Thus, upon receipt of a naturally generated heart pulse (or other signal of corresponding frequency), the amplifier 343 produces an output voltage to connect the field effect transistor 356. The extent to which the field power transistor 356 is connected depends on the output voltage of the amplifier 343, which is again determined by the amplitude of the signal sensed on the line 22.

in

The sensitivity of the pacemaker 10 to the signal produced by | The R-wave amplifier 32 is controlled by the sensitivity control circuit 35 (see Figure 1). The sensitivity control circuit 35 includes a NAND circuit 358 in whose inputs are connected to the output terminals GG of the data storage lock 295 1! (ie Fig. 3C). The output of the NAND circuit 358 is connected to a control terminal |

on a bilateral coupler 359 connected in parallel to a Schottky diode 361. J

!

Another terminal HH of the locking circuit 295 (Fig. 3G) is connected to one! in second bilateral coupler 362 connected in parallel with a silicon diode 364. j

Furthermore, the anode of diode 361 is connected to a ground terminal 191, and diode j i

The cathode 364 is connected to the source of the field power transistor 356. A resistor j 365 is connected between the field power transistor 356 and a negative thermal current.

nal 190. Thus, a current path is defined from ground terminal 191 through diodes 361 and 364, source and drain for field power transistor 356, and resistor 365 to negative terminal 190. Since the throughput resistance of Schottky and silicon diodes 361 and 364 is of the order of magnitude. about 0.2 and 0.7 ohms, respectively, the current through resistor 365 can reach the field power transmission! the resistor 356 is in a conductive state, controlled by operation of one or 19

DK 151935 B

the second, neither or both of the bilateral couplers 359 and 362. If, for example, logic signal 00 is applied to the respective terminals GG and HH, the bilateral coupler 359 is switched on and the bilateral coupler 362 is disconnected to provide a current path from the ground terminal 191 through coupler 359 and diode 364 to source field transistor 356. A logic signal 01 on terminals GG and HH connects both couplers 359 and 362 so that the two diodes 361 and 364 are bypassed in the current path from the ground terminal 191 to the source. A logic signal 10 at the respective terminals GG and HH disconnects coupler 359 and coupler 362, providing a current path through the two diodes 361 and 364 of the ground terminal 191 to the source. Finally, a logic signal 11 on the input terminals GG and HH disconnects coupler 359 and coupler 362, thereby providing a current path from ground terminal 191 through diode '361 and coupler 362 to the field power transistor 356. Thus, by supplying an appropriate logic signal to terminals GG and HH, the potential applied to the source power transistor 356 can be adjustably adjusted to determine the voltage level at which the field power transistor 356 is connected. When the field power transistor 356 is connected, a voltage is applied across the resistor 365 which is applied to an input of a pair of inverting circuits 370 and 371 for supply to the control counter 38 (see Fig. 1).

The control counter circuit 38, the refractory controller 43, the reset circuit 41 for the asynchronous generator, the asynchronous interval generator 15, the asynchronous frequency controller 16, and the width control circuit 17 shown in FIG.

1 is indicated in more detail in FIG. 5A and 5B. Pulses representing the first shared clock pulses, at a frequency divided by one quarter from the primary clock pulses originating from the clock generator 12 (see Figure 3A), are fed to the various circuit components of line 14, as shown.

The output of the R-wave amplifier 32 is fed by line Z to a reset terminal of the control counter 38, as shown in FIG. 5A. Thus, when the R-wave amplifier 32 detects a suitable signal, the control counter 38 is applied to a reset signal. The first set of split clock pulses on line 14 is transmitted to an input of NAND circuit 40 whose output is connected to the clock pulse of counter 38. Counter 38 which is of the type referred to in English as a "ripple carry counter", generating output signals at the various respective output terminals, which correspond to a predetermined corresponding number of clock pulses applied to its clock terminal. The primary function of the control counter 38 is, as briefly mentioned above, to define a refractory state or control interval during which a naturally occurring cardiac pulse has no reset effect, and after which receiving such a pulse produces a reset pulse, indicating , at

DK 151935B

20 the heart is functioning properly. There are two selectable output lines from the counter 38, one being the output line 373 from the Qg output and the other being the line 374 from the Qy and Q ^ Q outputs through the AND circuit 376. The signals on the wires 373 and 374 represent a state change corresponding to clock pulses of q 10 7 (2: 2 =) 256 and ((2 + 2): 2 =) 576. The clock pulses of line 14, of a duration of approximately 0.587 milliseconds, produce state changes on line 373 and 374 after 150, respectively. , 15 milliseconds and 337.83 milliseconds. Thus, there is access to a choice between the respective state change times on wires 373 and 374 to determine the pacemaker's refractory period. The choice between the signals on lines 373 and 374 is made by a multiplexer 377. Line 373 is connected to the 0 input and line 374 is connected to the 1 input of multiplexer 377. An A input is connected to terminal Qg (NN) of

the locking circuit 295 (Fig. 3C) for transmitting a signal thereon to the multiplexer 377. The truth table of the multiplexer 377 causes the input of the zero input to the A terminal to transmit the signal at the O input terminal to the output terminal of conduit 379. applied to the A terminal connects the signal at the 1 input to the output line 379. The output of the Q Q output (Fig. 3G) output representing the refractory control I

° in the signal, therefore, determines whether the refractory period of the circuit is 150.14 milliseconds, as determined by the signal on line 373 or 337.83 milliseconds, as determined by the signal on line 374. The output of multiplexer 377 on line 379 is fed to an inverting NAND circuit 45, whose output is connected to the reset circuit 41 of the asynchronous generator and to one of the terminals of the NAND circuit 40 at the input of the control counter 38. In operation and after the counter 38 is reset, it begins to count clock- | pulses applied to its clock input through the NAND circuit 40. When it reaches the predetermined number of the selected output line 373 or 374, an output signal on the line 379 is generated to the inverting NAND circuit 45, thereby producing a state change on output line 382 from one! normal high state to a low state. After the state change on line j 382, NAND circuit 40 is cut off from allowing additional clock pulses to pass into counter 38, thereby stopping its count. The control counter 38 is | therefore brought to abort its count until reset by one in it | the following received impulse from the R-wave amplifier 32. j

In addition to the output signals at terminals Qg, Qy and output, an output signal appears on the terminal of counter 38, which signal 'is transmitted to reset circuit 41 of the asynchronous generator, as described immediately below.

DK 151935B

21

Reset circuit 41 for the asynchronous generator includes two D-type toggle couplings 384 and 385. The D input of the flip-flop 384 is connected to the high state, and the Q output thereof is connected to the D-input of the flip-flop 385. The Q output of the flip-flop 385 is connected to the reset terminal of the flip-flop 384, and the Q output of the flip-flop 385 represents the output of the reset circuit 41 of the asynchronous generator, which signal is to be transmitted to one input of the NAND circuit 30 (Fig. 5B). The output signal of the NAND circuit 45 on line 382, which represents the selected refractory period signal, is applied to the clock input of the tilt coupling 384. The output of the counter terminal is applied to the clock input of the second tilt switch 385.

Thus, when the counter 36, when the pacemaker is in operation, is reset, it begins its count and first reaches a number which produces an output of the terminal Q ^ such that the high state of the D input thereof is clocked through to the D input. on the tilt coupling 385.

When the counter 38 then reaches the count of the selected output of line 373 or line 374, a clock pulse is applied to the clock input of the tilt coupling 385, thereby producing a state change on its outputs, with the Q output shifting from low to high state and the Q output. switches from high to low mode. The change in output signal from high to low state on the Q output supplied to NAND circuit 30 (Fig. 5B) defines the reset signal for output to asynchronous interval generator 15 (Fig. 5B).

Thus, it will be appreciated that if a reset signal is received at the reset terminal of counter 38 before it reaches the count of the selected output line 373 or 374, the counter will reset to begin its count completely again without generating an output pulse from the toggle switch 385. position condition can be extended indefinitely if, for example, a disturbing signal is caused to continuously reset the counter 38 within the refractory period determined by the main parameter controller 150. After the predetermined count is reached, the toggle switch 385 produces has been "armed" with the signal at the terminal Q ^ of the counter, however, a reset signal at the output terminal Q from the tilt coupling 385.

At this point, it should be noted that the formation or non-formation of a reset signal from the reset circuit 41 of the asynchronous generator regulates the demand function of the total pacemaker circuit 10. Thus, for example, no reset signal is generated, the asynchronous intervals allow the rator 15 to count continuously, stimulation signals are generated at the predetermined frequency selected.

There is a NAND circuit 387 whose output is connected to reset 22

DK 151935 B

the terminal of the flip-flop 385. One input of the NAND circuit 387 is connected to an inversion circuit 216 (see Fig. 3A). The second input to the NAND circuit 387 is connected to the output Q (FF) of the D kiocoby ring 292 ffig. 3C). Thus, if the reed coupler 215 (Fig. 3A) is closed due to, for example, the proximity of a magnet for test purposes or other purposes, a high output state of NAND circuit 387 is produced to continuously apply a reset voltage to the tilt coupler 385, thereby the formation of reset pulses is inhibited, causing the pacemaker circuit 10 to operate asynchronously. Furthermore, the presence of an O signal on the output Q (FF) of the tilt coupling 292 will also produce a constant reset voltage at the output of the NAND circuit j 387, thereby limiting the pacemaker circuit 10 to asynchronous operation or fixed frequency operation.

The reset signal from the reset circuit 41 of the asynchronous generator supplied to the NAND circuit 30, as described above, is transmitted through a line 388 to a reset terminal of the asynchronous interval generator 15 (Fig. 5B). The asynchronous interval generator 15, of the type referred to in English as a "ripple carry counter", receives clock pulses on line 14 to the clock terminal for generating output signals at various output terminals thereon. For example, in the illustrated embodiment, the output signals are derived from the terminals The output signals themselves are logical combinations of selected outputs, the choice of one of which may be used to determine the asynchronous interval frequency of the pacemaker circuit 10. More specifically, the output signals of the Qy-sQg and Q1 Q terminals on the counter 15 are combined by an AND circuit 390 to produce a change in the output state after about 489.41 milliseconds. The output of AND circuit 390 is applied to input 7 of a multiplexer 391. The output signals of terminals Qg, Qg, Qg and combined by an AND circuit 393 to produce a change in output state after approximately 544.29 milliseconds. The output of the AND circuit 393 is connected to the input terminal 6 of the multiplexer 391. The output terminal Q1 of the counter 15 is connected directly by a line 394 to the input 5 of the multiplexer 391 and provides a signal that changes state after approximately 600.58 milliseconds. The output terminals Qg and are combined by an AND circuit 395, the output of which is connected to the input terminal 4 of the multiplexer 391, and which produces a state change after approximately 675.66 milliseconds. The output terminals Qg and Q1 are combined in AND circuit 396, the output of which is connected to the input terminal 3 of a multiplexer 391 to produce a state change after about 750.73 milliseconds. The terminals Qg, Qg and Q are combined in AND circuit 397, the output of which is connected to 23

DK 151935 B

the input terminal 2 of the multiplexer 391 and produces a state change after about 825.81 milliseconds. The terminals Qg and Q are combined in an AND circuit 398, the output of which is connected to the terminal 1 of the multiplexer 391, which produces a state change after about 975.96 milliseconds. Finally, the output terminal is connected directly to the input terminal 0 of the multiplexer 391 through line 399 and a state change is produced after about 1201.17 milliseconds.

The control terminals A, B and C of the multiplexer 391 are connected to three corresponding frequency control terminals, Q 1, Q g and Q y (KK, LL, MM) on the locking circuit 295 (see Fig. 3C). The control signals which determine which of the inputs 0-7 are connected to the output line 400 are in accordance with the truth table given below: ABC OUT.

0 0 0 0 0 0 1 1 0 10 2 0 113 10 0 4 10 1 5 110 6 1117

Thus, the output time of one of the various multiplex lines is selected by a logical signal at the input terminals of the multiplexer, and the pacemaker circuit 10's asynchronous frequency can therefore be selected from any of the times stated above.

The output of line 400 from multiplexer 391 is transmitted to the width control circuit · 17 as follows. The width control circuit 17 includes two J-K master slave tilt couplings 402 and 403. The tilt input 402's J input is connected to high and the K input is connected to low. The Q and Q outputs of the flip-flop 402 are respectively connected to the J and K inputs of the flip-flop 403. The Q-output of the flip-flop 403 is connected to the reset terminal of the flip-flop 402, and the Q-output of the flip-flop 403 is the output of the width control circuit 17. The signal on the line 400 from the multiplexer 391 constitutes the clock signal for the tilt coupler 402 which, upon occurrence thereof, produces a high state at the output Q and a low state at the output Q. The output of a width determining multiplexer circuit (described below) is connected to 24

DK 151935 B

the clock input of the flip-flop 403 for clocking the input signal at the J-K terminals of the output terminals Q and Q. Specifically, multiplexer 405 receives a first set of shared clock pulses from line 14 of the O input terminal. Furthermore, it receives a second set of shared clock pulses with a different shared frequency from the tilt coupling 204 (Fig. 3A) from line 208 (BB) of the 1 input terminal. The control terminal A receives its input signal from the width control signal on the Q output (EE) of the D-tilt coupling 290 (Fig. 3C). Depending on whether the signal on the control terminal is high or low, it is thus determined whether the clock pulses on the input terminals 0 and 1 are applied to the output terminal on line 406 for j output to the clock terminal on the tilt coupling 403. It will be seen that the choice of clock! The lower frequency pulses produce a longer change of state on the output Q of the tilt coupler 403 than the higher frequency clock pulses on the input line 0 of the multiplexer 405, thereby providing the possibility of controlling the width of the pacing pulse produced by the pacemaker. The output of the flip-flop 403 on the Q output is transmitted along line 408 to provide the drive signal to the pulse generator circuit 21 (Figures 1 and 4). The output of the flip-flop 403 on the Q-terminal is further connected to one of the inputs on the NAwD circuit 30 to generate an additional reset signal to the asynchronous interval generator 15. Thus, when generating an asynchronous signal generator, the asynchronous interval generator is reset to reinitialize its time interval for the next intervening asynchronous.

The external control means indicated by the general reference numeral 500 for generating and transmitting the password and the pulses for determining the parameters of the pacemaker 10, as described above, are shown in detail in FIG. 6A, 6B, 6C and 6D. The connections between the figures are indicated by corresponding letters. Unlike the above with reference to FIG. 1-5 for the implantable pacemaker 10 circuit shown in FIG. 6A-6D, as will be apparent, designed with a ground level representing a 0 or a low 1 logic state and a + v representing a high logic state or 1.

The external control means 500 includes four main parts, each framed in dotted line. An oscillator portion 501 (Fig. 6B) produces clock pulses to the remaining portion of the external regulator circuit. The password generator 502 (5B) generates a special sequence of access pulses into the main parameter control circuit 150 (Figures 1 and 3A-3C). A parameter code in generator 503 (Fig. 6C) produces an adjustable number of pulses, each number corresponding to an individual set of selectable pacemaker parameters. Finally, a pulse output circuit 504 (Fig. 6D) generates electromagnetic pulses for transmission to the master parameter controller in accordance with the password generator 502 and the parameter code generated by the parameter code generator 503.

DK 151935B

25

More specifically, the clock pulse generator 501 (Fig. 6B) is activated by closing coupler 507 (Fig. 6A). Coupler 507, when moved from an upper position 508 to a lower position 509, changes from a low to a high state on the output line 510 from a bead-free contact circuit generally indicated by reference number 512. Upon return of the coupler 507 to the upper position 508, the state of line 510 is changed from high to low, thereby activating a monostable multivibrator 515 which, as described below, produces a reset signal on line 525 to the various circuit elements of the regulator and a subsequent start pulse.

The bead-free contact circuit 512 includes two NAND circuits 516 and 517 as well as the monostable multivibrator 515 connected so that it cannot be triggered after the initial trigger signal is received.

The one input of the NAND 516 is connected through a resistor 519 to a positive terminal 520 to establish a normal high state thereof. This terminal is further connected to the starting switch 507's upper terminal 508. The second input of the NAND 516 is connected to the output of the NAND circuit 517.

Similarly, one input of the NAND circuit 517 is connected by a resistor 521 to a positive terminal 520 and further to the lower terminal 509 of the coupler 507. The second input of the NAND circuit 517 is connected to the output of the NAND circuit 516. The output of the NAND circuit 517 is the output of the circuit and is connected to the monostable multivibrator 515.

As shown, the monostable multivibrator 515 is activated by a negative-going pulse (i.e., a high-to-low-state pulse). In the event of such a state change, the output Q is changed from low to high state where it remains for a period of time which depends on the value of a resistor 523 and a capacitor 524 connected from the RC terminal to R and C, respectively. -minalerne.

The R-terminal is connected to the positive terminal 520. The positive trigger input is connected to the Q-output to enable the monostable multivibrator 515's (negative-going) rear flanking with non-repetition, as mentioned.

It will therefore be appreciated that by applying a negative signal to the trigger input of multivibrator 515, the Q output will switch from low to high state, during which a reset signal is output to the various circuit components of line 525 as described below to provide the an initial starting state for this. Since the output Q of the multivibrator 515 has remained in the high state for the time determined by the time constant determined by the capacitor 524 and the resistor 523, that state changes from high to low. This change of state triggers another monostable multi- 26

DK 151935 B

vibrator 527 (Fig. 6B), which produces a signal for a J-K master-slave flip coupler 528 which serves as a starter lock circuit.

Similarly, the monostable multivibrator 527 is connected to the monostable multivibrator 515 for triggering a negative-going impulse applied to the mini-trigger input for a period of time defined by the RC time constant of the capacitor 530 and the resistor 531 connected from the RC. the terminal to the C and R terminals, respectively. Furthermore, the R-terminal is connected to a positive terminal 520. The positive trigger input is connected to the Q-output to provide the non-repetitive power of monostable multivibrator 527.

The tilt clutch 528 * s .T-K inputs are connected to low, along with the clock input. The output of monostable multivibrator 527 is connected to the still terminal and the output signal is derived from the Q terminal. The reset terminal is connected to the output of a pulse generator 532 which produces a pulse upon completion of the pulse generating sequence of the control circuit 500, as described below in detail. The output of the terminal Q of the flip-flop 528 provides an activation signal of line 534 to the clock pulse generator, 501.

The clock pulse generator 501 includes a 14-step ("ripple carry") binary counter / divisor and oscillator 536, a decad counter 537 and three NAND circuits 539, 540 and 541. Oscillator / counter 536 and decad counter 537 each have reset terminals connected to reset terminals. 525, as described above. The oscillator / counter 536's clock and inverted clock terminals (0 and γ) are interconnected by a series connection of capacitor 543, a fixed resistor 544 and a variable resistor 545. Another fixed resistor 547 is connected from the common point of capacitor 543 and resistor 544. to the one input of the NAND circuit 539. The second input of the NAND circuit 539 is connected to the output of the start lock chip coupling 528 with the wire 534. The output Qg of the oscillator / counter 536 is connected to an inverting NAND circuit 540 to provide clock pulses to the password generator 520. as described below.

The frequency derived from oscillator / counter 536 terminal Qg corresponds to the internal clock frequency of the pacemaker, with which the received access and parameter control codes are entered into the various registers. This clock frequency is derived from the counter 259's (Fig. 3B) Q ^ output.

The terminal Qg is connected to the clock input of the decoder counter 537 and one input of the NAND circuit 541. The output of the NAND circuit 541, which represents the clock pulses produced on the Qg terminal of the oscillator 536, is fed to one input terminal of the NAND circuit 577 ( Figure 6C) and to the beat

DK 151935B

27 the input of counter 558 (Fig. 6C). Decade counter 537's "e" term is connected to the clock activation input, thereby inhibiting decode counter 537's count after reaching "6". The "6" terminal of counter 537 is also connected to a second input of NAND circuit 541 and to various quiescent and reset terminals of parameter code generator 503 (FIG. 6C), as described below.

In operation, the clock pulse generator 501 will produce pulses as long as the signal on line 534 is in a high state. However, when the signal on line δ "* Λ is in a low state, the clock input signal for counter / oscillator 536 cannot vary, thereby stopping output pulses. Decadence counter 537 serves to switch between password generator output 502 (Fig. 6B) after the password is formed. and output to the output of the parameter code generator 503 (Fig. 6C) for subsequent output to the output, this is accomplished by the NAND circuit 541 which serves to select between the output of the password generator and the following parameter code sequence. 537 reaches the content "6", the input to the NAND circuit from the counter "53 "'s" 6 "output is thus in a low state, thereby inhibiting the passage of the clock pulses on the wire from the oscillator 536. The input signal to the NAND circuit 555 therefore remains due to the high code parameter code sequence, so that only the password generated by the password generator 502 is allowed to be transmitted to the In the output line 556. When the counter 537 reaches the number "6", it is permissible for the tactile pulses produced by the oscillator 536 to the line Q_ to pass the NAND circuit 541 for transmission to the output line 556 through NAND circuits 577, 578 (FIG. 6C) and 555 (Fig. 6B). The high state of the "6" output of the counter 537 continuously produces a reset state of the flip switch 551 in the password generator 502 to produce a continuous high state of its Q output, allowing the parameter code sequence to pass the NAND circuit 555, as described below.

The password generator 502 includes three J-K master-slave flip couplings 550, 551 and 552. The flip-flop 550's J and K inputs are connected to the flip-flop 552's Q output. The Q and Q outputs of the flip-flop 550 are respectively connected to the J and K inputs of the flip-flop 551, and the Q-and-Q outputs of the flip-flop 551 are again connected to the J-and Q-input of the flip-flop 552, respectively. The reset terminals of the tilt couplings 550 and 552 as well as the tilt terminal of the tilt coupler 551 are connected to the reset line 525. The switch terminals 550 and 552 and the reset terminal of the tilt coupler 551 are connected to the "6" output of the decoder counter 537. The output generator of the password generator is taken from the Q-terminal 551's Q-terminal. In operation, the password generator's flip-couplings 550-552 are thus initialized by the signal on reset.

DK 151935B

28 receive the line 525. Upon receiving clock pulses from the clock pulse generator 501, output Q of output switch 551 will produce the following logical sequence: 1000010 at a frequency that is half the Qg output signal of oscillator / counter 536 (at the same frequency as Q0).

y

The Q output of the flip-flop 551 is connected to one input of a NAND circuit 555. Provided that the second input of the NAND circuit 555 is in high state (that is, until the "6" content of decoder 537 is reached, as will be seen below), the inverted output of line 556 will thus be: 1000010, which is re-inverted by the transmission coil as described below.

As discussed above, the single-pulse pulse generator 151 (Fig. 3A) of the main parameter control circuit 150 produces only an output pulse upon change of the input state from low to high state. Therefore, the code generated by the single-pulse generator in response to a transmitted digital signal of the form 01100010 is 1000010. This is the exact code recognized by the password recognition circuit 270 (Fig. 3B).

Parameter code generator 503 (Fig. 6C) includes a twelve step counter 558, of the type referred to in English as a "ripple carry counter", four BCDs to decimal decoders 559, 560, 561 and 562, two inverting NAND circuits 564 and 565, a NAND circuit 566 capable of comparing at least six inputs and a JK master-slave toggle switch 567. Specifically, the counter receives 558 clock pulses from the output of NAND circuit 541 (Fig.6B) in the form of the clock frequency, . . . 9 produced by oscillator 536, divided by 2. The reset terminal is connected to the reset line 525 and Q- ^ Q-q is connected to the externally controlled parameter selection circuit, as described below. The Q - ^ output is connected to a main stop lock circuit 532, as mentioned above, for stopping the oscillator after the parameter code count is completed. More specifically, the Qj and (^) outputs of the counter 558 are connected to the A and B inputs of BCD to the decimal decoder 559. The C and D inputs of BCD to the decimal decoder 559 are connected to a ground terminal to produce a low state thereon.

A four-position switch 570 has each of its four terminals connected to the 0, 1, 2, and 3 terminals of the BCD to the decimal decoder. The coupler 570's arm is connected to one of the inputs of the NAND circuit 566 with six inputs.

The outputs of the counter 558 are connected to the input terminals A and B of the BCD to the decimal decoder 560, respectively. The C and D j inputs are connected to ground or low state. The 0, 1, 2 and 3 outputs of the BCD to the decimal decoder 560 are connected to the respective terminals of a four-position switch 571. The coupler 571 * arm is connected to a second input of the NAND circuit 566 with six inputs. The output terminals Q ^ -Qg are connected to the corresponding 29

DK 151935 B

inputs A-D on BCD to decimal decoder 561. The outputs 0-7 on BCD numbers the decimal decoder are connected to respective terminals on a coupler 572 with eight positions, the arm of which is also connected to an input on the NAND circuit 566 with six inputs. The output terminal Qq of the counter 558 is connected to the A input of BCD to the decimal decoder 562, and the inputs B-D to BCD of the decimal decoder 562 are connected to ground or to low state. The outputs 0-3 from BCD to decimal decoder 562 are connected to respective contacts in a coupler 573 with four terminals, the switching arm of which is connected to one of the inputs to the NAND circuit 566 with six inputs. The output of counter 558 is connected to an input of an inverting NAND circuit 564 (shown schematically only as an inversion circuit) and to one terminal of a coupler 574 with two positions. The output of the inverting NAND circuit 564 is connected to the second terminal of the coupler 574. The switch arm of the coupler 574 is connected to a second input of the six-input NAND circuit 566. Finally, the output of counter 558 is connected to the inputs of an inverting NAND circuit 565 (shown simply as an inversion circuit) and to one terminal of a coupler 575. The inactivity of the inverting NAND circuit 565 is connected to the other terminal of a coupler 575 with two positions. Coupler 575's shift arm is connected to a sixth input on NAND circuit 566 with six inputs.

The output terminal from the NAND circuit 566 with six inputs is connected to a clock terminal on the J-K flip-flop 567. The flip-flop 567's J and K terminals

• V

is connected to low and high state respectively and the output signal is derived from the Q terminal connected to an input on the NAND circuit 577.

Counter Q8 output of counter 558 is connected to a multivibrator head stop lock 532 (Fig. 6B).

During operation, the various couplers 570-575 are set to correspond to a predetermined set of operating parameters for the pacemaker. For example, in the illustrated embodiment, coupler 570 represents the pacemaker's sensitivity parameter and it can be set to correspond to either the 0, 1, 2, or 3 output terminals of BCD to decimal decoder 559. Similarly, couplers 571, 572 and 573 is set to the respective terminals of the BCD for the decimal decoders 560, 561, and 562 to determine the amplitude, frequency, and refractory period of the pacemaker as desired. Couplers 574 and 575 can be set to determine the desired width and mode of operation of the pacemaker. When each of the output terminals Q 1 -Q presents a state corresponding to the selected decimal number (0-3 for coupler 570, 0-3 for coupler 571, 0-7 for coupler 572, 0-3 for coupler 562, on or off for coupler 574 or on and off for the coupler 575), all of the NAND circuit 566 inputs will be in a high state, thereby producing a low state at the output of the NAND circuit 566. Since the clock pulses at the clock output terminal of 30

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oscillator 536 is applied to output line 556 through NAND circuits 577, 578 and 559, simultaneously generating the decimal equivalent number of pulses on output line 556. Upon the arrival of the following clock pulse, output states Q 1 -Q 2 will not coincide with the selected parameters as determined. of the positions of the corresponding couplers 570-575. The output of the NAND circuit 566 will therefore switch from low to high, thereby producing a low state on the Q terminal of the tilting switch 567. Added to the NAND circuit 577, this low state prevents further transmission of the clock pulses from the output Qg of the oscillator 536. Therefore, the number of pulses delivered to line 556 corresponds to a unique combination or set of desired pacemaker operating parameters.

When the counter 558 reaches the number that produces a high state at the output Q 2, the monostable multivibrator 532 (Fig. 6B) is triggered to produce a reset signal on its Q output line, which signal is applied to the reset terminal of the start lock chip coupling 528 (FIG. 6B). Upon emergence of the reset signal, the Q output signal of switch 528 changes from high to low state, thereby inhibiting further operation of oscillator 536 (Fig. 6B). The monostable multivibrator 532 (Fig. 6B) is connected to produce a pulse of a width which is determined by the magnitude of the capacitor 580 and the resistor 581 connected between the R and RC terminals by triggering a positive-going pulse. and a high state as shown. The Q output signal is connected to the negative trigger to produce a non-retractable state for triggering on a positive going edge.

Referring to FIG. 6D, the access and parameter codes are sequentially output by line 556 to a pair of Darlington coupled transistor pairs 583 and 584 for amplification and transfer to a coil 586 forming an electromagnetic field. The voltage of coil 586 is controlled by a voltage control circuit 587 and its associated external parts. In operation, the coil 586 which produces the electromagnetic field is thus located near the body of the carrier of the pacemaker circuit 10. Upon activation of the starter coupler 507 (Fig. 6A), the password and the following parameter code are generated, and are sequentially delivered to coil 586 to form an electromagnetic field in accordance with this sequence. The electromagnetic field is detected by the reed coupler 215 (Figures 1 and 3A) for controlling the pacemaker 10 in the manner described above.

To ensure that the control circuit 500 is functioning properly, an npn transistor 589 is connected between a positive voltage terminal 590 (which may be derived from the voltage control circuit 587 as shown) and ground. A light emitting diode 592 and a collector resistor 593 are connected in series between the positive wire 590 and the transistor 589's collector. The emitter of transistor 589 is connected to ground potential and the base of transistor 589 is connected to the Q output of the coupling 528. Thus, the Q output of the coupling 528 is switched from

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31 low to high state, the base-emitter junction of transistor 589 is biased in the through-direction so as to allow conduction through light-emitting diode 592 to provide a visual indication of circuit operation.

The circuits described above can be realized with the following special components. The components listed below are given by way of example only, as other components may be used with equal advantage as will be apparent to those skilled in the art.

Integrated Circuits (RCA Type)

Component: Component, Component: 536 CD 4060 537 CD 4017 559,560,561, 562 CD 4028 32

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Gate and inversion circuits (RCA type)

Component Designation 30,40,45 156,170,174, 358,327,387, 516,517,539, 540,541,555, 564,565,577, 578 CD 4011 216,272,273, 274 CD 4069 180,223,260, 376,390,393, 395,396,397, 398 CD 4081 178

transistors

Component Designation 356 (see gate circuit 356) 310,311,589 2N2222

diodes

Component Designation 213 IN 4623 361 5082-2835 344,364 IN 3070

324. IN 756A

resistors

Number Value 212 2 Mohm (variable) 365 3.9 Mohm 355 10 Mohm 352,519,521 1 Mohm 33

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Number Value 353 400 kohm 346 22 kohm 349 6.8 Mohm 340 51'kohm 322 30 kohm 318,320 4.7 kohm 326,329 130 kohm 316,594 10 kohm 330 68 kohm 523,531 200 kohm 593 1 kohm 547 75 kohm 544 1.1 kohm 545 10 kohm (variable)

capacitors

Number 'Value 211 100 pfarad 350 50 pfarad 341 0.1 / pfarad 347 0.22 ^ / farad 313,314 39 / iarad 524,530 0.01 yarad 543 820 pfarad

Claims (8)

Implantable cardiac pacemaker (10) for connection to cardiac contact electrodes (11), comprising means (12) for generating multiple time pulses within a normal heartbeat interval, triggerable means (21) for generating cardiac pacing pulses for delivery to cardiac electrodes, means (15) ) for counting time pulses for a stimulation interval, and then delivering a trigger pulse to the stimulation pulse generating means (21), means (38) for counting time pulses for a refractory interval, means (32) for detecting signals on the cardiac electrodes (11) and for generating a dependent signal for restarting the count in the refractory interval counting means (38), means (41) responding to the detected cardiac electrode signal after the refractory interval count to reset the stimulation interval means (1.5), externally controllable means for independently adjusting the stimulation pulse circuit. (17), the pacing pulse amplitude (24), the refractory interval count (43), the pacing pulse interval (16), the sensitivity of the detecting means (35), and the pacing pulse counter (50) reset, characterized by storage means (184) for storing a series of function parameter control signals the independent adjustment means (17, 24, 43, 16, 35, 50), as well as means (EE-NN) connecting the storage means (184) to the adjustment means (17, 24, 43, 16, 35, 50), for the exercise of the function parameter signals in the storage means so that the function parameters are controlled by these signals. Cardiac pacemaker according to claim 1, characterized by means (503) for generating at a distance from the pacemaker a unique parameter determining signal which uniquely identifies a selectable set of pacemaker function parameters, means (586) for transmitting this signal to the pacemaker, and means. (150) in the pacemaker for receiving this signal and for generating the array of function parameter control signals for storage in the storage means (184). Cardiac pacemaker according to claim 2, characterized in that the means (503) for generating the parameter determining signal contain means (586) for generating electromagnetic pulses and the means (150) in the pacemaker for receiving the signal magnetically actuated reed coupler (215). Cardiac pacemaker according to claim 2, characterized in that the means for generating the signal contain means (503, 504) for generating a selectable number of electromagnetic pulses, the number of which has a correlation to a predetermined unique range of pacemaker parameters. Cardiac pacemaker according to claim 2, characterized by an opening code detection circuit (172, 174, 176) which responds to a predetermined series of signals prior to the unique parameter determining signal, thereby enabling said control signals to be introduced into the storage means (184). Cardiac pacemaker according to claim 5, characterized in that the opening code detection circuit (172, 174, 176) is sensitive only to a predetermined opening code sequence of signals at a particular frequency. Cardiac pacemaker according to claim 6, characterized in that the opening code comprises both high and low logic states. Cardiac pacemaker according to claim 2, characterized in that the means (503) for generating the parameter determining signal contain a clock pulse generator (501) for separating the parameter determining signals and containing clock generator means (12, 162) for receiving the the parameter determining signals at a comparable clock frequency.